From: Glenn Miles <milesg@linux.ibm.com>
To: qemu-devel@nongnu.org
Cc: Glenn Miles <milesg@linux.ibm.com>,
qemu-ppc@nongnu.org, clg@redhat.com, npiggin@gmail.com,
harshpb@linux.ibm.com, thuth@redhat.com, rathc@linux.ibm.com,
richard.henderson@linaro.org
Subject: [PATCH v4 7/9] hw/ppc: Support for an IBM PPE42 CPU decrementer
Date: Fri, 12 Sep 2025 11:47:35 -0500 [thread overview]
Message-ID: <20250912164808.371944-8-milesg@linux.ibm.com> (raw)
In-Reply-To: <20250912164808.371944-1-milesg@linux.ibm.com>
The IBM PPE42 processors support a 32-bit decrementer
that can raise an external interrupt when DEC[0]
transitions from a 0 to a 1 (a non-negative value to a
negative value). It also continues decrementing
even after this condition is met.
The BookE timer is slightly different in that it
raises an interrupt when the DEC value reaches 0
and stops decrementing at that point.
Support a PPE42 version of the BookE timer by
adding a new PPC_TIMER_PPE flag that has the timer
code look for the transition from a non-negative value
to a negative value and allows the value to
continue decrementing.
Signed-off-by: Glenn Miles <milesg@linux.ibm.com>
---
hw/ppc/ppc_booke.c | 7 ++++++-
include/hw/ppc/ppc.h | 1 +
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/ppc_booke.c b/hw/ppc/ppc_booke.c
index 3872ae2822..13403a56b1 100644
--- a/hw/ppc/ppc_booke.c
+++ b/hw/ppc/ppc_booke.c
@@ -352,7 +352,12 @@ void ppc_booke_timers_init(PowerPCCPU *cpu, uint32_t freq, uint32_t flags)
booke_timer = g_new0(booke_timer_t, 1);
cpu->env.tb_env = tb_env;
- tb_env->flags = flags | PPC_TIMER_BOOKE | PPC_DECR_ZERO_TRIGGERED;
+ if (flags & PPC_TIMER_PPE) {
+ /* PPE's use a modified version of the booke behavior */
+ tb_env->flags = flags | PPC_DECR_UNDERFLOW_TRIGGERED;
+ } else {
+ tb_env->flags = flags | PPC_TIMER_BOOKE | PPC_DECR_ZERO_TRIGGERED;
+ }
tb_env->tb_freq = freq;
tb_env->decr_freq = freq;
diff --git a/include/hw/ppc/ppc.h b/include/hw/ppc/ppc.h
index 8a14d623f8..cb51d704c6 100644
--- a/include/hw/ppc/ppc.h
+++ b/include/hw/ppc/ppc.h
@@ -52,6 +52,7 @@ struct ppc_tb_t {
#define PPC_DECR_UNDERFLOW_LEVEL (1 << 4) /* Decr interrupt active when
* the most significant bit is 1.
*/
+#define PPC_TIMER_PPE (1 << 5) /* Enable PPE support */
uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset);
void cpu_ppc_tb_init(CPUPPCState *env, uint32_t freq);
--
2.43.0
next prev parent reply other threads:[~2025-09-12 16:49 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-12 16:47 [PATCH v4 0/9] Add IBM PPE42 CPU support Glenn Miles
2025-09-12 16:47 ` [PATCH v4 1/9] target/ppc: IBM PPE42 general regs and flags Glenn Miles
2025-09-12 16:47 ` [PATCH v4 2/9] target/ppc: Add IBM PPE42 family of processors Glenn Miles
2025-09-12 16:47 ` [PATCH v4 3/9] target/ppc: IBM PPE42 exception flags and regs Glenn Miles
2025-09-12 16:47 ` [PATCH v4 4/9] target/ppc: Add IBM PPE42 exception model Glenn Miles
2025-09-12 16:47 ` [PATCH v4 5/9] target/ppc: Support for IBM PPE42 MMU Glenn Miles
2025-09-12 16:47 ` [PATCH v4 6/9] target/ppc: Add IBM PPE42 special instructions Glenn Miles
2025-09-16 9:12 ` Cédric Le Goater
2025-09-17 4:57 ` Harsh Prateek Bora
2025-09-17 6:20 ` Thomas Huth
2025-09-17 14:38 ` Miles Glenn
2025-09-17 16:07 ` BALATON Zoltan
2025-09-17 16:43 ` Thomas Huth
2025-09-17 16:52 ` Miles Glenn
2025-09-17 16:35 ` Cédric Le Goater
2025-09-12 16:47 ` Glenn Miles [this message]
2025-09-12 16:47 ` [PATCH v4 8/9] hw/ppc: Add a test machine for the IBM PPE42 CPU Glenn Miles
2025-09-12 16:47 ` [PATCH v4 9/9] tests/functional: Add test for IBM PPE42 instructions Glenn Miles
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