From: Max Chou <max.chou@sifive.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Weiwei Li <liwei1518@gmail.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
Max Chou <max.chou@sifive.com>
Subject: [RFC PATCH 1/8] target/riscv: Add cfg properities for Zvfbfa extensions
Date: Mon, 15 Sep 2025 16:40:29 +0800 [thread overview]
Message-ID: <20250915084037.1816893-2-max.chou@sifive.com> (raw)
In-Reply-To: <20250915084037.1816893-1-max.chou@sifive.com>
The Zvfbfa extension adds more complete BF16 vector compute support
and requires the Zve32f and Zfbfmin extensions.
Signed-off-by: Max Chou <max.chou@sifive.com>
---
target/riscv/cpu.c | 1 +
target/riscv/cpu_cfg_fields.h.inc | 1 +
target/riscv/tcg/tcg-cpu.c | 8 ++++++++
3 files changed, 10 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d055ddf4623..fc0614dadba 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -169,6 +169,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
ISA_EXT_DATA_ENTRY(zve64x, PRIV_VERSION_1_10_0, ext_zve64x),
+ ISA_EXT_DATA_ENTRY(zvfbfa, PRIV_VERSION_1_13_0, ext_zvfbfa),
ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),
ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc
index e2d116f0dfb..f69be188e4a 100644
--- a/target/riscv/cpu_cfg_fields.h.inc
+++ b/target/riscv/cpu_cfg_fields.h.inc
@@ -96,6 +96,7 @@ BOOL_FIELD(ext_zvks)
BOOL_FIELD(ext_zvksc)
BOOL_FIELD(ext_zvksg)
BOOL_FIELD(ext_zmmul)
+BOOL_FIELD(ext_zvfbfa)
BOOL_FIELD(ext_zvfbfmin)
BOOL_FIELD(ext_zvfbfwma)
BOOL_FIELD(ext_zvfh)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 78fb2791847..07b2b137934 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -704,6 +704,14 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
return;
}
+ if (cpu->cfg.ext_zvfbfa) {
+ if (!cpu->cfg.ext_zve32f || !cpu->cfg.ext_zfbfmin) {
+ error_setg(errp, "Zvfbfa extension requires Zve32f extension "
+ "and Zfbfmin extension");
+ return;
+ }
+ }
+
if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
return;
--
2.43.0
next prev parent reply other threads:[~2025-09-15 8:44 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-15 8:40 [RFC PATCH 0/8] Add Zvfbfa extension support Max Chou
2025-09-15 8:40 ` Max Chou [this message]
2025-09-17 13:47 ` [RFC PATCH 1/8] target/riscv: Add cfg properities for Zvfbfa extensions Daniel Henrique Barboza
2025-09-15 8:40 ` [RFC PATCH 2/8] target/riscv: Add the Zvfbfa extension implied rule Max Chou
2025-09-17 13:47 ` Daniel Henrique Barboza
2025-09-15 8:40 ` [RFC PATCH 3/8] target/riscv: rvv: Add new VTYPE CSR field - altfmt Max Chou
2025-09-17 13:57 ` Daniel Henrique Barboza
2025-09-22 8:03 ` Max Chou
2025-09-22 11:41 ` Daniel Henrique Barboza
2025-09-15 8:40 ` [RFC PATCH 4/8] target/riscv: Use the tb->cs_bqse as the extend tb flags Max Chou
2025-09-15 8:40 ` [RFC PATCH 5/8] target/riscv: Introduce altfmt into DisasContext Max Chou
2025-09-15 8:40 ` [RFC PATCH 6/8] target/riscv: Introduce BF16 canonical NaN for Zvfbfa extension Max Chou
2025-09-15 8:40 ` [RFC PATCH 7/8] target/riscv: rvv: Support Zvfbfa vector bf16 operations Max Chou
2025-09-15 8:40 ` [RFC PATCH 8/8] target/riscv: Expose Zvfbfa extension as an experimental cpu property Max Chou
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