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[114.35.142.126]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-26295996ff6sm55852045ad.64.2025.09.15.01.40.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Sep 2025 01:40:58 -0700 (PDT) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Max Chou Subject: [RFC PATCH 3/8] target/riscv: rvv: Add new VTYPE CSR field - altfmt Date: Mon, 15 Sep 2025 16:40:31 +0800 Message-ID: <20250915084037.1816893-4-max.chou@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250915084037.1816893-1-max.chou@sifive.com> References: <20250915084037.1816893-1-max.chou@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=max.chou@sifive.com; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org According to the Zvfbfa ISA spec v0.1, the vtype CSR adds a new field: altfmt for BF16 support. This update changes the layout of the vtype CSR fields. Signed-off-by: Max Chou --- target/riscv/cpu.h | 4 ++-- target/riscv/vector_helper.c | 29 ++++++++++++++++++++++++----- 2 files changed, 26 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 738e68fa6e2..532386000af 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -190,8 +190,8 @@ FIELD(VTYPE, VLMUL, 0, 3) FIELD(VTYPE, VSEW, 3, 3) FIELD(VTYPE, VTA, 6, 1) FIELD(VTYPE, VMA, 7, 1) -FIELD(VTYPE, VEDIV, 8, 2) -FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) +FIELD(VTYPE, ALTFMT, 8, 1) +FIELD(VTYPE, RESERVED, 9, sizeof(target_ulong) * 8 - 10) typedef struct PMUCTRState { /* Current value of a counter */ diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 7c67d67a13f..603d0731ae1 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -33,6 +33,22 @@ #include "vector_internals.h" #include +static target_ulong vtype_reserved(CPURISCVState *env, target_ulong vtype) +{ + int xlen = riscv_cpu_xlen(env); + target_ulong reserved = 0; + + if (riscv_cpu_cfg(env)->ext_zvfbfa) { + reserved = vtype & MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT, + xlen - 1 - R_VTYPE_RESERVED_SHIFT); + } else { + reserved = vtype & MAKE_64BIT_MASK(R_VTYPE_ALTFMT_SHIFT, + xlen - 1 - R_VTYPE_ALTFMT_SHIFT); + } + + return reserved; +} + target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, target_ulong s2, target_ulong x0) { @@ -41,12 +57,9 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, uint64_t vlmul = FIELD_EX64(s2, VTYPE, VLMUL); uint8_t vsew = FIELD_EX64(s2, VTYPE, VSEW); uint16_t sew = 8 << vsew; - uint8_t ediv = FIELD_EX64(s2, VTYPE, VEDIV); + uint8_t altfmt = FIELD_EX64(s2, VTYPE, ALTFMT); int xlen = riscv_cpu_xlen(env); bool vill = (s2 >> (xlen - 1)) & 0x1; - target_ulong reserved = s2 & - MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT, - xlen - 1 - R_VTYPE_RESERVED_SHIFT); uint16_t vlen = cpu->cfg.vlenb << 3; int8_t lmul; @@ -63,7 +76,13 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, } } - if ((sew > cpu->cfg.elen) || vill || (ediv != 0) || (reserved != 0)) { + if (cpu->cfg.ext_zvfbfa) { + if (altfmt == 1 && vsew >= MO_32) { + vill = true; + } + } + + if ((sew > cpu->cfg.elen) || vill || (vtype_reserved(env, s2) != 0)) { /* only set vill bit. */ env->vill = 1; env->vtype = 0; -- 2.43.0