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[114.35.142.126]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-26295996ff6sm55852045ad.64.2025.09.15.01.40.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Sep 2025 01:41:01 -0700 (PDT) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Max Chou Subject: [RFC PATCH 4/8] target/riscv: Use the tb->cs_bqse as the extend tb flags. Date: Mon, 15 Sep 2025 16:40:32 +0800 Message-ID: <20250915084037.1816893-5-max.chou@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250915084037.1816893-1-max.chou@sifive.com> References: <20250915084037.1816893-1-max.chou@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=max.chou@sifive.com; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org We have more than 32-bits worth of state per TB, so use the tb->cs_base, which is otherwise unused for RISC-V, as the extend flag. Signed-off-by: Max Chou --- include/exec/translation-block.h | 1 + target/riscv/cpu.h | 2 ++ target/riscv/tcg/tcg-cpu.c | 6 +++++- 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/include/exec/translation-block.h b/include/exec/translation-block.h index cdce399ebab..aa2dd4b12f8 100644 --- a/include/exec/translation-block.h +++ b/include/exec/translation-block.h @@ -63,6 +63,7 @@ struct TranslationBlock { * arm: an extension of tb->flags, * s390x: instruction data for EXECUTE, * sparc: the next pc of the instruction queue (for delay slots). + * riscv: an extension of tb->flags, */ uint64_t cs_base; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 532386000af..d10464eeeca 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -704,6 +704,8 @@ FIELD(TB_FLAGS, BCFI_ENABLED, 28, 1) FIELD(TB_FLAGS, PM_PMM, 29, 2) FIELD(TB_FLAGS, PM_SIGNEXTEND, 31, 1) +FIELD(EXT_TB_FLAGS, ALTFMT, 0, 1) + #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) #else diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 07b2b137934..6fe3ae9c085 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -104,6 +104,7 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *cs) RISCVCPU *cpu = env_archcpu(env); RISCVExtStatus fs, vs; uint32_t flags = 0; + uint64_t ext_flags = 0; bool pm_signext = riscv_cpu_virt_mem_enabled(env); if (cpu->cfg.ext_zve32x) { @@ -118,6 +119,7 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *cs) /* lmul encoded as in DisasContext::lmul */ int8_t lmul = sextract32(FIELD_EX64(env->vtype, VTYPE, VLMUL), 0, 3); + uint8_t altfmt = FIELD_EX64(env->vtype, VTYPE, ALTFMT); uint32_t vsew = FIELD_EX64(env->vtype, VTYPE, VSEW); uint32_t vlmax = vext_get_vlmax(cpu->cfg.vlenb, vsew, lmul); uint32_t maxsz = vlmax << vsew; @@ -133,6 +135,7 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *cs) flags = FIELD_DP32(flags, TB_FLAGS, VMA, FIELD_EX64(env->vtype, VTYPE, VMA)); flags = FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart == 0); + ext_flags = FIELD_DP64(ext_flags, EXT_TB_FLAGS, ALTFMT, altfmt); } else { flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); } @@ -191,7 +194,8 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *cs) return (TCGTBCPUState){ .pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc, - .flags = flags + .flags = flags, + .cs_base = ext_flags, }; } -- 2.43.0