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From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com,
	alistair.francis@wdc.com, dbarboza@ventanamicro.com,
	liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com,
	Huang Tao <eric.huang@linux.alibaba.com>,
	TANG Tiancheng <lyndra@linux.alibaba.com>
Subject: [PATCH v2 6/6] target/riscv: Enable SMMPT extension
Date: Thu, 18 Sep 2025 14:19:11 +0800	[thread overview]
Message-ID: <20250918061911.904-7-zhiwei_liu@linux.alibaba.com> (raw)
In-Reply-To: <20250918061911.904-1-zhiwei_liu@linux.alibaba.com>

Co-authored-by: Huang Tao <eric.huang@linux.alibaba.com>
Co-authored-by: TANG Tiancheng <lyndra@linux.alibaba.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
 target/riscv/cpu.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ad5597c9ac..959024a0c5 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -204,8 +204,10 @@ const RISCVIsaExtData isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(smdbltrp, PRIV_VERSION_1_13_0, ext_smdbltrp),
     ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp),
     ISA_EXT_DATA_ENTRY(smmpm, PRIV_VERSION_1_13_0, ext_smmpm),
+    ISA_EXT_DATA_ENTRY(smmpt, PRIV_VERSION_1_13_0, ext_smmpt),
     ISA_EXT_DATA_ENTRY(smnpm, PRIV_VERSION_1_13_0, ext_smnpm),
     ISA_EXT_DATA_ENTRY(smrnmi, PRIV_VERSION_1_12_0, ext_smrnmi),
+    ISA_EXT_DATA_ENTRY(smsdid, PRIV_VERSION_1_13_0, ext_smsdid),
     ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen),
     ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia),
     ISA_EXT_DATA_ENTRY(ssccfg, PRIV_VERSION_1_13_0, ext_ssccfg),
@@ -1371,6 +1373,8 @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
 
 /* These are experimental so mark with 'x-' */
 const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
+    MULTI_EXT_CFG_BOOL("x-smmpt", ext_smmpt, false),
+    MULTI_EXT_CFG_BOOL("x-smsdid", ext_smsdid, false),
     MULTI_EXT_CFG_BOOL("x-svukte", ext_svukte, false),
 
     { },
-- 
2.25.1



  parent reply	other threads:[~2025-09-18  6:23 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-18  6:19 [PATCH v2 0/6] target/riscv: Implement Smsdid and Smmpt extension LIU Zhiwei
2025-09-18  6:19 ` [PATCH v2 1/6] target/riscv: Add basic definitions and CSRs for SMMPT LIU Zhiwei
2025-10-12 17:32   ` Daniel Henrique Barboza
2025-09-18  6:19 ` [PATCH v2 2/6] target/riscv: Implement core SMMPT lookup logic LIU Zhiwei
2025-10-12 17:32   ` Daniel Henrique Barboza
2025-09-18  6:19 ` [PATCH v2 3/6] target/riscv: Integrate SMMPT checks into MMU and TLB fill LIU Zhiwei
2025-09-18  6:19 ` [PATCH v2 4/6] target/riscv: Implement SMMPT fence instructions LIU Zhiwei
2025-09-18  6:19 ` [PATCH v2 5/6] target/riscv: Fix smrnmi isa alphabetical order LIU Zhiwei
2025-10-12 17:33   ` Daniel Henrique Barboza
2025-09-18  6:19 ` LIU Zhiwei [this message]
2025-10-12 17:33   ` [PATCH v2 6/6] target/riscv: Enable SMMPT extension Daniel Henrique Barboza

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