From: Jamin Lin via <qemu-devel@nongnu.org>
To: "Paolo Bonzini" <pbonzini@redhat.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Cédric Le Goater" <clg@kaod.org>,
"Steven Lee" <steven_lee@aspeedtech.com>,
"Troy Lee" <leetroy@gmail.com>,
"Andrew Jeffery" <andrew@codeconstruct.com.au>,
"Joel Stanley" <joel@jms.id.au>,
"Michael S. Tsirkin" <mst@redhat.com>,
"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
"open list:ARM TCG CPUs" <qemu-arm@nongnu.org>,
"open list:All patches CC here" <qemu-devel@nongnu.org>
Cc: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>,
<nabihestefan@google.com>, <wuhaotsh@google.com>,
<titusr@google.com>
Subject: [PATCH v4 11/14] hw/pci-host/aspeed: Disable Root Device and place Root Port at 00:00.0 to AST2700
Date: Fri, 19 Sep 2025 11:24:24 +0800 [thread overview]
Message-ID: <20250919032431.3316764-12-jamin_lin@aspeedtech.com> (raw)
In-Reply-To: <20250919032431.3316764-1-jamin_lin@aspeedtech.com>
AST2700 does not implement a PCIe Root Device; each RC exposes a single
PCIe Root Port at devfn 0:0.0.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/pci-host/aspeed_pcie.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/pci-host/aspeed_pcie.c b/hw/pci-host/aspeed_pcie.c
index a757fd7ec8..f7593444fc 100644
--- a/hw/pci-host/aspeed_pcie.c
+++ b/hw/pci-host/aspeed_pcie.c
@@ -829,6 +829,8 @@ static void aspeed_2700_pcie_cfg_class_init(ObjectClass *klass,
apc->nr_regs = 0x100 >> 2;
apc->rc_msi_addr = 0x000000F0;
apc->rc_bus_nr = 0;
+ apc->rc_has_rd = false;
+ apc->rc_rp_addr = PCI_DEVFN(0, 0);
}
static const TypeInfo aspeed_2700_pcie_cfg_info = {
--
2.43.0
next prev parent reply other threads:[~2025-09-19 3:28 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-19 3:24 [PATCH v4 00/14] Support PCIe RC to AST2600 and AST2700 Jamin Lin via
2025-09-19 3:24 ` [PATCH v4 01/14] hw/pci/pci_ids: Add PCI vendor ID for ASPEED Jamin Lin via
2025-09-19 3:24 ` [PATCH v4 02/14] hw/pci-host/aspeed: Add AST2600 PCIe PHY model Jamin Lin via
2025-09-19 7:13 ` [SPAM] " Cédric Le Goater
2025-09-19 3:24 ` [PATCH v4 03/14] hw/pci-host/aspeed: Add AST2600 PCIe config space and host bridge Jamin Lin via
2025-09-19 7:13 ` [SPAM] " Cédric Le Goater
2025-09-19 3:24 ` [PATCH v4 04/14] hw/pci-host/aspeed: Add AST2600 PCIe Root Device support Jamin Lin via
2025-09-19 8:05 ` [SPAM] " Cédric Le Goater
2025-09-19 3:24 ` [PATCH v4 05/14] hw/pci-host/aspeed: Add AST2600 PCIe Root Port and make address configurable Jamin Lin via
2025-09-19 8:05 ` [SPAM] " Cédric Le Goater
2025-09-19 3:24 ` [PATCH v4 06/14] hw/pci-host/aspeed: Add MSI support and per-RC IOMMU address space Jamin Lin via
2025-09-19 8:06 ` [SPAM] " Cédric Le Goater
2025-09-19 3:24 ` [PATCH v4 07/14] hw/arm/aspeed: Wire up PCIe devices in SoC model Jamin Lin via
2025-09-19 3:24 ` [PATCH v4 08/14] hw/arm/aspeed_ast2600: Add PCIe RC support (RC_H only) Jamin Lin via
2025-09-19 8:05 ` [SPAM] " Cédric Le Goater
2025-09-19 3:24 ` [PATCH v4 09/14] hw/pci-host/aspeed: Add AST2700 PCIe PHY Jamin Lin via
2025-09-19 8:06 ` [SPAM] " Cédric Le Goater
2025-09-19 3:24 ` [PATCH v4 10/14] hw/pci-host/aspeed: Add AST2700 PCIe config with dedicated H2X blocks Jamin Lin via
2025-09-19 8:57 ` [SPAM] " Cédric Le Goater
2025-09-19 3:24 ` Jamin Lin via [this message]
2025-09-19 8:55 ` [SPAM] [PATCH v4 11/14] hw/pci-host/aspeed: Disable Root Device and place Root Port at 00:00.0 to AST2700 Cédric Le Goater
2025-09-19 3:24 ` [PATCH v4 12/14] hw/arm/aspeed_ast27x0: Introduce 3 PCIe RCs for AST2700 Jamin Lin via
2025-09-19 8:53 ` [SPAM] " Cédric Le Goater
2025-09-19 8:58 ` Jamin Lin
2025-09-19 3:24 ` [PATCH v4 13/14] tests/functional/arm/test_aspeed_ast2600: Add PCIe and network test Jamin Lin via
2025-09-19 8:05 ` [SPAM] " Cédric Le Goater
2025-09-19 3:24 ` [PATCH v4 14/14] tests/functional/aarch64/aspeed_ast2700: Add PCIe and network tests Jamin Lin via
2025-09-19 8:56 ` [SPAM] " Cédric Le Goater
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