From: Ben Dooks <ben.dooks@codethink.co.uk>
To: qemu-riscv@nongnu.org
Cc: qemu-devel@nongnu.org, alistair.francis@wdc.com,
liwei1518@gmail.com, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com, lawrence.hunter@codethink.co.uk,
javier.jardon@codethink.co.uk, roan.richmond@codethink.co.uk
Subject: RISC-V: Add CVA6 machine
Date: Fri, 19 Sep 2025 18:12:33 +0100 [thread overview]
Message-ID: <20250919171235.152476-1-ben.dooks@codethink.co.uk> (raw)
Add CVA6 (the corev_apu from the fpga) model from
https://github.com/openhwgroup/cva6
Previous submission:
https://lists.gnu.org/archive/html/qemu-devel/2025-06/msg01411.html
v4:
- comment fixes
- make the core-type first and then add machine
v3:
- fix missing file source
- set 64bit only for now
v2:
- rebased and fixed whitespace issues
next reply other threads:[~2025-09-19 17:14 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-19 17:12 Ben Dooks [this message]
2025-09-19 17:12 ` [PATCH v4 1/2] target/riscv: add cva6 core type Ben Dooks
2025-09-19 17:12 ` [PATCH v4 2/2] hw/riscv: add CVA6 machine Ben Dooks
2025-10-31 3:27 ` Alistair Francis
-- strict thread matches above, loose matches on Subject: below --
2025-06-09 13:17 RISC-V: Add " Ben Dooks
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