From: Luc Michel <luc.michel@amd.com>
To: <qemu-devel@nongnu.org>, <qemu-arm@nongnu.org>
Cc: "Luc Michel" <luc.michel@amd.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Francisco Iglesias" <francisco.iglesias@amd.com>,
"Edgar E . Iglesias" <edgar.iglesias@amd.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Alistair Francis" <alistair@alistair23.me>,
"Frederic Konrad" <frederic.konrad@amd.com>,
"Sai Pavan Boddu" <sai.pavan.boddu@amd.com>
Subject: [PATCH v6 12/47] hw/arm/xlnx-versal: VersalMap: add support for OR'ed IRQs
Date: Fri, 26 Sep 2025 09:07:30 +0200 [thread overview]
Message-ID: <20250926070806.292065-13-luc.michel@amd.com> (raw)
In-Reply-To: <20250926070806.292065-1-luc.michel@amd.com>
Improve the IRQ index in the VersalMap structure to turn it into a
descriptor:
- the lower 16 bits still represent the IRQ index
- bit 18 is used to indicate a shared IRQ connected to a OR gate
- bits 19 to 22 indicate the index on the OR gate.
This allows to share an IRQ among multiple devices. An OR gate is
created to connect the devices to the actual IRQ pin.
Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
---
hw/arm/xlnx-versal.c | 63 +++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 62 insertions(+), 1 deletion(-)
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index 964250bf151..d3a084a0639 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -41,10 +41,21 @@
#define GEM_REVISION 0x40070106
#define VERSAL_NUM_PMC_APB_IRQS 18
#define NUM_OSPI_IRQ_LINES 3
+/*
+ * IRQ descriptor to catch the following cases:
+ * - Multiple devices can connect to the same IRQ. They are OR'ed together.
+ */
+FIELD(VERSAL_IRQ, IRQ, 0, 16)
+FIELD(VERSAL_IRQ, ORED, 18, 1)
+FIELD(VERSAL_IRQ, OR_IDX, 19, 4) /* input index on the IRQ OR gate */
+
+#define OR_IRQ(irq, or_idx) \
+ (R_VERSAL_IRQ_ORED_MASK | ((or_idx) << R_VERSAL_IRQ_OR_IDX_SHIFT) | (irq))
+
typedef struct VersalSimplePeriphMap {
uint64_t addr;
int irq;
} VersalSimplePeriphMap;
@@ -172,13 +183,57 @@ static inline Object *versal_get_child_idx(Versal *s, const char *child,
g_autofree char *n = g_strdup_printf("%s[%zu]", child, idx);
return versal_get_child(s, n);
}
+/*
+ * When the R_VERSAL_IRQ_ORED flag is set on an IRQ descriptor, this function is
+ * used to return the corresponding or gate input IRQ. The or gate is created if
+ * not already existant.
+ *
+ * Or gates are placed under the /soc/irq-or-gates QOM container.
+ */
+static qemu_irq versal_get_irq_or_gate_in(Versal *s, int irq_idx,
+ qemu_irq target_irq)
+{
+ Object *container = versal_get_child(s, "irq-or-gates");
+ DeviceState *dev;
+ g_autofree char *name;
+ int idx, or_idx;
+
+ idx = FIELD_EX32(irq_idx, VERSAL_IRQ, IRQ);
+ or_idx = FIELD_EX32(irq_idx, VERSAL_IRQ, OR_IDX);
+
+ name = g_strdup_printf("irq[%d]", idx);
+ dev = DEVICE(object_resolve_path_at(container, name));
+
+ if (dev == NULL) {
+ dev = qdev_new(TYPE_OR_IRQ);
+ object_property_add_child(container, name, OBJECT(dev));
+ qdev_prop_set_uint16(dev, "num-lines", 1 << R_VERSAL_IRQ_OR_IDX_LENGTH);
+ qdev_realize_and_unref(dev, NULL, &error_abort);
+ qdev_connect_gpio_out(dev, 0, target_irq);
+ }
+
+ return qdev_get_gpio_in(dev, or_idx);
+}
+
static qemu_irq versal_get_irq(Versal *s, int irq_idx)
{
- return qdev_get_gpio_in(DEVICE(&s->fpd.apu.gic), irq_idx);
+ qemu_irq irq;
+ bool ored;
+
+ ored = FIELD_EX32(irq_idx, VERSAL_IRQ, ORED);
+
+ irq = qdev_get_gpio_in(DEVICE(&s->fpd.apu.gic),
+ FIELD_EX32(irq_idx, VERSAL_IRQ, IRQ));
+
+ if (ored) {
+ irq = versal_get_irq_or_gate_in(s, irq_idx, irq);
+ }
+
+ return irq;
}
static void versal_sysbus_connect_irq(Versal *s, SysBusDevice *sbd,
int sbd_idx, int irq_idx)
{
@@ -1215,20 +1270,26 @@ static uint32_t fdt_add_clk_node(Versal *s, const char *name,
static void versal_realize(DeviceState *dev, Error **errp)
{
Versal *s = XLNX_VERSAL_BASE(dev);
qemu_irq pic[XLNX_VERSAL_NR_IRQS];
+ Object *container;
const VersalMap *map = versal_get_map(s);
size_t i;
g_assert(s->cfg.fdt != NULL);
s->phandle.clk_25mhz = fdt_add_clk_node(s, "/clk25", 25 * 1000 * 1000);
s->phandle.clk_125mhz = fdt_add_clk_node(s, "/clk125", 125 * 1000 * 1000);
versal_create_apu_cpus(s);
versal_create_apu_gic(s, pic);
+
+ container = object_new(TYPE_CONTAINER);
+ object_property_add_child(OBJECT(s), "irq-or-gates", container);
+ object_unref(container);
+
versal_create_rpu_cpus(s);
for (i = 0; i < map->num_uart; i++) {
versal_create_uart(s, &map->uart[i], i);
}
--
2.51.0
next prev parent reply other threads:[~2025-09-26 7:19 UTC|newest]
Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-26 7:07 [PATCH v6 00/47] AMD Versal Gen 2 support Luc Michel
2025-09-26 7:07 ` [PATCH v6 01/47] hw/arm/xlnx-versal: split the xlnx-versal type Luc Michel
2025-09-26 7:07 ` [PATCH v6 02/47] hw/arm/xlnx-versal: prepare for FDT creation Luc Michel
2025-09-26 7:07 ` [PATCH v6 03/47] hw/arm/xlnx-versal: uart: refactor creation Luc Michel
2025-09-26 7:07 ` [PATCH v6 04/47] hw/arm/xlnx-versal: canfd: " Luc Michel
2025-09-26 7:07 ` [PATCH v6 05/47] hw/arm/xlnx-versal: sdhci: " Luc Michel
2025-09-26 7:07 ` [PATCH v6 06/47] hw/arm/xlnx-versal: gem: " Luc Michel
2025-09-26 7:07 ` [PATCH v6 07/47] hw/arm/xlnx-versal: adma: " Luc Michel
2025-09-26 7:07 ` [PATCH v6 08/47] hw/arm/xlnx-versal: xram: " Luc Michel
2025-09-26 7:07 ` [PATCH v6 09/47] hw/arm/xlnx-versal: usb: " Luc Michel
2025-09-26 7:07 ` [PATCH v6 10/47] hw/arm/xlnx-versal: efuse: " Luc Michel
2025-09-26 7:07 ` [PATCH v6 11/47] hw/arm/xlnx-versal: ospi: " Luc Michel
2025-09-26 7:07 ` Luc Michel [this message]
2025-09-26 7:07 ` [PATCH v6 13/47] hw/arm/xlnx-versal: PMC IOU SCLR: " Luc Michel
2025-09-26 7:07 ` [PATCH v6 14/47] hw/arm/xlnx-versal: bbram: " Luc Michel
2025-09-26 7:07 ` [PATCH v6 15/47] hw/arm/xlnx-versal: trng: " Luc Michel
2025-09-26 7:07 ` [PATCH v6 16/47] hw/arm/xlnx-versal: rtc: " Luc Michel
2025-09-26 7:07 ` [PATCH v6 17/47] hw/arm/xlnx-versal: cfu: " Luc Michel
2025-09-26 7:07 ` [PATCH v6 18/47] hw/arm/xlnx-versal: crl: " Luc Michel
2025-09-26 7:07 ` [PATCH v6 19/47] hw/arm/xlnx-versal-virt: virtio: " Luc Michel
2025-09-26 7:07 ` [PATCH v6 20/47] hw/arm/xlnx-versal: refactor CPU cluster creation Luc Michel
2025-09-26 7:07 ` [PATCH v6 21/47] hw/arm/xlnx-versal: add the mp_affinity property to the CPU mapping Luc Michel
2025-09-26 7:07 ` [PATCH v6 22/47] hw/arm/xlnx-versal: instantiate the GIC ITS in the APU Luc Michel
2025-09-26 7:07 ` [PATCH v6 23/47] hw/intc/arm_gicv3: Introduce a 'first-cpu-index' property Luc Michel
2025-09-29 10:29 ` Philippe Mathieu-Daudé
2025-09-26 7:07 ` [PATCH v6 24/47] hw/arm/xlnx-versal: add support for multiple GICs Luc Michel
2025-09-26 7:07 ` [PATCH v6 25/47] hw/arm/xlnx-versal: add support for GICv2 Luc Michel
2025-09-26 7:07 ` [PATCH v6 26/47] hw/arm/xlnx-versal: rpu: refactor creation Luc Michel
2025-09-26 7:07 ` [PATCH v6 27/47] hw/arm/xlnx-versal: ocm: " Luc Michel
2025-09-26 7:07 ` [PATCH v6 28/47] hw/arm/xlnx-versal: ddr: " Luc Michel
2025-09-26 7:07 ` [PATCH v6 29/47] hw/arm/xlnx-versal: add the versal_get_num_cpu accessor Luc Michel
2025-09-26 7:07 ` [PATCH v6 30/47] hw/misc/xlnx-versal-crl: remove unnecessary include directives Luc Michel
2025-09-26 7:07 ` [PATCH v6 31/47] hw/misc/xlnx-versal-crl: split into base/concrete classes Luc Michel
2025-09-26 7:07 ` [PATCH v6 32/47] hw/misc/xlnx-versal-crl: refactor device reset logic Luc Michel
2025-09-26 7:07 ` [PATCH v6 33/47] hw/arm/xlnx-versal: reconnect the CRL to the other devices Luc Michel
2025-09-26 7:07 ` [PATCH v6 34/47] hw/arm/xlnx-versal: use hw/arm/bsa.h for timer IRQ indices Luc Michel
2025-09-26 7:07 ` [PATCH v6 35/47] hw/arm/xlnx-versal: tidy up Luc Michel
2025-09-26 7:07 ` [PATCH v6 36/47] hw/misc/xlnx-versal-crl: add the versal2 version Luc Michel
2025-09-26 7:07 ` [PATCH v6 37/47] hw/arm/xlnx-versal: add a per_cluster_gic switch to VersalCpuClusterMap Luc Michel
2025-09-26 7:07 ` [PATCH v6 38/47] hw/arm/xlnx-versal: add the target field in IRQ descriptor Luc Michel
2025-09-29 10:34 ` Philippe Mathieu-Daudé
2025-09-30 6:37 ` Luc Michel
2025-09-30 7:30 ` Philippe Mathieu-Daudé
2025-09-26 7:07 ` [PATCH v6 39/47] target/arm/tcg/cpu64: add the cortex-a78ae CPU Luc Michel
2025-09-26 7:07 ` [PATCH v6 40/47] hw/arm/xlnx-versal: add versal2 SoC Luc Michel
2025-09-29 10:37 ` Philippe Mathieu-Daudé
2025-09-26 7:07 ` [PATCH v6 41/47] hw/arm/xlnx-versal-virt: rename the machine to amd-versal-virt Luc Michel
2025-09-26 7:08 ` [PATCH v6 42/47] hw/arm/xlnx-versal-virt: split into base/concrete classes Luc Michel
2025-09-29 10:37 ` Philippe Mathieu-Daudé
2025-09-26 7:08 ` [PATCH v6 43/47] hw/arm/xlnx-versal-virt: tidy up Luc Michel
2025-09-26 7:08 ` [PATCH v6 44/47] docs/system/arm/xlnx-versal-virt: update supported devices Luc Michel
2025-09-26 7:08 ` [PATCH v6 45/47] docs/system/arm/xlnx-versal-virt: add a note about dumpdtb Luc Michel
2025-09-26 7:08 ` [PATCH v6 46/47] hw/arm/xlnx-versal-virt: add the xlnx-versal2-virt machine Luc Michel
2025-09-29 10:38 ` Philippe Mathieu-Daudé
2025-09-26 7:08 ` [PATCH v6 47/47] tests/functional/test_aarch64_xlnx_versal: test the versal2 machine Luc Michel
2025-09-29 10:39 ` Philippe Mathieu-Daudé
2025-09-29 10:26 ` [PATCH v6 00/47] AMD Versal Gen 2 support Philippe Mathieu-Daudé
2025-10-07 9:48 ` Peter Maydell
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