From: Harsh Prateek Bora <harshpb@linux.ibm.com>
To: qemu-devel@nongnu.org
Cc: Glenn Miles <milesg@linux.ibm.com>, Chinmay Rath <rathc@linux.ibm.com>
Subject: [PULL 09/27] target/ppc: IBM PPE42 general regs and flags
Date: Mon, 29 Sep 2025 00:56:11 +0530 [thread overview]
Message-ID: <20250928192629.139822-10-harshpb@linux.ibm.com> (raw)
In-Reply-To: <20250928192629.139822-1-harshpb@linux.ibm.com>
From: Glenn Miles <milesg@linux.ibm.com>
Introduces general IBM PPE42 processor register definitions
and flags.
Signed-off-by: Glenn Miles <milesg@linux.ibm.com>
Reviewed-by: Chinmay Rath <rathc@linux.ibm.com>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Link: https://lore.kernel.org/r/20250925201758.652077-2-milesg@linux.ibm.com
Message-ID: <20250925201758.652077-2-milesg@linux.ibm.com>
---
target/ppc/cpu-models.h | 4 ++++
target/ppc/cpu.h | 49 ++++++++++++++++++++++++++++++++++++++++-
2 files changed, 52 insertions(+), 1 deletion(-)
diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h
index 72ad31ba50..c6cd27f390 100644
--- a/target/ppc/cpu-models.h
+++ b/target/ppc/cpu-models.h
@@ -69,6 +69,10 @@ enum {
/* Xilinx cores */
CPU_POWERPC_X2VP4 = 0x20010820,
CPU_POWERPC_X2VP20 = 0x20010860,
+ /* IBM PPE42 Family */
+ CPU_POWERPC_PPE42 = 0x42000000,
+ CPU_POWERPC_PPE42X = 0x42100000,
+ CPU_POWERPC_PPE42XM = 0x42200000,
/* PowerPC 440 family */
/* Generic PowerPC 440 */
#define CPU_POWERPC_440 CPU_POWERPC_440GXf
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 0e26e4343d..8e13ce41a9 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -282,6 +282,8 @@ typedef enum powerpc_input_t {
PPC_FLAGS_INPUT_POWER9,
/* Freescale RCPU bus */
PPC_FLAGS_INPUT_RCPU,
+ /* PPE42 bus */
+ PPC_FLAGS_INPUT_PPE42,
} powerpc_input_t;
#define PPC_INPUT(env) ((env)->bus_model)
@@ -433,39 +435,64 @@ typedef enum {
#define MSR_TM PPC_BIT_NR(31) /* Transactional Memory Available (Book3s) */
#define MSR_CM PPC_BIT_NR(32) /* Computation mode for BookE hflags */
#define MSR_ICM PPC_BIT_NR(33) /* Interrupt computation mode for BookE */
+#define MSR_SEM0 PPC_BIT_NR(33) /* SIB Error Mask Bit 0 (PPE42) */
+#define MSR_SEM1 PPC_BIT_NR(34) /* SIB Error Mask Bit 1 (PPE42) */
+#define MSR_SEM2 PPC_BIT_NR(35) /* SIB Error Mask Bit 2 (PPE42) */
#define MSR_GS PPC_BIT_NR(35) /* guest state for BookE */
+#define MSR_SEM3 PPC_BIT_NR(36) /* SIB Error Mask Bit 3 (PPE42) */
+#define MSR_SEM4 PPC_BIT_NR(37) /* SIB Error Mask Bit 4 (PPE42) */
#define MSR_UCLE PPC_BIT_NR(37) /* User-mode cache lock enable for BookE */
#define MSR_VR PPC_BIT_NR(38) /* altivec available x hflags */
#define MSR_SPE PPC_BIT_NR(38) /* SPE enable for BookE x hflags */
+#define MSR_SEM5 PPC_BIT_NR(38) /* SIB Error Mask Bit 5 (PPE42) */
+#define MSR_SEM6 PPC_BIT_NR(39) /* SIB Error Mask Bit 6 (PPE42) */
#define MSR_VSX PPC_BIT_NR(40) /* Vector Scalar Extension (>= 2.06)x hflags */
+#define MSR_IS0 PPC_BIT_NR(40) /* Instance Specific Bit 0 (PPE42) */
#define MSR_S PPC_BIT_NR(41) /* Secure state */
+#define MSR_SIBRC0 PPC_BIT_NR(41) /* Last SIB return code Bit 0 (PPE42) */
+#define MSR_SIBRC1 PPC_BIT_NR(42) /* Last SIB return code Bit 1 (PPE42) */
+#define MSR_SIBRC2 PPC_BIT_NR(43) /* Last SIB return code Bit 2 (PPE42) */
+#define MSR_LP PPC_BIT_NR(44) /* Low Priority (PPE42) */
#define MSR_KEY PPC_BIT_NR(44) /* key bit on 603e */
#define MSR_POW PPC_BIT_NR(45) /* Power management */
#define MSR_WE PPC_BIT_NR(45) /* Wait State Enable on 405 */
+#define MSR_IS1 PPC_BIT_NR(46) /* Instance Specific Bit 1 (PPE42) */
#define MSR_TGPR PPC_BIT_NR(46) /* TGPR usage on 602/603 x */
#define MSR_CE PPC_BIT_NR(46) /* Critical int. enable on embedded PPC x */
#define MSR_ILE PPC_BIT_NR(47) /* Interrupt little-endian mode */
+#define MSR_UIE PPC_BIT_NR(47) /* Unmaskable Interrupt Enable (PPE42) */
#define MSR_EE PPC_BIT_NR(48) /* External interrupt enable */
#define MSR_PR PPC_BIT_NR(49) /* Problem state hflags */
#define MSR_FP PPC_BIT_NR(50) /* Floating point available hflags */
#define MSR_ME PPC_BIT_NR(51) /* Machine check interrupt enable */
#define MSR_FE0 PPC_BIT_NR(52) /* Floating point exception mode 0 */
+#define MSR_IS2 PPC_BIT_NR(52) /* Instance Specific Bit 2 (PPE42) */
+#define MSR_IS3 PPC_BIT_NR(53) /* Instance Specific Bit 3 (PPE42) */
#define MSR_SE PPC_BIT_NR(53) /* Single-step trace enable x hflags */
#define MSR_DWE PPC_BIT_NR(53) /* Debug wait enable on 405 x */
#define MSR_UBLE PPC_BIT_NR(53) /* User BTB lock enable on e500 x */
#define MSR_BE PPC_BIT_NR(54) /* Branch trace enable x hflags */
#define MSR_DE PPC_BIT_NR(54) /* Debug int. enable on embedded PPC x */
#define MSR_FE1 PPC_BIT_NR(55) /* Floating point exception mode 1 */
+#define MSR_IPE PPC_BIT_NR(55) /* Imprecise Mode Enable (PPE42) */
#define MSR_AL PPC_BIT_NR(56) /* AL bit on POWER */
+#define MSR_SIBRCA0 PPC_BIT_NR(56) /* SIB Return Code Accumulator 0 (PPE42) */
+#define MSR_SIBRCA1 PPC_BIT_NR(57) /* SIB Return Code Accumulator 1 (PPE42) */
#define MSR_EP PPC_BIT_NR(57) /* Exception prefix on 601 */
#define MSR_IR PPC_BIT_NR(58) /* Instruction relocate */
#define MSR_IS PPC_BIT_NR(58) /* Instruction address space (BookE) */
+#define MSR_SIBRCA2 PPC_BIT_NR(58) /* SIB Return Code Accumulator 2 (PPE42) */
+#define MSR_SIBRCA3 PPC_BIT_NR(59) /* SIB Return Code Accumulator 3 (PPE42) */
#define MSR_DR PPC_BIT_NR(59) /* Data relocate */
#define MSR_DS PPC_BIT_NR(59) /* Data address space (BookE) */
#define MSR_PE PPC_BIT_NR(60) /* Protection enable on 403 */
+#define MSR_SIBRCA4 PPC_BIT_NR(60) /* SIB Return Code Accumulator 4 (PPE42) */
+#define MSR_SIBRCA5 PPC_BIT_NR(61) /* SIB Return Code Accumulator 5 (PPE42) */
#define MSR_PX PPC_BIT_NR(61) /* Protection exclusive on 403 x */
#define MSR_PMM PPC_BIT_NR(61) /* Performance monitor mark on POWER x */
#define MSR_RI PPC_BIT_NR(62) /* Recoverable interrupt 1 */
+#define MSR_SIBRCA6 PPC_BIT_NR(62) /* SIB Return Code Accumulator 6 (PPE42) */
+#define MSR_SIBRCA7 PPC_BIT_NR(63) /* SIB Return Code Accumulator 7 (PPE42) */
#define MSR_LE PPC_BIT_NR(63) /* Little-endian mode 1 hflags */
FIELD(MSR, SF, MSR_SF, 1)
@@ -517,6 +544,9 @@ FIELD(MSR, PX, MSR_PX, 1)
FIELD(MSR, PMM, MSR_PMM, 1)
FIELD(MSR, RI, MSR_RI, 1)
FIELD(MSR, LE, MSR_LE, 1)
+FIELD(MSR, SEM, MSR_SEM6, 7)
+FIELD(MSR, SIBRC, MSR_SIBRC2, 3)
+FIELD(MSR, SIBRCA, MSR_SIBRCA7, 8)
/*
* FE0 and FE1 bits are not side-by-side
@@ -785,6 +815,8 @@ enum {
POWERPC_FLAG_SMT_1LPAR = 0x00800000,
/* Has BHRB */
POWERPC_FLAG_BHRB = 0x01000000,
+ /* Use PPE42-specific behavior */
+ POWERPC_FLAG_PPE42 = 0x02000000,
};
/*
@@ -1754,9 +1786,12 @@ void ppc_compat_add_property(Object *obj, const char *name,
#define SPR_BOOKE_CSRR0 (0x03A)
#define SPR_BOOKE_CSRR1 (0x03B)
#define SPR_BOOKE_DEAR (0x03D)
+#define SPR_PPE42_EDR (0x03D)
#define SPR_IAMR (0x03D)
#define SPR_BOOKE_ESR (0x03E)
+#define SPR_PPE42_ISR (0x03E)
#define SPR_BOOKE_IVPR (0x03F)
+#define SPR_PPE42_IVPR (0x03F)
#define SPR_MPC_EIE (0x050)
#define SPR_MPC_EID (0x051)
#define SPR_MPC_NRI (0x052)
@@ -1822,6 +1857,7 @@ void ppc_compat_add_property(Object *obj, const char *name,
#define SPR_TBU40 (0x11E)
#define SPR_SVR (0x11E)
#define SPR_BOOKE_PIR (0x11E)
+#define SPR_PPE42_PIR (0x11E)
#define SPR_PVR (0x11F)
#define SPR_HSPRG0 (0x130)
#define SPR_BOOKE_DBSR (0x130)
@@ -1831,6 +1867,7 @@ void ppc_compat_add_property(Object *obj, const char *name,
#define SPR_BOOKE_EPCR (0x133)
#define SPR_SPURR (0x134)
#define SPR_BOOKE_DBCR0 (0x134)
+#define SPR_PPE42_DBCR (0x134)
#define SPR_IBCR (0x135)
#define SPR_PURR (0x135)
#define SPR_BOOKE_DBCR1 (0x135)
@@ -1848,6 +1885,7 @@ void ppc_compat_add_property(Object *obj, const char *name,
#define SPR_HSRR1 (0x13B)
#define SPR_BOOKE_IAC4 (0x13B)
#define SPR_BOOKE_DAC1 (0x13C)
+#define SPR_PPE42_DACR (0x13C)
#define SPR_MMCRH (0x13C)
#define SPR_DABR2 (0x13D)
#define SPR_BOOKE_DAC2 (0x13D)
@@ -1857,12 +1895,14 @@ void ppc_compat_add_property(Object *obj, const char *name,
#define SPR_BOOKE_DVC2 (0x13F)
#define SPR_LPIDR (0x13F)
#define SPR_BOOKE_TSR (0x150)
+#define SPR_PPE42_TSR (0x150)
#define SPR_HMER (0x150)
#define SPR_HMEER (0x151)
#define SPR_PCR (0x152)
#define SPR_HEIR (0x153)
#define SPR_BOOKE_LPIDR (0x152)
#define SPR_BOOKE_TCR (0x154)
+#define SPR_PPE42_TCR (0x154)
#define SPR_BOOKE_TLB0PS (0x158)
#define SPR_BOOKE_TLB1PS (0x159)
#define SPR_BOOKE_TLB2PS (0x15A)
@@ -2532,6 +2572,12 @@ enum {
PPC2_MEM_LWSYNC = 0x0000000000200000ULL,
/* ISA 2.06 BCD assist instructions */
PPC2_BCDA_ISA206 = 0x0000000000400000ULL,
+ /* PPE42 instructions */
+ PPC2_PPE42 = 0x0000000000800000ULL,
+ /* PPE42X instructions */
+ PPC2_PPE42X = 0x0000000001000000ULL,
+ /* PPE42XM instructions */
+ PPC2_PPE42XM = 0x0000000002000000ULL,
#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
@@ -2541,7 +2587,8 @@ enum {
PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
PPC2_ISA300 | PPC2_ISA310 | PPC2_MEM_LWSYNC | \
- PPC2_BCDA_ISA206)
+ PPC2_BCDA_ISA206 | PPC2_PPE42 | PPC2_PPE42X | \
+ PPC2_PPE42XM)
};
/*****************************************************************************/
--
2.43.5
next prev parent reply other threads:[~2025-09-28 19:28 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-28 19:26 [PULL 00/27] ppc-for-20250928 queue Harsh Prateek Bora
2025-09-28 19:26 ` [PULL 01/27] ppc/pnv: Introduce Pnv11Chip Harsh Prateek Bora
2025-09-28 19:26 ` [PULL 02/27] ppc/pnv: Introduce Power11 PowerNV machine Harsh Prateek Bora
2025-09-28 19:26 ` [PULL 03/27] ppc/pnv: Add PnvChipClass handler to get reference to interrupt controller Harsh Prateek Bora
2025-09-28 19:26 ` [PULL 04/27] ppc/pnv: Add XIVE2 controller to Power11 Harsh Prateek Bora
2025-09-28 19:26 ` [PULL 05/27] ppc/pnv: Add PHB5 PCIe Host bridge " Harsh Prateek Bora
2025-09-28 19:26 ` [PULL 06/27] ppc/pnv: Add ChipTOD model for Power11 Harsh Prateek Bora
2025-09-28 19:26 ` [PULL 07/27] tests/powernv: Switch to buildroot images instead of op-build Harsh Prateek Bora
2025-09-28 19:26 ` [PULL 08/27] tests/powernv: Add PowerNV test for Power11 Harsh Prateek Bora
2025-09-28 19:26 ` Harsh Prateek Bora [this message]
2025-09-28 19:26 ` [PULL 10/27] target/ppc: Add IBM PPE42 family of processors Harsh Prateek Bora
2025-09-28 19:26 ` [PULL 11/27] target/ppc: IBM PPE42 exception flags and regs Harsh Prateek Bora
2025-09-28 19:26 ` [PULL 12/27] target/ppc: Add IBM PPE42 exception model Harsh Prateek Bora
2025-09-28 19:26 ` [PULL 13/27] target/ppc: Support for IBM PPE42 MMU Harsh Prateek Bora
2025-09-28 19:26 ` [PULL 14/27] target/ppc: Add IBM PPE42 special instructions Harsh Prateek Bora
2025-09-28 19:26 ` [PULL 15/27] hw/ppc: Support for an IBM PPE42 CPU decrementer Harsh Prateek Bora
2025-09-28 19:26 ` [PULL 16/27] hw/ppc: Add a test machine for the IBM PPE42 CPU Harsh Prateek Bora
2025-09-28 19:26 ` [PULL 17/27] tests/functional: Add test for IBM PPE42 instructions Harsh Prateek Bora
2025-09-28 19:26 ` [PULL 18/27] hw/intc/xics: Add missing call to register vmstate_icp_server Harsh Prateek Bora
2025-09-29 19:32 ` Michael Tokarev
2025-09-30 4:15 ` Harsh Prateek Bora
2025-09-28 19:26 ` [PULL 19/27] ppc/spapr: init lrdr-capapcity phys with ram size if maxmem not provided Harsh Prateek Bora
2025-09-29 19:36 ` Michael Tokarev
2025-09-30 4:18 ` Harsh Prateek Bora
2025-09-28 19:26 ` [PULL 20/27] ppc/xive2: Fix integer overflow warning in xive2_redistribute() Harsh Prateek Bora
2025-09-28 19:26 ` [PULL 21/27] target/ppc: Move floating-point rounding and conversion instructions to decodetree Harsh Prateek Bora
2025-09-28 19:26 ` [PULL 22/27] target/ppc: Move floating-point compare " Harsh Prateek Bora
2025-09-28 19:26 ` [PULL 23/27] target/ppc: Move floating-point move " Harsh Prateek Bora
2025-09-28 19:26 ` [PULL 24/27] target/ppc: Move remaining " Harsh Prateek Bora
2025-09-28 19:26 ` [PULL 25/27] target/ppc: Introduce macro for deprecating PowerPC CPUs Harsh Prateek Bora
2025-09-28 19:26 ` [PULL 26/27] target/ppc: Deprecate Power8E and Power8NVL Harsh Prateek Bora
2025-09-28 19:26 ` [PULL 27/27] target/ppc: use MAKE_64BIT_MASK for mcrfs exception clear mask Harsh Prateek Bora
2025-09-29 16:50 ` [PULL 00/27] ppc-for-20250928 queue Richard Henderson
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