From: "Cédric Le Goater" <clg@redhat.com>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: "Jamin Lin" <jamin_lin@aspeedtech.com>,
"Cédric Le Goater" <clg@redhat.com>
Subject: [PULL 28/32] hw/arm/aspeed: Move write_boot_rom to common SoC code
Date: Mon, 29 Sep 2025 18:52:26 +0200 [thread overview]
Message-ID: <20250929165230.797471-29-clg@redhat.com> (raw)
In-Reply-To: <20250929165230.797471-1-clg@redhat.com>
From: Jamin Lin <jamin_lin@aspeedtech.com>
Move the write_boot_rom helper from hw/arm/aspeed.c into
hw/arm/aspeed_soc_common.c so it can be reused by all ASPEED
machines. Export the API as aspeed_write_boot_rom() in
include/hw/arm/aspeed_soc.h and update the existing call site
to use the new helper.
No functional change.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250925050535.2657256-3-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
include/hw/arm/aspeed_soc.h | 2 ++
hw/arm/aspeed.c | 33 ++-------------------------------
hw/arm/aspeed_soc_common.c | 31 +++++++++++++++++++++++++++++++
3 files changed, 35 insertions(+), 31 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index aaf518d1799e..5567bdcb699f 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -312,6 +312,8 @@ void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
uint64_t size);
void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
unsigned int count, int unit0);
+void aspeed_write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size,
+ Error **errp);
static inline int aspeed_uart_index(int uart_dev)
{
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 55f0afe0a499..4d0d93583659 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -263,35 +263,6 @@ static void aspeed_reset_secondary(ARMCPU *cpu,
cpu_set_pc(cs, info->smp_loader_start);
}
-static void write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size,
- Error **errp)
-{
- g_autofree void *storage = NULL;
- int64_t size;
-
- /*
- * The block backend size should have already been 'validated' by
- * the creation of the m25p80 object.
- */
- size = blk_getlength(blk);
- if (size <= 0) {
- error_setg(errp, "failed to get flash size");
- return;
- }
-
- if (rom_size > size) {
- rom_size = size;
- }
-
- storage = g_malloc0(rom_size);
- if (blk_pread(blk, 0, rom_size, storage, 0) < 0) {
- error_setg(errp, "failed to read the initial flash content");
- return;
- }
-
- rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr);
-}
-
/*
* Create a ROM and copy the flash contents at the expected address
* (0x0). Boots faster than execute-in-place.
@@ -306,8 +277,8 @@ static void aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk,
&error_abort);
memory_region_add_subregion_overlap(&soc->spi_boot_container, 0,
&bmc->boot_rom, 1);
- write_boot_rom(blk, sc->memmap[ASPEED_DEV_SPI_BOOT],
- rom_size, &error_abort);
+ aspeed_write_boot_rom(blk, sc->memmap[ASPEED_DEV_SPI_BOOT], rom_size,
+ &error_abort);
}
#define VBOOTROM_FILE_NAME "ast27x0_bootrom.bin"
diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c
index 31b1e683c375..d0a400725f24 100644
--- a/hw/arm/aspeed_soc_common.c
+++ b/hw/arm/aspeed_soc_common.c
@@ -17,6 +17,8 @@
#include "hw/arm/aspeed_soc.h"
#include "hw/char/serial-mm.h"
#include "system/blockdev.h"
+#include "system/block-backend.h"
+#include "hw/loader.h"
const char *aspeed_soc_cpu_type(AspeedSoCClass *sc)
@@ -147,6 +149,35 @@ void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
}
}
+void aspeed_write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size,
+ Error **errp)
+{
+ g_autofree void *storage = NULL;
+ int64_t size;
+
+ /*
+ * The block backend size should have already been 'validated' by
+ * the creation of the m25p80 object.
+ */
+ size = blk_getlength(blk);
+ if (size <= 0) {
+ error_setg(errp, "failed to get flash size");
+ return;
+ }
+
+ if (rom_size > size) {
+ rom_size = size;
+ }
+
+ storage = g_malloc0(rom_size);
+ if (blk_pread(blk, 0, rom_size, storage, 0) < 0) {
+ error_setg(errp, "failed to read the initial flash content");
+ return;
+ }
+
+ rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr);
+}
+
static void aspeed_soc_realize(DeviceState *dev, Error **errp)
{
AspeedSoCState *s = ASPEED_SOC(dev);
--
2.51.0
next prev parent reply other threads:[~2025-09-29 16:59 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-29 16:51 [PULL 00/32] aspeed queue Cédric Le Goater
2025-09-29 16:51 ` [PULL 01/32] hw/nvram/aspeed_otp: Add ASPEED OTP memory device model Cédric Le Goater
2025-09-29 16:52 ` [PULL 02/32] hw/misc/aspeed_sbc: Connect ASPEED OTP memory device to SBC Cédric Le Goater
2025-09-29 16:52 ` [PULL 03/32] hw/arm: Integrate ASPEED OTP memory support into AST2600 SoCs Cédric Le Goater
2025-09-29 16:52 ` [PULL 04/32] hw/nvram/aspeed_otp: Add 'drive' property to support block backend Cédric Le Goater
2025-09-29 16:52 ` [PULL 05/32] hw/nvram/aspeed_otp: Add OTP programming semantics and tracing Cédric Le Goater
2025-09-29 16:52 ` [PULL 06/32] hw/arm: Integrate ASPEED OTP memory support into AST1030 SoCs Cédric Le Goater
2025-09-29 16:52 ` [PULL 07/32] hw/misc/aspeed_sbc: Add CAMP2 support for OTP data reads Cédric Le Goater
2025-09-29 16:52 ` [PULL 08/32] hw/misc/aspeed_sbc: Handle OTP write command for voltage mode registers Cédric Le Goater
2025-09-29 16:52 ` [PULL 09/32] docs/system/arm/aspeed: Document OTP memory options Cédric Le Goater
2025-09-29 16:52 ` [PULL 10/32] hw/arm/aspeed Move ast2700-evb alias to ast2700a1-evb Cédric Le Goater
2025-09-29 16:52 ` [PULL 11/32] tests/functional/arm: Add helper to generate OTP images Cédric Le Goater
2025-09-29 16:52 ` [PULL 12/32] tests/functional/arm: Add AST1030 boot test with generated OTP image Cédric Le Goater
2025-09-29 16:52 ` [PULL 13/32] tests/functional/arm: Add AST2600 " Cédric Le Goater
2025-09-29 16:52 ` [PULL 14/32] hw/pci/pci_ids: Add PCI vendor ID for ASPEED Cédric Le Goater
2025-09-29 16:52 ` [PULL 15/32] hw/pci-host/aspeed: Add AST2600 PCIe PHY model Cédric Le Goater
2025-09-29 16:52 ` [PULL 16/32] hw/pci-host/aspeed: Add AST2600 PCIe config space and host bridge Cédric Le Goater
2025-09-29 16:52 ` [PULL 17/32] hw/pci-host/aspeed: Add AST2600 PCIe Root Device support Cédric Le Goater
2025-09-29 16:52 ` [PULL 18/32] hw/pci-host/aspeed: Add AST2600 PCIe Root Port and make address configurable Cédric Le Goater
2025-09-29 16:52 ` [PULL 19/32] hw/pci-host/aspeed: Add MSI support and per-RC IOMMU address space Cédric Le Goater
2025-09-29 16:52 ` [PULL 20/32] hw/arm/aspeed: Wire up PCIe devices in SoC model Cédric Le Goater
2025-09-29 16:52 ` [PULL 21/32] hw/arm/aspeed_ast2600: Add PCIe RC support (RC_H only) Cédric Le Goater
2025-09-29 16:52 ` [PULL 22/32] hw/pci-host/aspeed: Add AST2700 PCIe PHY Cédric Le Goater
2025-09-29 16:52 ` [PULL 23/32] hw/pci-host/aspeed: Add AST2700 PCIe config with dedicated H2X blocks Cédric Le Goater
2025-09-29 16:52 ` [PULL 24/32] hw/pci-host/aspeed: Disable Root Device and place Root Port at 00:00.0 to AST2700 Cédric Le Goater
2025-09-29 16:52 ` [PULL 25/32] hw/arm/aspeed_ast27x0: Introduce 3 PCIe RCs for AST2700 Cédric Le Goater
2025-09-29 16:52 ` [PULL 26/32] tests/functional/arm/test_aspeed_ast2600: Add PCIe and network test Cédric Le Goater
2025-09-29 16:52 ` [PULL 27/32] hw/arm/aspeed: Move aspeed_board_init_flashes() to common SoC code Cédric Le Goater
2025-09-29 16:52 ` Cédric Le Goater [this message]
2025-09-29 16:52 ` [PULL 29/32] hw/arm/aspeed: Move aspeed_install_boot_rom " Cédric Le Goater
2025-09-29 16:52 ` [PULL 30/32] hw/arm/aspeed: Move aspeed_load_vbootrom " Cédric Le Goater
2025-09-29 16:52 ` [PULL 31/32] hw/arm/aspeed_ast27x0-fc: Drop dead return checks Cédric Le Goater
2025-09-29 16:52 ` [PULL 32/32] hw/arm/aspeed_ast27x0-fc: Make sub-init functions return bool with errp Cédric Le Goater
2025-09-30 14:10 ` [PULL 00/32] aspeed queue Richard Henderson
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