From: "Cédric Le Goater" <clg@redhat.com>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: "Jamin Lin" <jamin_lin@aspeedtech.com>,
"Cédric Le Goater" <clg@redhat.com>
Subject: [PULL 32/32] hw/arm/aspeed_ast27x0-fc: Make sub-init functions return bool with errp
Date: Mon, 29 Sep 2025 18:52:30 +0200 [thread overview]
Message-ID: <20250929165230.797471-33-clg@redhat.com> (raw)
In-Reply-To: <20250929165230.797471-1-clg@redhat.com>
From: Jamin Lin <jamin_lin@aspeedtech.com>
Refactor ast2700fc_ca35_init(), ast2700fc_ssp_init(), and ast2700fc_tsp_init()
to take an Error **errp parameter and return a bool.
Each function now reports failure through the error object and returns false.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250925050535.2657256-7-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
hw/arm/aspeed_ast27x0-fc.c | 34 ++++++++++++++++++++--------------
1 file changed, 20 insertions(+), 14 deletions(-)
diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
index ebf3784df588..2e16a0340a7b 100644
--- a/hw/arm/aspeed_ast27x0-fc.c
+++ b/hw/arm/aspeed_ast27x0-fc.c
@@ -56,7 +56,7 @@ struct Ast2700FCState {
#define AST2700FC_FMC_MODEL "w25q01jvq"
#define AST2700FC_SPI_MODEL "w25q512jv"
-static void ast2700fc_ca35_init(MachineState *machine)
+static bool ast2700fc_ca35_init(MachineState *machine, Error **errp)
{
Ast2700FCState *s = AST2700A1FC(machine);
AspeedSoCState *soc;
@@ -71,8 +71,8 @@ static void ast2700fc_ca35_init(MachineState *machine)
memory_region_add_subregion(get_system_memory(), 0, &s->ca35_memory);
if (!memory_region_init_ram(&s->ca35_dram, OBJECT(&s->ca35), "ca35-dram",
- AST2700FC_BMC_RAM_SIZE, &error_abort)) {
- return;
+ AST2700FC_BMC_RAM_SIZE, errp)) {
+ return false;
}
object_property_set_link(OBJECT(&s->ca35), "memory",
OBJECT(&s->ca35_memory), &error_abort);
@@ -92,8 +92,8 @@ static void ast2700fc_ca35_init(MachineState *machine)
object_property_set_int(OBJECT(&s->ca35), "hw-strap2",
AST2700FC_HW_STRAP2, &error_abort);
aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART12, serial_hd(0));
- if (!qdev_realize(DEVICE(&s->ca35), NULL, &error_abort)) {
- return;
+ if (!qdev_realize(DEVICE(&s->ca35), NULL, errp)) {
+ return false;
}
/*
@@ -108,9 +108,11 @@ static void ast2700fc_ca35_init(MachineState *machine)
ast2700fc_board_info.loader_start = sc->memmap[ASPEED_DEV_SDRAM];
arm_load_kernel(ARM_CPU(first_cpu), machine, &ast2700fc_board_info);
+
+ return true;
}
-static void ast2700fc_ssp_init(MachineState *machine)
+static bool ast2700fc_ssp_init(MachineState *machine, Error **errp)
{
AspeedSoCState *soc;
Ast2700FCState *s = AST2700A1FC(machine);
@@ -127,12 +129,14 @@ static void ast2700fc_ssp_init(MachineState *machine)
soc = ASPEED_SOC(&s->ssp);
aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART4, serial_hd(1));
- if (!qdev_realize(DEVICE(&s->ssp), NULL, &error_abort)) {
- return;
+ if (!qdev_realize(DEVICE(&s->ssp), NULL, errp)) {
+ return false;
}
+
+ return true;
}
-static void ast2700fc_tsp_init(MachineState *machine)
+static bool ast2700fc_tsp_init(MachineState *machine, Error **errp)
{
AspeedSoCState *soc;
Ast2700FCState *s = AST2700A1FC(machine);
@@ -149,16 +153,18 @@ static void ast2700fc_tsp_init(MachineState *machine)
soc = ASPEED_SOC(&s->tsp);
aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART7, serial_hd(2));
- if (!qdev_realize(DEVICE(&s->tsp), NULL, &error_abort)) {
- return;
+ if (!qdev_realize(DEVICE(&s->tsp), NULL, errp)) {
+ return false;
}
+
+ return true;
}
static void ast2700fc_init(MachineState *machine)
{
- ast2700fc_ca35_init(machine);
- ast2700fc_ssp_init(machine);
- ast2700fc_tsp_init(machine);
+ ast2700fc_ca35_init(machine, &error_abort);
+ ast2700fc_ssp_init(machine, &error_abort);
+ ast2700fc_tsp_init(machine, &error_abort);
}
static void ast2700fc_class_init(ObjectClass *oc, const void *data)
--
2.51.0
next prev parent reply other threads:[~2025-09-29 16:57 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-29 16:51 [PULL 00/32] aspeed queue Cédric Le Goater
2025-09-29 16:51 ` [PULL 01/32] hw/nvram/aspeed_otp: Add ASPEED OTP memory device model Cédric Le Goater
2025-09-29 16:52 ` [PULL 02/32] hw/misc/aspeed_sbc: Connect ASPEED OTP memory device to SBC Cédric Le Goater
2025-09-29 16:52 ` [PULL 03/32] hw/arm: Integrate ASPEED OTP memory support into AST2600 SoCs Cédric Le Goater
2025-09-29 16:52 ` [PULL 04/32] hw/nvram/aspeed_otp: Add 'drive' property to support block backend Cédric Le Goater
2025-09-29 16:52 ` [PULL 05/32] hw/nvram/aspeed_otp: Add OTP programming semantics and tracing Cédric Le Goater
2025-09-29 16:52 ` [PULL 06/32] hw/arm: Integrate ASPEED OTP memory support into AST1030 SoCs Cédric Le Goater
2025-09-29 16:52 ` [PULL 07/32] hw/misc/aspeed_sbc: Add CAMP2 support for OTP data reads Cédric Le Goater
2025-09-29 16:52 ` [PULL 08/32] hw/misc/aspeed_sbc: Handle OTP write command for voltage mode registers Cédric Le Goater
2025-09-29 16:52 ` [PULL 09/32] docs/system/arm/aspeed: Document OTP memory options Cédric Le Goater
2025-09-29 16:52 ` [PULL 10/32] hw/arm/aspeed Move ast2700-evb alias to ast2700a1-evb Cédric Le Goater
2025-09-29 16:52 ` [PULL 11/32] tests/functional/arm: Add helper to generate OTP images Cédric Le Goater
2025-09-29 16:52 ` [PULL 12/32] tests/functional/arm: Add AST1030 boot test with generated OTP image Cédric Le Goater
2025-09-29 16:52 ` [PULL 13/32] tests/functional/arm: Add AST2600 " Cédric Le Goater
2025-09-29 16:52 ` [PULL 14/32] hw/pci/pci_ids: Add PCI vendor ID for ASPEED Cédric Le Goater
2025-09-29 16:52 ` [PULL 15/32] hw/pci-host/aspeed: Add AST2600 PCIe PHY model Cédric Le Goater
2025-09-29 16:52 ` [PULL 16/32] hw/pci-host/aspeed: Add AST2600 PCIe config space and host bridge Cédric Le Goater
2025-09-29 16:52 ` [PULL 17/32] hw/pci-host/aspeed: Add AST2600 PCIe Root Device support Cédric Le Goater
2025-09-29 16:52 ` [PULL 18/32] hw/pci-host/aspeed: Add AST2600 PCIe Root Port and make address configurable Cédric Le Goater
2025-09-29 16:52 ` [PULL 19/32] hw/pci-host/aspeed: Add MSI support and per-RC IOMMU address space Cédric Le Goater
2025-09-29 16:52 ` [PULL 20/32] hw/arm/aspeed: Wire up PCIe devices in SoC model Cédric Le Goater
2025-09-29 16:52 ` [PULL 21/32] hw/arm/aspeed_ast2600: Add PCIe RC support (RC_H only) Cédric Le Goater
2025-09-29 16:52 ` [PULL 22/32] hw/pci-host/aspeed: Add AST2700 PCIe PHY Cédric Le Goater
2025-09-29 16:52 ` [PULL 23/32] hw/pci-host/aspeed: Add AST2700 PCIe config with dedicated H2X blocks Cédric Le Goater
2025-09-29 16:52 ` [PULL 24/32] hw/pci-host/aspeed: Disable Root Device and place Root Port at 00:00.0 to AST2700 Cédric Le Goater
2025-09-29 16:52 ` [PULL 25/32] hw/arm/aspeed_ast27x0: Introduce 3 PCIe RCs for AST2700 Cédric Le Goater
2025-09-29 16:52 ` [PULL 26/32] tests/functional/arm/test_aspeed_ast2600: Add PCIe and network test Cédric Le Goater
2025-09-29 16:52 ` [PULL 27/32] hw/arm/aspeed: Move aspeed_board_init_flashes() to common SoC code Cédric Le Goater
2025-09-29 16:52 ` [PULL 28/32] hw/arm/aspeed: Move write_boot_rom " Cédric Le Goater
2025-09-29 16:52 ` [PULL 29/32] hw/arm/aspeed: Move aspeed_install_boot_rom " Cédric Le Goater
2025-09-29 16:52 ` [PULL 30/32] hw/arm/aspeed: Move aspeed_load_vbootrom " Cédric Le Goater
2025-09-29 16:52 ` [PULL 31/32] hw/arm/aspeed_ast27x0-fc: Drop dead return checks Cédric Le Goater
2025-09-29 16:52 ` Cédric Le Goater [this message]
2025-09-30 14:10 ` [PULL 00/32] aspeed queue Richard Henderson
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