From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9F3B9CCA468 for ; Mon, 29 Sep 2025 15:56:05 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v3GCs-0004LI-Gh; Mon, 29 Sep 2025 11:54:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v3GCl-0003yX-N3; Mon, 29 Sep 2025 11:54:24 -0400 Received: from [185.176.79.56] (helo=frasgout.his.huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v3GCc-0001Tn-Dt; Mon, 29 Sep 2025 11:54:17 -0400 Received: from mail.maildlp.com (unknown [172.18.186.216]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4cb5KN0zb4z6L4xv; Mon, 29 Sep 2025 23:51:52 +0800 (CST) Received: from dubpeml100005.china.huawei.com (unknown [7.214.146.113]) by mail.maildlp.com (Postfix) with ESMTPS id EAF37140133; Mon, 29 Sep 2025 23:53:59 +0800 (CST) Received: from localhost (10.47.79.72) by dubpeml100005.china.huawei.com (7.214.146.113) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Mon, 29 Sep 2025 16:53:58 +0100 Date: Mon, 29 Sep 2025 16:53:51 +0100 To: Shameer Kolothum CC: , , , , , , , , , , , , , , , , Subject: Re: [PATCH v4 05/27] hw/arm/smmuv3-accel: Introduce smmuv3 accel device Message-ID: <20250929165351.000063a5@huawei.com> In-Reply-To: <20250929133643.38961-6-skolothumtho@nvidia.com> References: <20250929133643.38961-1-skolothumtho@nvidia.com> <20250929133643.38961-6-skolothumtho@nvidia.com> X-Mailer: Claws Mail 4.3.0 (GTK 3.24.42; x86_64-w64-mingw32) MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.47.79.72] X-ClientProxiedBy: lhrpeml100011.china.huawei.com (7.191.174.247) To dubpeml100005.china.huawei.com (7.214.146.113) X-Host-Lookup-Failed: Reverse DNS lookup failed for 185.176.79.56 (deferred) Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron From: Jonathan Cameron via Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon, 29 Sep 2025 14:36:21 +0100 Shameer Kolothum wrote: > Set up dedicated PCIIOMMUOps for the accel SMMUv3, since it will need > different callback handling in upcoming patches. This also adds a > CONFIG_ARM_SMMUV3_ACCEL build option so the feature can be disabled > at compile time. Because we now include CONFIG_DEVICES in the header to > check for ARM_SMMUV3_ACCEL, the meson file entry for smmuv3.c needs to > be changed as well. >=20 > The =E2=80=9Caccel=E2=80=9D property isn=E2=80=99t user visible yet, it w= ill be introduced in > a later patch once all the supporting pieces are ready. >=20 > Reviewed-by: Nicolin Chen > Signed-off-by: Shameer Kolothum All the code looks fine, just comment stuff. Reviewed-by: Jonathan Cameron > diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h > index d183a62766..bb7076286b 100644 > --- a/include/hw/arm/smmuv3.h > +++ b/include/hw/arm/smmuv3.h > @@ -63,6 +63,9 @@ struct SMMUv3State { > qemu_irq irq[4]; > QemuMutex mutex; > char *stage; > + > + /* SMMU has HW accelerator support for nested S1 + s2 */ s1 + s2 or S1 + S2 (probably the second) > + bool accel; > }; > =20 > typedef enum {