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Tue, 30 Sep 2025 03:22:33 +0000 Received: from offworld.lan (syn-076-167-199-067.res.spectrum.com [76.167.199.67]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: dave@stgolabs.net) by pdx1-sub0-mail-a315.dreamhost.com (Postfix) with ESMTPSA id 4cbNfJ0CXlzR4; Mon, 29 Sep 2025 20:22:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=stgolabs.net; s=dreamhost; t=1759202552; bh=4HKJL5h1ARnqVldpjrYAQKbNdJpIoNaPV8mz4ta3ep8=; h=From:To:Cc:Subject:Date:Content-Transfer-Encoding; b=kwJgGbM5MNibHxtXtt7p6ZAZeoHbXFdfUuB8jaW2BAdUwu3e41HrrIIr2B7wVS0Vx VQyGgfmdu8SWpSiM3ADjqU29tbdQUVUG+z3NhvuOeYG2dmlySBrdvvYSsfi2WplsYi mlHazcw6iRY5ysG2XNjDuMO1g+aDsUbfATjJYNlmYOt/VEvul+oMGHifTwVtpDSOpE mm94JBIlJK70Nga4gyQMXbSenoRtyinxfYTng9BBxTzcSVVeRS6zkZ+/kGim+pu1DH l6djMlbsNKQjUr/isaWXWbUF7JZrdOX3e8/qaEB+lrDF4uRm7OJm46bHjw1AWuC284 mdcA5cYuQ7RVg== From: Davidlohr Bueso To: jonathan.cameron@huawei.com Cc: ira.weiny@intel.com, lucerop@amd.com, a.manzanares@samsung.com, mst@redhat.com, marcel.apfelbaum@gmail.com, armbru@redhat.com, linux-cxl@vger.kernel.org, qemu-devel@nongnu.org, dave@stgolabs.net Subject: [PATCH v3 -qemu 0/5] hw/cxl: Support Back-Invalidate Date: Mon, 29 Sep 2025 20:21:48 -0700 Message-Id: <20250930032153.1127773-1-dave@stgolabs.net> X-Mailer: git-send-email 2.39.5 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=23.83.222.61; envelope-from=dave@stgolabs.net; helo=fly.ash.relay.mailchannels.net X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hello, The following allows support for component basic back invalidation discovery and config, by exposing the BI routing table and decoder registers. Instead of going the type2[0] route, this series proposes adding support for type3 hdm-db, which allows a more direct way of supporting BI in qemu. Changes from v2 (https://lore.kernel.org/linux-cxl/20250811033405.332295-1-dave@stgolabs.net/): o Renamed 256b-flit to x-256b-flit (mst) o Added a brief description of flit mode in patch 1 changelog (Markus) o Added missing hdm-db parameter which went missing in v2. o Replaced the new CXL3_TYPE3_DEVICE with passing 'bi' params. (Jonathan) o Fixed writemask bits in patch 4. (Jonathan) o Misc cleanups in patch 4. (Jonathan) o New patch 5 to remove register special_ops read() cb. (Jonathan) Changes from v1 (https://lore.kernel.org/qemu-devel/20250806055708.196851-1-dave@stgolabs.net/): o Further lnk training in patch 1. (Jonathan) o Flit parameter changed to bool in patch 1. (Jonathan) o Do not set 68B in component Flexbus Port when in flitmode in patch 1. o Doc build fixlet in patch 3. o Pass the exact type3 type in cxl_component_create_dvsec() - unused, but better for keeping track, in patch 4. o Change doc example to volatile device in patch 4. Changes from rfc (https://lore.kernel.org/qemu-devel/20250729165441.1898150-1-dave@stgolabs.net/): o Added 256b-flit parameter, per Jonathan. o Added window restrictions changes. o Dropped rfc tag. Patch 1 introduces the flit mode parameter. Patch 2 is lifted from Ira's series with some small (but non-trivial) changes. Patch 3 updates the cfmw restrictions option. Patch 4 adds BI decoder/rt register support to enable type3 HDM-DB. Patch 5 is a small cleanup. Testing wise, this has passed relevant kernel side BI register IO flows for BI-ID setup and deallocation. The next step for this would be to add UIO support to qemu. Applies against branch 'origin/cxl-2025-07-03' from Jonathan's repository. Thanks! Davidlohr Bueso (4): hw/pcie: Support enabling flit mode hw/cxl: Allow BI by default in Window restrictions hw/cxl: Support type3 HDM-DB hw/cxl: Remove register special_ops->read() Ira Weiny (1): hw/cxl: Refactor component register initialization docs/system/devices/cxl.rst | 23 +++ hw/cxl/cxl-component-utils.c | 214 ++++++++++++++++------ hw/cxl/cxl-host.c | 2 +- hw/mem/cxl_type3.c | 18 +- hw/pci-bridge/cxl_downstream.c | 13 +- hw/pci-bridge/cxl_root_port.c | 14 +- hw/pci-bridge/cxl_upstream.c | 21 ++- hw/pci-bridge/gen_pcie_root_port.c | 1 + hw/pci-bridge/pci_expander_bridge.c | 2 +- hw/pci/pcie.c | 23 ++- include/hw/cxl/cxl_component.h | 87 +++++++-- include/hw/cxl/cxl_device.h | 4 + include/hw/pci-bridge/cxl_upstream_port.h | 1 + include/hw/pci/pcie.h | 2 +- include/hw/pci/pcie_port.h | 1 + qapi/machine.json | 3 +- qemu-options.hx | 4 +- 17 files changed, 329 insertions(+), 104 deletions(-) -- 2.39.5