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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-46e5b69bc0bsm5141855e9.3.2025.09.29.21.14.07 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 29 Sep 2025 21:14:08 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Peter Maydell Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jason Herne , Stefano Stabellini , Stefano Garzarella , xen-devel@lists.xenproject.org, Paolo Bonzini , Ilya Leoshkevich , Anthony PERARD , Paul Durrant , Eric Farman , Marcelo Tosatti , Halil Pasic , Matthew Rosato , Reinoud Zandijk , Zhao Liu , David Woodhouse , Christian Borntraeger , Sunil Muthuswamy , kvm@vger.kernel.org, "Michael S. Tsirkin" , Peter Xu , Thomas Huth , qemu-s390x@nongnu.org, "Edgar E. Iglesias" , Richard Henderson , David Hildenbrand Subject: [PATCH v2 07/17] system/physmem: Pass address space argument to cpu_flush_icache_range() Date: Tue, 30 Sep 2025 06:13:15 +0200 Message-ID: <20250930041326.6448-8-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250930041326.6448-1-philmd@linaro.org> References: <20250930041326.6448-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Rename cpu_flush_icache_range() as address_space_flush_icache_range(), passing an address space by argument. The single caller, rom_reset(), already operates on an address space. Use it. Signed-off-by: Philippe Mathieu-Daudé --- include/exec/cpu-common.h | 2 -- include/system/memory.h | 2 ++ hw/core/loader.c | 2 +- system/physmem.c | 5 ++--- 4 files changed, 5 insertions(+), 6 deletions(-) diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index a73463a7038..6c7d84aacb4 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -156,8 +156,6 @@ void cpu_physical_memory_unmap(void *buffer, hwaddr len, */ void qemu_flush_coalesced_mmio_buffer(void); -void cpu_flush_icache_range(hwaddr start, hwaddr len); - typedef int (RAMBlockIterFunc)(RAMBlock *rb, void *opaque); int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque); diff --git a/include/system/memory.h b/include/system/memory.h index 546c643961d..dfea90c4d6b 100644 --- a/include/system/memory.h +++ b/include/system/memory.h @@ -2977,6 +2977,8 @@ void address_space_cache_invalidate(MemoryRegionCache *cache, */ void address_space_cache_destroy(MemoryRegionCache *cache); +void address_space_flush_icache_range(AddressSpace *as, hwaddr addr, hwaddr len); + /* address_space_get_iotlb_entry: translate an address into an IOTLB * entry. Should be called from an RCU critical section. */ diff --git a/hw/core/loader.c b/hw/core/loader.c index 524af6f14a0..477661a0255 100644 --- a/hw/core/loader.c +++ b/hw/core/loader.c @@ -1242,7 +1242,7 @@ static void rom_reset(void *unused) * that the instruction cache for that new region is clear, so that the * CPU definitely fetches its instructions from the just written data. */ - cpu_flush_icache_range(rom->addr, rom->datasize); + address_space_flush_icache_range(rom->as, rom->addr, rom->datasize); trace_loader_write_rom(rom->name, rom->addr, rom->datasize, rom->isrom); } diff --git a/system/physmem.c b/system/physmem.c index 573e5bb1adc..70b02675b93 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -3214,7 +3214,7 @@ MemTxResult address_space_write_rom(AddressSpace *as, hwaddr addr, return MEMTX_OK; } -void cpu_flush_icache_range(hwaddr addr, hwaddr len) +void address_space_flush_icache_range(AddressSpace *as, hwaddr addr, hwaddr len) { /* * This function should do the same thing as an icache flush that was @@ -3229,8 +3229,7 @@ void cpu_flush_icache_range(hwaddr addr, hwaddr len) RCU_READ_LOCK_GUARD(); while (len > 0) { hwaddr addr1, l = len; - MemoryRegion *mr = address_space_translate(&address_space_memory, - addr, &addr1, &l, true, + MemoryRegion *mr = address_space_translate(as, addr, &addr1, &l, true, MEMTXATTRS_UNSPECIFIED); if (!memory_region_supports_direct_access(mr)) { -- 2.51.0