From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B2697CAC5BB for ; Wed, 1 Oct 2025 07:38:59 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v3rJM-0005iq-NG; Wed, 01 Oct 2025 03:31:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v3rJH-0005gA-7k for qemu-devel@nongnu.org; Wed, 01 Oct 2025 03:31:36 -0400 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v3rIo-0003U7-I4 for qemu-devel@nongnu.org; Wed, 01 Oct 2025 03:31:34 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=KAz3l9YySJarbQvayNbfOjIKxzpWIYxG8ANwOuW1THY=; b=ne2LpQA32grXiN3 azCFqcGjQSp2a5NmwpkFJK7EoThv7SM/BhS/l/MaRkMpLjT1fFYDloNNrum5dJ62DaKzDF2QL9svP TGMGeJHCYFg9fZniHafZtPhXCivmjVksDmEotC2NLd3e66FA6pVdyEyEawwJoY9Sa93mT/wjQqUgv UU=; To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org, richard.henderson@linaro.org, alistair.francis@wdc.com, palmer@dabbelt.com Subject: [PATCH v2 14/33] target/riscv: Fix size of guest_phys_fault_addr Date: Wed, 1 Oct 2025 09:32:47 +0200 Message-ID: <20251001073306.28573-15-anjo@rev.ng> In-Reply-To: <20251001073306.28573-1-anjo@rev.ng> References: <20251001073306.28573-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Widen to 64 bits, and use hwaddr as argument to get_physical_address(). Signed-off-by: Anton Johansson --- target/riscv/cpu.h | 2 +- target/riscv/cpu_helper.c | 3 +-- target/riscv/machine.c | 2 +- 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9e3b6b6879..fcca4dfe49 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -236,7 +236,7 @@ struct CPUArchState { uint64_t badaddr; uint64_t bins; - target_ulong guest_phys_fault_addr; + uint64_t guest_phys_fault_addr; target_ulong priv_ver; target_ulong vext_ver; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 36f7baf690..c9594b8719 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1186,7 +1186,7 @@ static bool check_svukte_addr(CPURISCVState *env, vaddr addr) */ static int get_physical_address(CPURISCVState *env, hwaddr *physical, int *ret_prot, vaddr addr, - target_ulong *fault_pte_addr, + hwaddr *fault_pte_addr, int access_type, int mmu_idx, bool first_stage, bool two_stage, bool is_debug, bool is_probe) @@ -1787,7 +1787,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, ret = get_physical_address(env, &pa, &prot, address, &env->guest_phys_fault_addr, access_type, mmu_idx, true, true, false, probe); - /* * A G-stage exception may be triggered during two state lookup. * And the env->guest_phys_fault_addr has already been set in diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 7aafe5f5dd..1bac57a60b 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -413,7 +413,7 @@ const VMStateDescription vmstate_riscv_cpu = { VMSTATE_UINT64(env.load_val, RISCVCPU), VMSTATE_UINT8(env.frm, RISCVCPU), VMSTATE_UINT64(env.badaddr, RISCVCPU), - VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU), + VMSTATE_UINT64(env.guest_phys_fault_addr, RISCVCPU), VMSTATE_UINTTL(env.priv_ver, RISCVCPU), VMSTATE_UINTTL(env.vext_ver, RISCVCPU), VMSTATE_UINT32(env.misa_mxl, RISCVCPU), -- 2.51.0