From: Anton Johansson via <qemu-devel@nongnu.org>
To: qemu-devel@nongnu.org
Cc: pierrick.bouvier@linaro.org, philmd@linaro.org,
richard.henderson@linaro.org, alistair.francis@wdc.com,
palmer@dabbelt.com
Subject: [PATCH v2 31/33] target/riscv: Move CSR declarations to separate csr.h header
Date: Wed, 1 Oct 2025 09:33:04 +0200 [thread overview]
Message-ID: <20251001073306.28573-32-anjo@rev.ng> (raw)
In-Reply-To: <20251001073306.28573-1-anjo@rev.ng>
Most of these definitions save riscv_csrr, riscv_csrrw, riscv_csr_read,
riscv_csr_write are only used in target/. Move declarations to a
separate headers which will soon be made internal to target/.
csr.h is temporarily included from cpu.h to not break includes from
outside target/, this include will be removed in the following commit.
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
target/riscv/cpu.h | 82 +--------------------------------
target/riscv/csr.h | 94 ++++++++++++++++++++++++++++++++++++++
target/riscv/cpu.c | 1 +
target/riscv/csr.c | 1 +
target/riscv/gdbstub.c | 1 +
target/riscv/kvm/kvm-cpu.c | 1 +
target/riscv/op_helper.c | 1 +
target/riscv/th_csr.c | 1 +
8 files changed, 101 insertions(+), 81 deletions(-)
create mode 100644 target/riscv/csr.h
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 70e0f3718c..61319575b0 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -849,75 +849,7 @@ RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env);
RISCVPmPmm riscv_pm_get_virt_pmm(CPURISCVState *env);
uint32_t riscv_pm_get_pmlen(RISCVPmPmm pmm);
-RISCVException riscv_csrr(CPURISCVState *env, int csrno,
- target_ulong *ret_value);
-
-RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
- target_ulong *ret_value, target_ulong new_value,
- target_ulong write_mask, uintptr_t ra);
-RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
- target_ulong *ret_value,
- target_ulong new_value,
- target_ulong write_mask);
-
-static inline void riscv_csr_write(CPURISCVState *env, int csrno,
- target_ulong val)
-{
- riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS), 0);
-}
-
-static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
-{
- target_ulong val = 0;
- riscv_csrrw(env, csrno, &val, 0, 0, 0);
- return val;
-}
-
-typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env,
- int csrno);
-typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
- target_ulong *ret_value);
-typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
- target_ulong new_value,
- uintptr_t ra);
-typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
- target_ulong *ret_value,
- target_ulong new_value,
- target_ulong write_mask);
-
-RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
- Int128 *ret_value);
-RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
- Int128 *ret_value, Int128 new_value,
- Int128 write_mask, uintptr_t ra);
-
-typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno,
- Int128 *ret_value);
-typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno,
- Int128 new_value);
-
-typedef struct {
- const char *name;
- riscv_csr_predicate_fn predicate;
- riscv_csr_read_fn read;
- riscv_csr_write_fn write;
- riscv_csr_op_fn op;
- riscv_csr_read128_fn read128;
- riscv_csr_write128_fn write128;
- /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */
- uint32_t min_priv_ver;
-} riscv_csr_operations;
-
-struct RISCVCSR {
- int csrno;
- bool (*insertion_test)(RISCVCPU *cpu);
- riscv_csr_operations csr_ops;
-};
-
-/* CSR function table constants */
-enum {
- CSR_TABLE_SIZE = 0x1000
-};
+#include "csr.h"
/*
* The event id are encoded based on the encoding specified in the
@@ -961,23 +893,11 @@ void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp);
void riscv_add_satp_mode_properties(Object *obj);
bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu);
-/* CSR function table */
-extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
-
extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[];
-void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
-void riscv_set_csr_ops(int csrno, const riscv_csr_operations *ops);
-
void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
-target_ulong riscv_new_csr_seed(target_ulong new_value,
- target_ulong write_mask);
-
const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
-/* In th_csr.c */
-extern const RISCVCSR th_csr_list[];
-
const char *priv_spec_to_str(int priv_version);
#endif /* RISCV_CPU_H */
diff --git a/target/riscv/csr.h b/target/riscv/csr.h
new file mode 100644
index 0000000000..fab53992bb
--- /dev/null
+++ b/target/riscv/csr.h
@@ -0,0 +1,94 @@
+/*
+ * QEMU RISC-V CSRs
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
+ * Copyright (c) 2017-2018 SiFive, Inc.
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef RISCV_CSR_H
+#define RISCV_CSR_H
+
+target_ulong riscv_new_csr_seed(target_ulong new_value,
+ target_ulong write_mask);
+
+RISCVException riscv_csrr(CPURISCVState *env, int csrno,
+ target_ulong *ret_value);
+
+RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
+ target_ulong *ret_value, target_ulong new_value,
+ target_ulong write_mask, uintptr_t ra);
+RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
+ target_ulong *ret_value,
+ target_ulong new_value,
+ target_ulong write_mask);
+
+static inline void riscv_csr_write(CPURISCVState *env, int csrno,
+ target_ulong val)
+{
+ riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS), 0);
+}
+
+static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
+{
+ target_ulong val = 0;
+ riscv_csrrw(env, csrno, &val, 0, 0, 0);
+ return val;
+}
+
+typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env,
+ int csrno);
+typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
+ target_ulong *ret_value);
+typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
+ target_ulong new_value,
+ uintptr_t ra);
+typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
+ target_ulong *ret_value,
+ target_ulong new_value,
+ target_ulong write_mask);
+
+RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
+ Int128 *ret_value);
+RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
+ Int128 *ret_value, Int128 new_value,
+ Int128 write_mask, uintptr_t ra);
+
+typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno,
+ Int128 *ret_value);
+typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno,
+ Int128 new_value);
+
+typedef struct {
+ const char *name;
+ riscv_csr_predicate_fn predicate;
+ riscv_csr_read_fn read;
+ riscv_csr_write_fn write;
+ riscv_csr_op_fn op;
+ riscv_csr_read128_fn read128;
+ riscv_csr_write128_fn write128;
+ /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */
+ uint32_t min_priv_ver;
+} riscv_csr_operations;
+
+struct RISCVCSR {
+ int csrno;
+ bool (*insertion_test)(RISCVCPU *cpu);
+ riscv_csr_operations csr_ops;
+};
+
+/* CSR function table constants */
+enum {
+ CSR_TABLE_SIZE = 0x1000
+};
+
+/* CSR function table */
+extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
+
+void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
+void riscv_set_csr_ops(int csrno, const riscv_csr_operations *ops);
+
+/* In th_csr.c */
+extern const RISCVCSR th_csr_list[];
+
+#endif /* RISCV_CSR_H */
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 246ec81beb..d8d06f92bc 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -23,6 +23,7 @@
#include "qemu/log.h"
#include "cpu.h"
#include "cpu_vendorid.h"
+#include "csr.h"
#include "internals.h"
#include "qapi/error.h"
#include "qapi/visitor.h"
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 0e7236098b..3ebfd19b07 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -22,6 +22,7 @@
#include "qemu/log.h"
#include "qemu/timer.h"
#include "cpu.h"
+#include "csr.h"
#include "tcg/tcg-cpu.h"
#include "pmu.h"
#include "time_helper.h"
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 1934f919c0..f8d3bc0df1 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -20,6 +20,7 @@
#include "exec/gdbstub.h"
#include "gdbstub/helpers.h"
#include "cpu.h"
+#include "csr.h"
struct TypeSize {
const char *gdb_type;
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index 5c19062c19..ad58e84158 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -31,6 +31,7 @@
#include "system/kvm.h"
#include "system/kvm_int.h"
#include "cpu.h"
+#include "csr.h"
#include "trace.h"
#include "accel/accel-cpu-target.h"
#include "hw/pci/pci.h"
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 110292e84d..d2d9f2a47a 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -20,6 +20,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
+#include "csr.h"
#include "internals.h"
#include "exec/cputlb.h"
#include "accel/tcg/cpu-ldst.h"
diff --git a/target/riscv/th_csr.c b/target/riscv/th_csr.c
index 49eb7bbab5..bf6f8d62a3 100644
--- a/target/riscv/th_csr.c
+++ b/target/riscv/th_csr.c
@@ -19,6 +19,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "cpu_vendorid.h"
+#include "csr.h"
#define CSR_TH_SXSTATUS 0x5c0
--
2.51.0
next prev parent reply other threads:[~2025-10-01 7:42 UTC|newest]
Thread overview: 99+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-01 7:32 [PATCH v2 00/33] single-binary: Make riscv cpu.h target independent Anton Johansson via
2025-10-01 7:32 ` [PATCH v2 01/33] target/riscv: Use 32 bits for misa extensions Anton Johansson via
2025-10-01 7:34 ` Philippe Mathieu-Daudé
2025-10-02 1:56 ` Alistair Francis
2025-10-02 18:31 ` Pierrick Bouvier
2025-10-01 7:32 ` [PATCH v2 02/33] target/riscv: Fix size of trivial CPUArchState fields Anton Johansson via
2025-10-02 1:57 ` Alistair Francis
2025-10-02 18:31 ` Pierrick Bouvier
2025-10-01 7:32 ` [PATCH v2 03/33] target/riscv: Fix size of mhartid Anton Johansson via
2025-10-01 7:38 ` Philippe Mathieu-Daudé
2025-10-01 8:28 ` Anton Johansson via
2025-10-02 18:34 ` Pierrick Bouvier
2025-10-01 7:32 ` [PATCH v2 04/33] target/riscv: Bugfix riscv_pmu_ctr_get_fixed_counters_val() Anton Johansson via
2025-10-02 18:50 ` Pierrick Bouvier
2025-10-02 23:34 ` Alistair Francis
2025-10-07 11:08 ` Anton Johansson via
2025-10-15 2:55 ` Alistair Francis
2025-10-15 9:58 ` Anton Johansson via
2025-10-16 4:01 ` Alistair Francis
2025-10-17 14:24 ` Anton Johansson via
2025-10-23 1:54 ` Alistair Francis
2025-10-01 7:32 ` [PATCH v2 05/33] target/riscv: Combine mhpmevent and mhpmeventh Anton Johansson via
2025-10-01 7:39 ` Philippe Mathieu-Daudé
2025-10-02 19:09 ` Pierrick Bouvier
2025-10-02 23:52 ` Alistair Francis
2025-10-02 19:08 ` Pierrick Bouvier
2025-10-02 19:33 ` Pierrick Bouvier
2025-10-02 23:55 ` Alistair Francis
2025-10-07 11:29 ` Anton Johansson via
2025-10-14 11:25 ` Anton Johansson via
2025-10-01 7:32 ` [PATCH v2 06/33] target/riscv: Combine mcyclecfg and mcyclecfgh Anton Johansson via
2025-10-02 19:13 ` Pierrick Bouvier
2025-10-03 0:05 ` Alistair Francis
2025-10-01 7:32 ` [PATCH v2 07/33] target/riscv: Combine minstretcfg and minstretcfgh Anton Johansson via
2025-10-02 19:14 ` Pierrick Bouvier
2025-10-03 0:06 ` Alistair Francis
2025-10-01 7:32 ` [PATCH v2 08/33] target/riscv: Combine mhpmcounter and mhpmcounterh Anton Johansson via
2025-10-02 19:24 ` Pierrick Bouvier
2025-10-02 19:25 ` Pierrick Bouvier
2025-10-01 7:32 ` [PATCH v2 09/33] target/riscv: Fix size of gpr and gprh Anton Johansson via
2025-10-01 7:42 ` Philippe Mathieu-Daudé
2025-10-03 9:00 ` Anton Johansson via
2025-10-01 7:32 ` [PATCH v2 10/33] target/riscv: Fix size of vector CSRs Anton Johansson via
2025-10-02 19:42 ` Pierrick Bouvier
2025-10-01 7:32 ` [PATCH v2 11/33] target/riscv: Fix size of pc, load_[val|res] Anton Johansson via
2025-10-02 19:54 ` Pierrick Bouvier
2025-10-03 12:43 ` Anton Johansson via
2025-10-01 7:32 ` [PATCH v2 12/33] target/riscv: Fix size of frm and fflags Anton Johansson via
2025-10-02 19:57 ` Pierrick Bouvier
2025-10-01 7:32 ` [PATCH v2 13/33] target/riscv: Fix size of badaddr and bins Anton Johansson via
2025-10-02 20:02 ` Pierrick Bouvier
2025-10-01 7:32 ` [PATCH v2 14/33] target/riscv: Fix size of guest_phys_fault_addr Anton Johansson via
2025-10-02 20:03 ` Pierrick Bouvier
2025-10-01 7:32 ` [PATCH v2 15/33] target/riscv: Fix size of priv_ver and vext_ver Anton Johansson via
2025-10-02 20:03 ` Pierrick Bouvier
2025-10-01 7:32 ` [PATCH v2 16/33] target/riscv: Fix size of retxh Anton Johansson via
2025-10-02 20:05 ` Pierrick Bouvier
2025-10-01 7:32 ` [PATCH v2 17/33] target/riscv: Fix size of ssp Anton Johansson via
2025-10-02 20:06 ` Pierrick Bouvier
2025-10-01 7:32 ` [PATCH v2 18/33] target/riscv: Fix size of excp_uw2 Anton Johansson via
2025-10-02 20:06 ` Pierrick Bouvier
2025-10-01 7:32 ` [PATCH v2 19/33] target/riscv: Fix size of sw_check_code Anton Johansson via
2025-10-02 20:07 ` Pierrick Bouvier
2025-10-01 7:32 ` [PATCH v2 20/33] target/riscv: Fix size of priv Anton Johansson via
2025-10-02 20:07 ` Pierrick Bouvier
2025-10-01 7:32 ` [PATCH v2 21/33] target/riscv: Fix size of gei fields Anton Johansson via
2025-10-02 20:08 ` Pierrick Bouvier
2025-10-01 7:32 ` [PATCH v2 22/33] target/riscv: Fix size of [m|s|vs]iselect fields Anton Johansson via
2025-10-02 20:09 ` Pierrick Bouvier
2025-10-01 7:32 ` [PATCH v2 23/33] target/riscv: Fix arguments to board IMSIC emulation callbacks Anton Johansson via
2025-10-02 20:15 ` Pierrick Bouvier
2025-10-01 7:32 ` [PATCH v2 24/33] target/riscv: Fix size of irq_overflow_left Anton Johansson via
2025-10-02 20:15 ` Pierrick Bouvier
2025-10-01 7:32 ` [PATCH v2 25/33] target/riscv: Indent PMUFixedCtrState correctly Anton Johansson via
2025-10-01 7:43 ` Philippe Mathieu-Daudé
2025-10-02 20:15 ` Pierrick Bouvier
2025-10-01 7:32 ` [PATCH v2 26/33] target/riscv: Replace target_ulong in riscv_cpu_get_trap_name() Anton Johansson via
2025-10-01 7:43 ` Philippe Mathieu-Daudé
2025-10-02 20:15 ` Pierrick Bouvier
2025-10-01 7:33 ` [PATCH v2 27/33] target/riscv: Replace target_ulong in riscv_ctr_add_entry() Anton Johansson via
2025-10-01 7:44 ` Philippe Mathieu-Daudé
2025-10-02 20:19 ` Pierrick Bouvier
2025-10-01 7:33 ` [PATCH v2 28/33] target/riscv: Fix size of trigger data Anton Johansson via
2025-10-01 7:46 ` Philippe Mathieu-Daudé
2025-10-02 20:19 ` Pierrick Bouvier
2025-10-01 7:33 ` [PATCH v2 29/33] target/riscv: Fix size of mseccfg Anton Johansson via
2025-10-01 7:46 ` Philippe Mathieu-Daudé
2025-10-02 20:20 ` Pierrick Bouvier
2025-10-01 7:33 ` [PATCH v2 30/33] target/riscv: Move debug.h include away from cpu.h Anton Johansson via
2025-10-02 20:21 ` Pierrick Bouvier
2025-10-03 12:52 ` Anton Johansson via
2025-10-01 7:33 ` Anton Johansson via [this message]
2025-10-02 20:22 ` [PATCH v2 31/33] target/riscv: Move CSR declarations to separate csr.h header Pierrick Bouvier
2025-10-01 7:33 ` [PATCH v2 32/33] target/riscv: Introduce externally facing CSR access functions Anton Johansson via
2025-10-02 20:24 ` Pierrick Bouvier
2025-10-01 7:33 ` [PATCH v2 33/33] target/riscv: Make pmp.h target_ulong agnostic Anton Johansson via
2025-10-01 7:49 ` Philippe Mathieu-Daudé
2025-10-03 12:57 ` Anton Johansson via
2025-10-02 20:23 ` Pierrick Bouvier
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20251001073306.28573-32-anjo@rev.ng \
--to=qemu-devel@nongnu.org \
--cc=alistair.francis@wdc.com \
--cc=anjo@rev.ng \
--cc=palmer@dabbelt.com \
--cc=philmd@linaro.org \
--cc=pierrick.bouvier@linaro.org \
--cc=richard.henderson@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).