From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AD7A9CCA476 for ; Wed, 1 Oct 2025 07:40:56 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v3rIz-0005VV-4H; Wed, 01 Oct 2025 03:31:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v3rIm-0005Nn-Qr for qemu-devel@nongnu.org; Wed, 01 Oct 2025 03:31:05 -0400 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v3rIW-0003QW-AS for qemu-devel@nongnu.org; Wed, 01 Oct 2025 03:31:04 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=GfRGNeKJNA1ivwc6t9OAJNjeh/GFPkRWaFmHAiJfeVk=; b=NFKpJKuxk15hjwY a7Wb/ybGl7/Rm7ypR3VDHkFv+y/Zkm0TVgdPYR3rVaMxntwsqir6wfLxnymWQSSt0nJLyHMcIrx7o 4EKMxxtC2mGNDLTNWChQSacxdBK0+SL2+fIlexYsPXjfvuQ9uKVyFsiePGdAYjA52Y0JVbOe3XMSJ JY=; To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org, richard.henderson@linaro.org, alistair.francis@wdc.com, palmer@dabbelt.com Subject: [PATCH v2 04/33] target/riscv: Bugfix riscv_pmu_ctr_get_fixed_counters_val() Date: Wed, 1 Oct 2025 09:32:37 +0200 Message-ID: <20251001073306.28573-5-anjo@rev.ng> In-Reply-To: <20251001073306.28573-1-anjo@rev.ng> References: <20251001073306.28573-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, T_SPF_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org >From my understanding the upper_half argument only indicates whether the upper or lower 32 bits should be returned, and upper_half will only ever be set when MXLEN == 32. However, the function also uses upper_half to determine whether the inhibit flags are located in mcyclecfgh or mcyclecfg, but this misses the case where MXLEN == 32, upper_half == false for TARGET_RISCV32 where we would also need to read the upper half field. Minor simplifications are also made along with some formatting fixes. Signed-off-by: Anton Johansson --- target/riscv/csr.c | 22 ++++++++++------------ 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 3c8989f522..859f89aedd 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -17,6 +17,7 @@ * this program. If not, see . */ +#include "cpu_bits.h" #include "qemu/osdep.h" #include "qemu/log.h" #include "qemu/timer.h" @@ -1241,18 +1242,21 @@ static target_ulong riscv_pmu_ctr_get_fixed_counters_val(CPURISCVState *env, int inst = riscv_pmu_ctr_monitor_instructions(env, counter_idx); uint64_t *counter_arr_virt = env->pmu_fixed_ctrs[inst].counter_virt; uint64_t *counter_arr = env->pmu_fixed_ctrs[inst].counter; - target_ulong result = 0; uint64_t curr_val = 0; uint64_t cfg_val = 0; + bool rv32 = riscv_cpu_mxl(env) == MXL_RV32; + + /* Ensure upper_half is only set for MXL_RV32 */ + g_assert(rv32 || !upper_half); if (counter_idx == 0) { - cfg_val = upper_half ? ((uint64_t)env->mcyclecfgh << 32) : + cfg_val = rv32 ? ((uint64_t)env->mcyclecfgh << 32) : env->mcyclecfg; } else if (counter_idx == 2) { - cfg_val = upper_half ? ((uint64_t)env->minstretcfgh << 32) : + cfg_val = rv32 ? ((uint64_t)env->minstretcfgh << 32) : env->minstretcfg; } else { - cfg_val = upper_half ? + cfg_val = rv32 ? ((uint64_t)env->mhpmeventh_val[counter_idx] << 32) : env->mhpmevent_val[counter_idx]; cfg_val &= MHPMEVENT_FILTER_MASK; @@ -1260,7 +1264,7 @@ static target_ulong riscv_pmu_ctr_get_fixed_counters_val(CPURISCVState *env, if (!cfg_val) { if (icount_enabled()) { - curr_val = inst ? icount_get_raw() : icount_get(); + curr_val = inst ? icount_get_raw() : icount_get(); } else { curr_val = cpu_get_host_ticks(); } @@ -1292,13 +1296,7 @@ static target_ulong riscv_pmu_ctr_get_fixed_counters_val(CPURISCVState *env, } done: - if (riscv_cpu_mxl(env) == MXL_RV32) { - result = upper_half ? curr_val >> 32 : curr_val; - } else { - result = curr_val; - } - - return result; + return upper_half ? curr_val >> 32 : curr_val; } static RISCVException riscv_pmu_write_ctr(CPURISCVState *env, target_ulong val, -- 2.51.0