From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9B884CAC5BB for ; Wed, 1 Oct 2025 13:45:46 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v3x7b-0006XZ-PH; Wed, 01 Oct 2025 09:43:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v3x7U-0006Wr-M7; Wed, 01 Oct 2025 09:43:48 -0400 Received: from [185.176.79.56] (helo=frasgout.his.huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v3x7D-000383-CL; Wed, 01 Oct 2025 09:43:44 -0400 Received: from mail.maildlp.com (unknown [172.18.186.31]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4ccGKT6x32z6L4sH; Wed, 1 Oct 2025 21:41:01 +0800 (CST) Received: from dubpeml100005.china.huawei.com (unknown [7.214.146.113]) by mail.maildlp.com (Postfix) with ESMTPS id 3483114014C; Wed, 1 Oct 2025 21:43:15 +0800 (CST) Received: from localhost (10.203.177.15) by dubpeml100005.china.huawei.com (7.214.146.113) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 1 Oct 2025 14:43:14 +0100 Date: Wed, 1 Oct 2025 14:43:12 +0100 To: Shameer Kolothum CC: , , , , , , , , , , , , , , , , Subject: Re: [PATCH v4 22/27] hw/arm/smmuv3-accel: Add support for ATS Message-ID: <20251001144312.00006085@huawei.com> In-Reply-To: <20250929133643.38961-23-skolothumtho@nvidia.com> References: <20250929133643.38961-1-skolothumtho@nvidia.com> <20250929133643.38961-23-skolothumtho@nvidia.com> X-Mailer: Claws Mail 4.3.0 (GTK 3.24.42; x86_64-w64-mingw32) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.203.177.15] X-ClientProxiedBy: lhrpeml100010.china.huawei.com (7.191.174.197) To dubpeml100005.china.huawei.com (7.214.146.113) X-Host-Lookup-Failed: Reverse DNS lookup failed for 185.176.79.56 (deferred) Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron From: Jonathan Cameron via Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon, 29 Sep 2025 14:36:38 +0100 Shameer Kolothum wrote: > QEMU SMMUv3 does not enable ATS (Address Translation Services) by default. > When accelerated mode is enabled and the host SMMUv3 supports ATS, it can > be useful to report ATS capability to the guest so it can take advantage > of it if the device also supports ATS. > > Note: ATS support cannot be reliably detected from the host SMMUv3 IDR > registers alone, as firmware ACPI IORT tables may override them. The > user must therefore ensure the support before enabling it. > > Signed-off-by: Shameer Kolothum Trivial stuff only. Reviewed-by: Jonathan Cameron Feels like there should be some host mechanism we could query for support but if not I guess the 'don't set it wrong' comment is the best we can do. > --- > hw/arm/smmuv3-accel.c | 4 ++++ > hw/arm/smmuv3.c | 25 ++++++++++++++++++++++++- > hw/arm/virt-acpi-build.c | 10 ++++++++-- > include/hw/arm/smmuv3.h | 1 + > 4 files changed, 37 insertions(+), 3 deletions(-) > > diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c > index e8607b253e..eee54316bf 100644 > --- a/hw/arm/smmuv3-accel.c > +++ b/hw/arm/smmuv3-accel.c > @@ -644,6 +644,10 @@ void smmuv3_accel_idr_override(SMMUv3State *s) > if (!s->ril) { > s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, 0); > } > + /* QEMU SMMUv3 has no ATS. Update IDR0 if user has enabled it */ > + if (s->ats) { > + s->idr[0] = FIELD_DP32(s->idr[0], IDR0, ATS, 1); /* ATS */ Not sure the comment adds anything given the field name! > + } > } > > /* > diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c > index 0f3a61646a..77d46a9cd6 100644 > --- a/hw/arm/smmuv3.c > +++ b/hw/arm/smmuv3.c > @@ -1510,13 +1510,28 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) > */ > smmuv3_range_inval(bs, &cmd, SMMU_STAGE_2); > break; > + case SMMU_CMD_ATC_INV: > + { > + SMMUDevice *sdev = smmu_find_sdev(bs, CMD_SID(&cmd)); > + Error *local_err = NULL; > + > + if (!sdev) { > + break; > + } > + > + if (!smmuv3_accel_issue_inv_cmd(s, &cmd, sdev, &local_err)) { > + error_report_err(local_err); > + cmd_error = SMMU_CERROR_ILL; > + break; > + } > + break; > + } > case SMMU_CMD_TLBI_EL3_ALL: > case SMMU_CMD_TLBI_EL3_VA: > case SMMU_CMD_TLBI_EL2_ALL: > case SMMU_CMD_TLBI_EL2_ASID: > case SMMU_CMD_TLBI_EL2_VA: > case SMMU_CMD_TLBI_EL2_VAA: > - case SMMU_CMD_ATC_INV: > case SMMU_CMD_PRI_RESP: > case SMMU_CMD_RESUME: > case SMMU_CMD_STALL_TERM: > @@ -1934,6 +1949,10 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp) > error_setg(errp, "ril can only be disabled if accel=on"); > return false; > } > + if (s->ats) { > + error_setg(errp, "ats can only be enabled if accel=on"); > + return false; Comment in previous patch follow through here... > + } > return true; > } > diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c > index d0c1e10019..a53f0229b8 100644 > --- a/hw/arm/virt-acpi-build.c > +++ b/hw/arm/virt-acpi-build.c