From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org,
"Richard Henderson" <richard.henderson@linaro.org>,
qemu-riscv@nongnu.org, "Peter Maydell" <peter.maydell@linaro.org>,
qemu-ppc@nongnu.org, "Paolo Bonzini" <pbonzini@redhat.com>,
"Pierrick Bouvier" <pierrick.bouvier@linaro.org>,
"Peter Xu" <peterx@redhat.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PATCH 10/22] target/alpha: Get cpu first addr space with cpu_get_address_space()
Date: Wed, 1 Oct 2025 17:05:15 +0200 [thread overview]
Message-ID: <20251001150529.14122-11-philmd@linaro.org> (raw)
In-Reply-To: <20251001150529.14122-1-philmd@linaro.org>
In order to remove the convenient CPUState::as field, access
the vcpu first address space using the cpu_get_address_space()
helper.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/alpha/helper.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/target/alpha/helper.c b/target/alpha/helper.c
index 096eac34458..8819f0b6cb5 100644
--- a/target/alpha/helper.c
+++ b/target/alpha/helper.c
@@ -175,6 +175,7 @@ static int get_physical_address(CPUAlphaState *env, target_ulong addr,
target_ulong pt, index;
int prot = 0;
int ret = MM_K_ACV;
+ AddressSpace *as;
/* Handle physical accesses. */
if (mmu_idx == MMU_PHYS_IDX) {
@@ -211,6 +212,7 @@ static int get_physical_address(CPUAlphaState *env, target_ulong addr,
/* Interpret the page table exactly like PALcode does. */
+ as = cpu_get_address_space(cs, 0);
pt = env->ptbr;
/* TODO: rather than using ldq_phys() to read the page table we should
@@ -223,7 +225,7 @@ static int get_physical_address(CPUAlphaState *env, target_ulong addr,
/* L1 page table read. */
index = (addr >> (TARGET_PAGE_BITS + 20)) & 0x3ff;
- L1pte = ldq_phys(cs->as, pt + index*8);
+ L1pte = ldq_phys(as, pt + index*8);
if (unlikely((L1pte & PTE_VALID) == 0)) {
ret = MM_K_TNV;
@@ -236,7 +238,7 @@ static int get_physical_address(CPUAlphaState *env, target_ulong addr,
/* L2 page table read. */
index = (addr >> (TARGET_PAGE_BITS + 10)) & 0x3ff;
- L2pte = ldq_phys(cs->as, pt + index*8);
+ L2pte = ldq_phys(as, pt + index*8);
if (unlikely((L2pte & PTE_VALID) == 0)) {
ret = MM_K_TNV;
@@ -249,7 +251,7 @@ static int get_physical_address(CPUAlphaState *env, target_ulong addr,
/* L3 page table read. */
index = (addr >> TARGET_PAGE_BITS) & 0x3ff;
- L3pte = ldq_phys(cs->as, pt + index*8);
+ L3pte = ldq_phys(as, pt + index*8);
phys = L3pte >> 32 << TARGET_PAGE_BITS;
if (unlikely((L3pte & PTE_VALID) == 0)) {
--
2.51.0
next prev parent reply other threads:[~2025-10-01 15:10 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-01 15:05 [PATCH 00/22] hw/core/cpu: Remove @CPUState::as field Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 01/22] system/qtest: Use &address_space_memory for first vCPU address space Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 02/22] disas/disas-mon: Get cpu first addr space with cpu_get_address_space() Philippe Mathieu-Daudé
2025-10-01 15:34 ` BALATON Zoltan
2025-10-01 15:05 ` [PATCH 03/22] monitor/hmp-cmds: " Philippe Mathieu-Daudé
2025-10-01 15:35 ` BALATON Zoltan
2025-10-01 16:23 ` Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 04/22] hw/core/loader: " Philippe Mathieu-Daudé
2025-10-01 15:08 ` Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 05/22] hw/ppc: " Philippe Mathieu-Daudé
2025-10-01 15:23 ` Miles Glenn
2025-10-01 15:05 ` [PATCH 06/22] hw/m86k: " Philippe Mathieu-Daudé
2025-10-18 5:52 ` Thomas Huth
2025-10-01 15:05 ` [PATCH 07/22] target/xtensa: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 08/22] target/riscv: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 09/22] semihosting: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` Philippe Mathieu-Daudé [this message]
2025-10-01 15:05 ` [PATCH 11/22] target/arm: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 12/22] target/hppa: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 13/22] target/i386: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 14/22] target/loongarch: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 15/22] target/m68k: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 16/22] target/microblaze: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 17/22] target/ppc: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 18/22] target/s390x: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 19/22] target/sparc: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 20/22] hw/core/cpu: Remove @CPUState::as field Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 21/22] exec/cpu: Declare cpu_memory_rw_debug() in 'hw/core/cpu.h' and document Philippe Mathieu-Daudé
2025-10-06 19:08 ` Philippe Mathieu-Daudé
2025-10-08 16:25 ` Zhao Liu
2025-10-01 15:05 ` [PATCH 22/22] target/sparc: Reduce inclusions of 'exec/cpu-common.h' Philippe Mathieu-Daudé
2025-10-01 15:39 ` [PATCH 00/22] hw/core/cpu: Remove @CPUState::as field BALATON Zoltan
2025-10-01 16:08 ` Peter Maydell
2025-10-01 16:35 ` Richard Henderson
2025-10-01 16:42 ` Philippe Mathieu-Daudé
2025-10-01 18:38 ` Philippe Mathieu-Daudé
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