From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org,
"Richard Henderson" <richard.henderson@linaro.org>,
qemu-riscv@nongnu.org, "Peter Maydell" <peter.maydell@linaro.org>,
qemu-ppc@nongnu.org, "Paolo Bonzini" <pbonzini@redhat.com>,
"Pierrick Bouvier" <pierrick.bouvier@linaro.org>,
"Peter Xu" <peterx@redhat.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Nicholas Piggin" <npiggin@gmail.com>,
"Chinmay Rath" <rathc@linux.ibm.com>
Subject: [PATCH 17/22] target/ppc: Get cpu first addr space with cpu_get_address_space()
Date: Wed, 1 Oct 2025 17:05:22 +0200 [thread overview]
Message-ID: <20251001150529.14122-18-philmd@linaro.org> (raw)
In-Reply-To: <20251001150529.14122-1-philmd@linaro.org>
In order to remove the convenient CPUState::as field, access
the vcpu first address space using the cpu_get_address_space()
helper.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/ppc/mmu-hash32.h | 12 ++++++++----
target/ppc/excp_helper.c | 4 ++--
target/ppc/mmu-book3s-v3.c | 5 +++--
target/ppc/mmu-hash32.c | 6 ++++--
target/ppc/mmu-hash64.c | 12 ++++++++----
target/ppc/mmu-radix64.c | 13 +++++++------
6 files changed, 32 insertions(+), 20 deletions(-)
diff --git a/target/ppc/mmu-hash32.h b/target/ppc/mmu-hash32.h
index 04c23ea75ed..f49991e8651 100644
--- a/target/ppc/mmu-hash32.h
+++ b/target/ppc/mmu-hash32.h
@@ -74,33 +74,37 @@ static inline hwaddr ppc_hash32_hpt_mask(PowerPCCPU *cpu)
static inline target_ulong ppc_hash32_load_hpte0(PowerPCCPU *cpu,
hwaddr pte_offset)
{
+ AddressSpace *as = cpu_get_address_space(CPU(cpu), 0);
target_ulong base = ppc_hash32_hpt_base(cpu);
- return ldl_phys(CPU(cpu)->as, base + pte_offset);
+ return ldl_phys(as, base + pte_offset);
}
static inline target_ulong ppc_hash32_load_hpte1(PowerPCCPU *cpu,
hwaddr pte_offset)
{
+ AddressSpace *as = cpu_get_address_space(CPU(cpu), 0);
target_ulong base = ppc_hash32_hpt_base(cpu);
- return ldl_phys(CPU(cpu)->as, base + pte_offset + HASH_PTE_SIZE_32 / 2);
+ return ldl_phys(as, base + pte_offset + HASH_PTE_SIZE_32 / 2);
}
static inline void ppc_hash32_store_hpte0(PowerPCCPU *cpu,
hwaddr pte_offset, target_ulong pte0)
{
+ AddressSpace *as = cpu_get_address_space(CPU(cpu), 0);
target_ulong base = ppc_hash32_hpt_base(cpu);
- stl_phys(CPU(cpu)->as, base + pte_offset, pte0);
+ stl_phys(as, base + pte_offset, pte0);
}
static inline void ppc_hash32_store_hpte1(PowerPCCPU *cpu,
hwaddr pte_offset, target_ulong pte1)
{
+ AddressSpace *as = cpu_get_address_space(CPU(cpu), 0);
target_ulong base = ppc_hash32_hpt_base(cpu);
- stl_phys(CPU(cpu)->as, base + pte_offset + HASH_PTE_SIZE_32 / 2, pte1);
+ stl_phys(as, base + pte_offset + HASH_PTE_SIZE_32 / 2, pte1);
}
static inline hwaddr get_pteg_offset32(PowerPCCPU *cpu, hwaddr hash)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 1efdc4066eb..6dbcf4dae10 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -1012,9 +1012,9 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
break;
case POWERPC_EXCP_EXTERNAL: /* External input */
if (env->mpic_proxy) {
- CPUState *cs = env_cpu(env);
+ AddressSpace *as = cpu_get_address_space(env_cpu(env), 0);
/* IACK the IRQ on delivery */
- env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
+ env->spr[SPR_BOOKE_EPR] = ldl_phys(as, env->mpic_iack);
}
break;
case POWERPC_EXCP_ALIGN: /* Alignment exception */
diff --git a/target/ppc/mmu-book3s-v3.c b/target/ppc/mmu-book3s-v3.c
index 38655563105..fb8dd3df8c4 100644
--- a/target/ppc/mmu-book3s-v3.c
+++ b/target/ppc/mmu-book3s-v3.c
@@ -25,6 +25,7 @@
bool ppc64_v3_get_pate(PowerPCCPU *cpu, target_ulong lpid, ppc_v3_pate_t *entry)
{
+ AddressSpace *as = cpu_get_address_space(CPU(cpu), 0);
uint64_t patb = cpu->env.spr[SPR_PTCR] & PTCR_PATB;
uint64_t pats = cpu->env.spr[SPR_PTCR] & PTCR_PATS;
@@ -41,7 +42,7 @@ bool ppc64_v3_get_pate(PowerPCCPU *cpu, target_ulong lpid, ppc_v3_pate_t *entry)
/* Grab entry */
patb += 16 * lpid;
- entry->dw0 = ldq_phys(CPU(cpu)->as, patb);
- entry->dw1 = ldq_phys(CPU(cpu)->as, patb + 8);
+ entry->dw0 = ldq_phys(as, patb);
+ entry->dw1 = ldq_phys(as, patb + 8);
return true;
}
diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c
index 8b980a5aa90..957184fd2e9 100644
--- a/target/ppc/mmu-hash32.c
+++ b/target/ppc/mmu-hash32.c
@@ -235,20 +235,22 @@ static hwaddr ppc_hash32_pteg_search(PowerPCCPU *cpu, hwaddr pteg_off,
static void ppc_hash32_set_r(PowerPCCPU *cpu, hwaddr pte_offset, uint32_t pte1)
{
+ AddressSpace *as = cpu_get_address_space(CPU(cpu), 0);
target_ulong base = ppc_hash32_hpt_base(cpu);
hwaddr offset = pte_offset + 6;
/* The HW performs a non-atomic byte update */
- stb_phys(CPU(cpu)->as, base + offset, ((pte1 >> 8) & 0xff) | 0x01);
+ stb_phys(as, base + offset, ((pte1 >> 8) & 0xff) | 0x01);
}
static void ppc_hash32_set_c(PowerPCCPU *cpu, hwaddr pte_offset, uint64_t pte1)
{
+ AddressSpace *as = cpu_get_address_space(CPU(cpu), 0);
target_ulong base = ppc_hash32_hpt_base(cpu);
hwaddr offset = pte_offset + 7;
/* The HW performs a non-atomic byte update */
- stb_phys(CPU(cpu)->as, base + offset, (pte1 & 0xff) | 0x80);
+ stb_phys(as, base + offset, (pte1 & 0xff) | 0x80);
}
static hwaddr ppc_hash32_htab_lookup(PowerPCCPU *cpu,
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index dd337558aa6..52db16ded5b 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -552,6 +552,7 @@ static hwaddr ppc_hash64_hpt_mask(PowerPCCPU *cpu)
const ppc_hash_pte64_t *ppc_hash64_map_hptes(PowerPCCPU *cpu,
hwaddr ptex, int n)
{
+ AddressSpace *as = cpu_get_address_space(CPU(cpu), 0);
hwaddr pte_offset = ptex * HASH_PTE_SIZE_64;
hwaddr base;
hwaddr plen = n * HASH_PTE_SIZE_64;
@@ -566,7 +567,7 @@ const ppc_hash_pte64_t *ppc_hash64_map_hptes(PowerPCCPU *cpu,
return NULL;
}
- hptes = address_space_map(CPU(cpu)->as, base + pte_offset, &plen, false,
+ hptes = address_space_map(as, base + pte_offset, &plen, false,
MEMTXATTRS_UNSPECIFIED);
if (plen < (n * HASH_PTE_SIZE_64)) {
hw_error("%s: Unable to map all requested HPTEs\n", __func__);
@@ -577,12 +578,13 @@ const ppc_hash_pte64_t *ppc_hash64_map_hptes(PowerPCCPU *cpu,
void ppc_hash64_unmap_hptes(PowerPCCPU *cpu, const ppc_hash_pte64_t *hptes,
hwaddr ptex, int n)
{
+ AddressSpace *as = cpu_get_address_space(CPU(cpu), 0);
if (cpu->vhyp) {
cpu->vhyp_class->unmap_hptes(cpu->vhyp, hptes, ptex, n);
return;
}
- address_space_unmap(CPU(cpu)->as, (void *)hptes, n * HASH_PTE_SIZE_64,
+ address_space_unmap(as, (void *)hptes, n * HASH_PTE_SIZE_64,
false, n * HASH_PTE_SIZE_64);
}
@@ -864,6 +866,7 @@ static void ppc_hash64_set_dsi(CPUState *cs, int mmu_idx, uint64_t slb_vsid,
static void ppc_hash64_set_r(PowerPCCPU *cpu, hwaddr ptex, uint64_t pte1)
{
+ AddressSpace *as = cpu_get_address_space(CPU(cpu), 0);
hwaddr base, offset = ptex * HASH_PTE_SIZE_64 + HPTE64_DW1_R;
if (cpu->vhyp) {
@@ -874,11 +877,12 @@ static void ppc_hash64_set_r(PowerPCCPU *cpu, hwaddr ptex, uint64_t pte1)
/* The HW performs a non-atomic byte update */
- stb_phys(CPU(cpu)->as, base + offset, ((pte1 >> 8) & 0xff) | 0x01);
+ stb_phys(as, base + offset, ((pte1 >> 8) & 0xff) | 0x01);
}
static void ppc_hash64_set_c(PowerPCCPU *cpu, hwaddr ptex, uint64_t pte1)
{
+ AddressSpace *as = cpu_get_address_space(CPU(cpu), 0);
hwaddr base, offset = ptex * HASH_PTE_SIZE_64 + HPTE64_DW1_C;
if (cpu->vhyp) {
@@ -888,7 +892,7 @@ static void ppc_hash64_set_c(PowerPCCPU *cpu, hwaddr ptex, uint64_t pte1)
base = ppc_hash64_hpt_base(cpu);
/* The HW performs a non-atomic byte update */
- stb_phys(CPU(cpu)->as, base + offset, (pte1 & 0xff) | 0x80);
+ stb_phys(as, base + offset, (pte1 & 0xff) | 0x80);
}
static target_ulong rmls_limit(PowerPCCPU *cpu)
diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c
index 33ac3412901..c381a833ebd 100644
--- a/target/ppc/mmu-radix64.c
+++ b/target/ppc/mmu-radix64.c
@@ -431,6 +431,7 @@ static int ppc_radix64_partition_scoped_xlate(PowerPCCPU *cpu,
int mmu_idx, uint64_t lpid,
bool guest_visible)
{
+ AddressSpace *as = cpu_get_address_space(CPU(cpu), 0);
MMUAccessType access_type = orig_access_type;
int fault_cause = 0;
hwaddr pte_addr;
@@ -451,7 +452,7 @@ static int ppc_radix64_partition_scoped_xlate(PowerPCCPU *cpu,
*h_page_size = PRTBE_R_GET_RTS(pate.dw0);
/* No valid pte or access denied due to protection */
- if (ppc_radix64_walk_tree(CPU(cpu)->as, g_raddr, pate.dw0 & PRTBE_R_RPDB,
+ if (ppc_radix64_walk_tree(as, g_raddr, pate.dw0 & PRTBE_R_RPDB,
pate.dw0 & PRTBE_R_RPDS, h_raddr, h_page_size,
&pte, &fault_cause, &pte_addr) ||
ppc_radix64_check_prot(cpu, access_type, pte,
@@ -516,7 +517,7 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu,
int mmu_idx, uint64_t lpid,
bool guest_visible)
{
- CPUState *cs = CPU(cpu);
+ AddressSpace *as = cpu_get_address_space(CPU(cpu), 0);
CPUPPCState *env = &cpu->env;
uint64_t offset, size, prtb, prtbe_addr, prtbe0, base_addr, nls, index, pte;
int fault_cause = 0, h_page_size, h_prot;
@@ -550,7 +551,7 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu,
prtbe_addr = prtb + offset;
if (vhyp_flat_addressing(cpu)) {
- prtbe0 = ldq_phys(cs->as, prtbe_addr);
+ prtbe0 = ldq_phys(as, prtbe_addr);
} else {
/*
* Process table addresses are subject to partition-scoped
@@ -568,7 +569,7 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu,
if (ret) {
return ret;
}
- prtbe0 = ldq_phys(cs->as, h_raddr);
+ prtbe0 = ldq_phys(as, h_raddr);
}
/*
@@ -593,7 +594,7 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu,
/*
* Can treat process table addresses as real addresses
*/
- ret = ppc_radix64_walk_tree(cs->as, eaddr & R_EADDR_MASK, base_addr,
+ ret = ppc_radix64_walk_tree(as, eaddr & R_EADDR_MASK, base_addr,
nls, g_raddr, g_page_size, &pte,
&fault_cause, &pte_addr);
if (ret) {
@@ -630,7 +631,7 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu,
fault_cause |= DSISR_R_BADCONFIG;
ret = 1;
} else {
- ret = ppc_radix64_next_level(cs->as, eaddr & R_EADDR_MASK,
+ ret = ppc_radix64_next_level(as, eaddr & R_EADDR_MASK,
&h_raddr, &nls, g_page_size,
&pte, &fault_cause);
}
--
2.51.0
next prev parent reply other threads:[~2025-10-01 15:11 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-01 15:05 [PATCH 00/22] hw/core/cpu: Remove @CPUState::as field Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 01/22] system/qtest: Use &address_space_memory for first vCPU address space Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 02/22] disas/disas-mon: Get cpu first addr space with cpu_get_address_space() Philippe Mathieu-Daudé
2025-10-01 15:34 ` BALATON Zoltan
2025-10-01 15:05 ` [PATCH 03/22] monitor/hmp-cmds: " Philippe Mathieu-Daudé
2025-10-01 15:35 ` BALATON Zoltan
2025-10-01 16:23 ` Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 04/22] hw/core/loader: " Philippe Mathieu-Daudé
2025-10-01 15:08 ` Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 05/22] hw/ppc: " Philippe Mathieu-Daudé
2025-10-01 15:23 ` Miles Glenn
2025-10-01 15:05 ` [PATCH 06/22] hw/m86k: " Philippe Mathieu-Daudé
2025-10-18 5:52 ` Thomas Huth
2025-10-01 15:05 ` [PATCH 07/22] target/xtensa: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 08/22] target/riscv: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 09/22] semihosting: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 10/22] target/alpha: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 11/22] target/arm: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 12/22] target/hppa: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 13/22] target/i386: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 14/22] target/loongarch: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 15/22] target/m68k: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 16/22] target/microblaze: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` Philippe Mathieu-Daudé [this message]
2025-10-01 15:05 ` [PATCH 18/22] target/s390x: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 19/22] target/sparc: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 20/22] hw/core/cpu: Remove @CPUState::as field Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 21/22] exec/cpu: Declare cpu_memory_rw_debug() in 'hw/core/cpu.h' and document Philippe Mathieu-Daudé
2025-10-06 19:08 ` Philippe Mathieu-Daudé
2025-10-08 16:25 ` Zhao Liu
2025-10-01 15:05 ` [PATCH 22/22] target/sparc: Reduce inclusions of 'exec/cpu-common.h' Philippe Mathieu-Daudé
2025-10-01 15:39 ` [PATCH 00/22] hw/core/cpu: Remove @CPUState::as field BALATON Zoltan
2025-10-01 16:08 ` Peter Maydell
2025-10-01 16:35 ` Richard Henderson
2025-10-01 16:42 ` Philippe Mathieu-Daudé
2025-10-01 18:38 ` Philippe Mathieu-Daudé
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