From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org,
"Richard Henderson" <richard.henderson@linaro.org>,
qemu-riscv@nongnu.org, "Peter Maydell" <peter.maydell@linaro.org>,
qemu-ppc@nongnu.org, "Paolo Bonzini" <pbonzini@redhat.com>,
"Pierrick Bouvier" <pierrick.bouvier@linaro.org>,
"Peter Xu" <peterx@redhat.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Mark Cave-Ayland" <mark.cave-ayland@ilande.co.uk>,
"Artyom Tarasenko" <atar4qemu@gmail.com>
Subject: [PATCH 19/22] target/sparc: Get cpu first addr space with cpu_get_address_space()
Date: Wed, 1 Oct 2025 17:05:24 +0200 [thread overview]
Message-ID: <20251001150529.14122-20-philmd@linaro.org> (raw)
In-Reply-To: <20251001150529.14122-1-philmd@linaro.org>
In order to remove the convenient CPUState::as field, access
the vcpu first address space using the cpu_get_address_space()
helper.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/sparc/ldst_helper.c | 22 ++++++++++++----------
target/sparc/mmu_helper.c | 21 ++++++++++++---------
2 files changed, 24 insertions(+), 19 deletions(-)
diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c
index 2c63eb9e036..35d1f63fd2a 100644
--- a/target/sparc/ldst_helper.c
+++ b/target/sparc/ldst_helper.c
@@ -700,23 +700,24 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr,
{
MemTxResult result;
hwaddr access_addr = (hwaddr)addr | ((hwaddr)(asi & 0xf) << 32);
+ AddressSpace *as = cpu_get_address_space(cs, 0);
switch (size) {
case 1:
- ret = address_space_ldub(cs->as, access_addr,
+ ret = address_space_ldub(as, access_addr,
MEMTXATTRS_UNSPECIFIED, &result);
break;
case 2:
- ret = address_space_lduw(cs->as, access_addr,
+ ret = address_space_lduw(as, access_addr,
MEMTXATTRS_UNSPECIFIED, &result);
break;
default:
case 4:
- ret = address_space_ldl(cs->as, access_addr,
+ ret = address_space_ldl(as, access_addr,
MEMTXATTRS_UNSPECIFIED, &result);
break;
case 8:
- ret = address_space_ldq(cs->as, access_addr,
+ ret = address_space_ldq(as, access_addr,
MEMTXATTRS_UNSPECIFIED, &result);
break;
}
@@ -809,6 +810,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val,
{
int size = 1 << (memop & MO_SIZE);
CPUState *cs = env_cpu(env);
+ AddressSpace *as = cpu_get_address_space(cs, 0);
do_check_align(env, addr, size - 1, GETPC());
switch (asi) {
@@ -878,7 +880,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val,
MemTxResult result;
hwaddr access_addr = (env->mxccregs[0] & 0xffffffffULL) + 8 * i;
- env->mxccdata[i] = address_space_ldq(cs->as,
+ env->mxccdata[i] = address_space_ldq(as,
access_addr,
MEMTXATTRS_UNSPECIFIED,
&result);
@@ -906,7 +908,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val,
MemTxResult result;
hwaddr access_addr = (env->mxccregs[1] & 0xffffffffULL) + 8 * i;
- address_space_stq(cs->as, access_addr, env->mxccdata[i],
+ address_space_stq(as, access_addr, env->mxccdata[i],
MEMTXATTRS_UNSPECIFIED, &result);
if (result != MEMTX_OK) {
@@ -1068,20 +1070,20 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val,
switch (size) {
case 1:
- address_space_stb(cs->as, access_addr, val,
+ address_space_stb(as, access_addr, val,
MEMTXATTRS_UNSPECIFIED, &result);
break;
case 2:
- address_space_stw(cs->as, access_addr, val,
+ address_space_stw(as, access_addr, val,
MEMTXATTRS_UNSPECIFIED, &result);
break;
case 4:
default:
- address_space_stl(cs->as, access_addr, val,
+ address_space_stl(as, access_addr, val,
MEMTXATTRS_UNSPECIFIED, &result);
break;
case 8:
- address_space_stq(cs->as, access_addr, val,
+ address_space_stq(as, access_addr, val,
MEMTXATTRS_UNSPECIFIED, &result);
break;
}
diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c
index 217580a4d8c..1e13ef3da40 100644
--- a/target/sparc/mmu_helper.c
+++ b/target/sparc/mmu_helper.c
@@ -80,6 +80,7 @@ static int get_physical_address(CPUSPARCState *env, CPUTLBEntryFull *full,
unsigned long page_offset;
CPUState *cs = env_cpu(env);
MemTxResult result;
+ AddressSpace *as;
is_user = mmu_idx == MMU_USER_IDX;
@@ -96,13 +97,14 @@ static int get_physical_address(CPUSPARCState *env, CPUTLBEntryFull *full,
return 0;
}
+ as = cpu_get_address_space(cs, 0);
*access_index = ((rw & 1) << 2) | (rw & 2) | (is_user ? 0 : 1);
full->phys_addr = 0xffffffffffff0000ULL;
/* SPARC reference MMU table walk: Context table->L1->L2->PTE */
/* Context base + context number */
pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
- pde = address_space_ldl(cs->as, pde_ptr, MEMTXATTRS_UNSPECIFIED, &result);
+ pde = address_space_ldl(as, pde_ptr, MEMTXATTRS_UNSPECIFIED, &result);
if (result != MEMTX_OK) {
return 4 << 2; /* Translation fault, L = 0 */
}
@@ -117,7 +119,7 @@ static int get_physical_address(CPUSPARCState *env, CPUTLBEntryFull *full,
return 4 << 2;
case 1: /* L0 PDE */
pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
- pde = address_space_ldl(cs->as, pde_ptr,
+ pde = address_space_ldl(as, pde_ptr,
MEMTXATTRS_UNSPECIFIED, &result);
if (result != MEMTX_OK) {
return (1 << 8) | (4 << 2); /* Translation fault, L = 1 */
@@ -131,7 +133,7 @@ static int get_physical_address(CPUSPARCState *env, CPUTLBEntryFull *full,
return (1 << 8) | (4 << 2);
case 1: /* L1 PDE */
pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
- pde = address_space_ldl(cs->as, pde_ptr,
+ pde = address_space_ldl(as, pde_ptr,
MEMTXATTRS_UNSPECIFIED, &result);
if (result != MEMTX_OK) {
return (2 << 8) | (4 << 2); /* Translation fault, L = 2 */
@@ -145,7 +147,7 @@ static int get_physical_address(CPUSPARCState *env, CPUTLBEntryFull *full,
return (2 << 8) | (4 << 2);
case 1: /* L2 PDE */
pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
- pde = address_space_ldl(cs->as, pde_ptr,
+ pde = address_space_ldl(as, pde_ptr,
MEMTXATTRS_UNSPECIFIED, &result);
if (result != MEMTX_OK) {
return (3 << 8) | (4 << 2); /* Translation fault, L = 3 */
@@ -189,7 +191,7 @@ static int get_physical_address(CPUSPARCState *env, CPUTLBEntryFull *full,
if (is_dirty) {
pde |= PG_MODIFIED_MASK;
}
- stl_phys_notdirty(cs->as, pde_ptr, pde);
+ stl_phys_notdirty(as, pde_ptr, pde);
}
/* the page can be put in the TLB */
@@ -264,6 +266,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev)
{
CPUState *cs = env_cpu(env);
+ AddressSpace *as = cpu_get_address_space(cs, 0);
hwaddr pde_ptr;
uint32_t pde;
MemTxResult result;
@@ -276,7 +279,7 @@ target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev)
/* Context base + context number */
pde_ptr = (hwaddr)(env->mmuregs[1] << 4) +
(env->mmuregs[2] << 2);
- pde = address_space_ldl(cs->as, pde_ptr, MEMTXATTRS_UNSPECIFIED, &result);
+ pde = address_space_ldl(as, pde_ptr, MEMTXATTRS_UNSPECIFIED, &result);
if (result != MEMTX_OK) {
return 0;
}
@@ -292,7 +295,7 @@ target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev)
return pde;
}
pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
- pde = address_space_ldl(cs->as, pde_ptr,
+ pde = address_space_ldl(as, pde_ptr,
MEMTXATTRS_UNSPECIFIED, &result);
if (result != MEMTX_OK) {
return 0;
@@ -310,7 +313,7 @@ target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev)
return pde;
}
pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
- pde = address_space_ldl(cs->as, pde_ptr,
+ pde = address_space_ldl(as, pde_ptr,
MEMTXATTRS_UNSPECIFIED, &result);
if (result != MEMTX_OK) {
return 0;
@@ -328,7 +331,7 @@ target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev)
return pde;
}
pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
- pde = address_space_ldl(cs->as, pde_ptr,
+ pde = address_space_ldl(as, pde_ptr,
MEMTXATTRS_UNSPECIFIED, &result);
if (result != MEMTX_OK) {
return 0;
--
2.51.0
next prev parent reply other threads:[~2025-10-01 15:14 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-01 15:05 [PATCH 00/22] hw/core/cpu: Remove @CPUState::as field Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 01/22] system/qtest: Use &address_space_memory for first vCPU address space Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 02/22] disas/disas-mon: Get cpu first addr space with cpu_get_address_space() Philippe Mathieu-Daudé
2025-10-01 15:34 ` BALATON Zoltan
2025-10-01 15:05 ` [PATCH 03/22] monitor/hmp-cmds: " Philippe Mathieu-Daudé
2025-10-01 15:35 ` BALATON Zoltan
2025-10-01 16:23 ` Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 04/22] hw/core/loader: " Philippe Mathieu-Daudé
2025-10-01 15:08 ` Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 05/22] hw/ppc: " Philippe Mathieu-Daudé
2025-10-01 15:23 ` Miles Glenn
2025-10-01 15:05 ` [PATCH 06/22] hw/m86k: " Philippe Mathieu-Daudé
2025-10-18 5:52 ` Thomas Huth
2025-10-01 15:05 ` [PATCH 07/22] target/xtensa: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 08/22] target/riscv: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 09/22] semihosting: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 10/22] target/alpha: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 11/22] target/arm: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 12/22] target/hppa: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 13/22] target/i386: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 14/22] target/loongarch: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 15/22] target/m68k: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 16/22] target/microblaze: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 17/22] target/ppc: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 18/22] target/s390x: " Philippe Mathieu-Daudé
2025-10-01 15:05 ` Philippe Mathieu-Daudé [this message]
2025-10-01 15:05 ` [PATCH 20/22] hw/core/cpu: Remove @CPUState::as field Philippe Mathieu-Daudé
2025-10-01 15:05 ` [PATCH 21/22] exec/cpu: Declare cpu_memory_rw_debug() in 'hw/core/cpu.h' and document Philippe Mathieu-Daudé
2025-10-06 19:08 ` Philippe Mathieu-Daudé
2025-10-08 16:25 ` Zhao Liu
2025-10-01 15:05 ` [PATCH 22/22] target/sparc: Reduce inclusions of 'exec/cpu-common.h' Philippe Mathieu-Daudé
2025-10-01 15:39 ` [PATCH 00/22] hw/core/cpu: Remove @CPUState::as field BALATON Zoltan
2025-10-01 16:08 ` Peter Maydell
2025-10-01 16:35 ` Richard Henderson
2025-10-01 16:42 ` Philippe Mathieu-Daudé
2025-10-01 18:38 ` Philippe Mathieu-Daudé
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