From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: berrange@redhat.com, magnus.kulke@linux.microsoft.com,
wei.liu@kernel.org
Subject: [PATCH v5 00/27] Implementing a MSHV (Microsoft Hypervisor) accelerator
Date: Thu, 2 Oct 2025 19:15:09 +0200 [thread overview]
Message-ID: <20251002171536.1460049-1-pbonzini@redhat.com> (raw)
Hi Magnus,
this is your series with a lot of fixes to make it pass CI. It's very
much untested but the changes are mostly concentrated in the headers,
where you obviously didn't have great coverage of target systems. :)
So I don't expect any huge issues, but anyway here it is for your testing.
The changes are:
- nits from Daniel's review
- add check for availability with --enable-whpx
- do not use __uN types outside linux-headers/
- add stubs in accel/stubs/mshv-stub.c
- do not include <linux/mshv.h> on files with Linux stubs
- split mshv.h/mshv_int.h to avoid conflicts with other accelerators
(esp. in the definition of AccelCPUState)
- change first argument of mshv_request_interrupt to MshvState*
(though it could go away altogether)
- fix double free of cpu->accel [Daniel]
- adjust for rename of qemu_wait_io_event()
- use MAX_CONST instead of MAX_SIZE
- adjust trace-events to use PRIx64
Thanks,
Paolo
Magnus Kulke (26):
accel: Add Meson and config support for MSHV accelerator
target/i386/emulate: Allow instruction decoding from stream
target/i386/mshv: Add x86 decoder/emu implementation
hw/intc: Generalize APIC helper names from kvm_* to accel_*
include/hw/hyperv: Add MSHV ABI header definitions
linux-headers/linux: Add mshv.h headers
accel/mshv: Add accelerator skeleton
accel/mshv: Register memory region listeners
accel/mshv: Initialize VM partition
accel/mshv: Add vCPU creation and execution loop
accel/mshv: Add vCPU signal handling
target/i386/mshv: Add CPU create and remove logic
target/i386/mshv: Implement mshv_store_regs()
target/i386/mshv: Implement mshv_get_standard_regs()
target/i386/mshv: Implement mshv_get_special_regs()
target/i386/mshv: Implement mshv_arch_put_registers()
target/i386/mshv: Set local interrupt controller state
target/i386/mshv: Register CPUID entries with MSHV
target/i386/mshv: Register MSRs with MSHV
target/i386/mshv: Integrate x86 instruction decoder/emulator
target/i386/mshv: Write MSRs to the hypervisor
target/i386/mshv: Implement mshv_vcpu_run()
accel/mshv: Handle overlapping mem mappings
target/i386/mshv: Use preallocated page for hvcall
docs: Add mshv to documentation
MAINTAINERS: Add maintainers for mshv accelerator
Praveen K Paladugu (1):
qapi/accel: Allow to query mshv capabilities
MAINTAINERS | 15 +
docs/about/build-platforms.rst | 2 +-
docs/devel/codebase.rst | 2 +-
docs/glossary.rst | 7 +-
docs/system/introduction.rst | 3 +
meson.build | 14 +
qapi/accelerator.json | 29 +
accel/mshv/trace.h | 14 +
include/hw/hyperv/hvgdk.h | 20 +
include/hw/hyperv/hvgdk_mini.h | 817 ++++++++++++++
include/hw/hyperv/hvhdk.h | 249 +++++
include/hw/hyperv/hvhdk_mini.h | 102 ++
include/monitor/hmp.h | 1 +
include/system/accel-irq.h | 37 +
include/system/hw_accel.h | 1 +
include/system/mshv.h | 64 ++
include/system/mshv_int.h | 155 +++
linux-headers/linux/mshv.h | 291 +++++
target/i386/cpu.h | 4 +-
target/i386/emulate/x86_decode.h | 9 +
target/i386/emulate/x86_emu.h | 2 +
accel/accel-irq.c | 106 ++
accel/mshv/irq.c | 399 +++++++
accel/mshv/mem.c | 563 ++++++++++
accel/mshv/mshv-all.c | 727 ++++++++++++
accel/mshv/msr.c | 375 +++++++
accel/stubs/mshv-stub.c | 44 +
hw/core/machine-hmp-cmds.c | 15 +
hw/core/machine-qmp-cmds.c | 14 +
hw/intc/apic.c | 8 +
hw/intc/ioapic.c | 20 +-
hw/virtio/virtio-pci.c | 21 +-
target/i386/emulate/x86_decode.c | 27 +-
target/i386/emulate/x86_emu.c | 3 +-
target/i386/mshv/mshv-cpu.c | 1763 ++++++++++++++++++++++++++++++
target/i386/mshv/x86.c | 297 +++++
accel/Kconfig | 3 +
accel/meson.build | 3 +-
accel/mshv/meson.build | 9 +
accel/mshv/trace-events | 33 +
accel/stubs/meson.build | 1 +
hmp-commands-info.hx | 13 +
meson_options.txt | 2 +
qemu-options.hx | 16 +-
scripts/meson-buildoptions.sh | 3 +
scripts/update-linux-headers.sh | 2 +-
target/i386/emulate/meson.build | 7 +-
target/i386/meson.build | 2 +
target/i386/mshv/meson.build | 8 +
49 files changed, 6281 insertions(+), 41 deletions(-)
create mode 100644 accel/mshv/trace.h
create mode 100644 include/hw/hyperv/hvgdk.h
create mode 100644 include/hw/hyperv/hvgdk_mini.h
create mode 100644 include/hw/hyperv/hvhdk.h
create mode 100644 include/hw/hyperv/hvhdk_mini.h
create mode 100644 include/system/accel-irq.h
create mode 100644 include/system/mshv.h
create mode 100644 include/system/mshv_int.h
create mode 100644 linux-headers/linux/mshv.h
create mode 100644 accel/accel-irq.c
create mode 100644 accel/mshv/irq.c
create mode 100644 accel/mshv/mem.c
create mode 100644 accel/mshv/mshv-all.c
create mode 100644 accel/mshv/msr.c
create mode 100644 accel/stubs/mshv-stub.c
create mode 100644 target/i386/mshv/mshv-cpu.c
create mode 100644 target/i386/mshv/x86.c
create mode 100644 accel/mshv/meson.build
create mode 100644 accel/mshv/trace-events
create mode 100644 target/i386/mshv/meson.build
--
2.51.0
next reply other threads:[~2025-10-02 17:18 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-02 17:15 Paolo Bonzini [this message]
2025-10-02 17:15 ` [PATCH 01/27] accel: Add Meson and config support for MSHV accelerator Paolo Bonzini
2025-10-08 17:15 ` Magnus Kulke
2025-10-02 17:15 ` [PATCH 02/27] target/i386/emulate: Allow instruction decoding from stream Paolo Bonzini
2025-10-02 17:15 ` [PATCH 03/27] target/i386/mshv: Add x86 decoder/emu implementation Paolo Bonzini
2025-10-02 17:15 ` [PATCH 04/27] hw/intc: Generalize APIC helper names from kvm_* to accel_* Paolo Bonzini
2025-10-02 17:15 ` [PATCH 05/27] include/hw/hyperv: Add MSHV ABI header definitions Paolo Bonzini
2025-10-02 17:15 ` [PATCH 06/27] linux-headers/linux: Add mshv.h headers Paolo Bonzini
2025-10-02 17:15 ` [PATCH 07/27] accel/mshv: Add accelerator skeleton Paolo Bonzini
2025-10-02 17:15 ` [PATCH 08/27] accel/mshv: Register memory region listeners Paolo Bonzini
2025-10-02 17:15 ` [PATCH 09/27] accel/mshv: Initialize VM partition Paolo Bonzini
2025-10-02 17:15 ` [PATCH 10/27] accel/mshv: Add vCPU creation and execution loop Paolo Bonzini
2025-10-02 17:15 ` [PATCH 11/27] accel/mshv: Add vCPU signal handling Paolo Bonzini
2025-10-02 17:15 ` [PATCH 12/27] target/i386/mshv: Add CPU create and remove logic Paolo Bonzini
2025-10-02 17:15 ` [PATCH 13/27] target/i386/mshv: Implement mshv_store_regs() Paolo Bonzini
2025-10-02 17:15 ` [PATCH 14/27] target/i386/mshv: Implement mshv_get_standard_regs() Paolo Bonzini
2025-10-02 17:15 ` [PATCH 15/27] target/i386/mshv: Implement mshv_get_special_regs() Paolo Bonzini
2025-10-02 17:15 ` [PATCH 16/27] target/i386/mshv: Implement mshv_arch_put_registers() Paolo Bonzini
2025-10-02 17:15 ` [PATCH 17/27] target/i386/mshv: Set local interrupt controller state Paolo Bonzini
2025-10-02 17:15 ` [PATCH 18/27] target/i386/mshv: Register CPUID entries with MSHV Paolo Bonzini
2025-10-02 17:15 ` [PATCH 19/27] target/i386/mshv: Register MSRs " Paolo Bonzini
2025-10-02 17:15 ` [PATCH 20/27] target/i386/mshv: Integrate x86 instruction decoder/emulator Paolo Bonzini
2025-10-02 17:15 ` [PATCH 21/27] target/i386/mshv: Write MSRs to the hypervisor Paolo Bonzini
2025-10-02 17:15 ` [PATCH 22/27] target/i386/mshv: Implement mshv_vcpu_run() Paolo Bonzini
2025-10-02 17:15 ` [PATCH 23/27] accel/mshv: Handle overlapping mem mappings Paolo Bonzini
2025-10-02 17:15 ` [PATCH 24/27] qapi/accel: Allow to query mshv capabilities Paolo Bonzini
2025-10-02 17:15 ` [PATCH 25/27] target/i386/mshv: Use preallocated page for hvcall Paolo Bonzini
2025-10-02 17:15 ` [PATCH 26/27] docs: Add mshv to documentation Paolo Bonzini
2025-10-08 19:13 ` Wei Liu
2025-10-02 17:15 ` [PATCH 27/27] MAINTAINERS: Add maintainers for mshv accelerator Paolo Bonzini
2025-10-08 17:13 ` [PATCH v5 00/27] Implementing a MSHV (Microsoft Hypervisor) accelerator Magnus Kulke
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