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Fri, 03 Oct 2025 08:02:51 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGLD9+JbG9S/yKzQRS/YEGM+6BAJi98kzIZZLi8drv4IZ2r9FHhzIkjd36jpkDM0JLRzk5Omg== X-Received: by 2002:a05:600c:4f08:b0:46d:d949:daba with SMTP id 5b1f17b1804b1-46e7608b683mr10558715e9.4.1759503769147; Fri, 03 Oct 2025 08:02:49 -0700 (PDT) Received: from fedora ([85.93.96.130]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-46e723431d0sm39581195e9.5.2025.10.03.08.02.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Oct 2025 08:02:48 -0700 (PDT) Date: Fri, 3 Oct 2025 17:02:45 +0200 From: Igor Mammedov To: salil.mehta@opnsrc.net Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, mst@redhat.com, salil.mehta@huawei.com, maz@kernel.org, jean-philippe@linaro.org, jonathan.cameron@huawei.com, lpieralisi@kernel.org, peter.maydell@linaro.org, richard.henderson@linaro.org, armbru@redhat.com, andrew.jones@linux.dev, david@redhat.com, philmd@linaro.org, eric.auger@redhat.com, will@kernel.org, ardb@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, gshan@redhat.com, rafael@kernel.org, borntraeger@linux.ibm.com, alex.bennee@linaro.org, gustavo.romero@linaro.org, npiggin@gmail.com, harshpb@linux.ibm.com, linux@armlinux.org.uk, darren@os.amperecomputing.com, ilkka@os.amperecomputing.com, vishnu@os.amperecomputing.com, gankulkarni@os.amperecomputing.com, karl.heubaum@oracle.com, miguel.luis@oracle.com, zhukeqian1@huawei.com, wangxiongfeng2@huawei.com, wangyanan55@huawei.com, wangzhou1@hisilicon.com, linuxarm@huawei.com, jiakernel2@gmail.com, maobibo@loongson.cn, lixianglai@loongson.cn, shahuang@redhat.com, zhao1.liu@intel.com Subject: Re: [PATCH RFC V6 10/24] arm/virt: Init PMU at host for all present vCPUs Message-ID: <20251003170245.75ad2405@fedora> In-Reply-To: <20251001010127.3092631-11-salil.mehta@opnsrc.net> References: <20251001010127.3092631-1-salil.mehta@opnsrc.net> <20251001010127.3092631-11-salil.mehta@opnsrc.net> X-Mailer: Claws Mail 4.3.1 (GTK 3.24.49; x86_64-redhat-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=170.10.133.124; envelope-from=imammedo@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.467, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, 1 Oct 2025 01:01:13 +0000 salil.mehta@opnsrc.net wrote: > From: Salil Mehta >=20 ... > diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h > index 5eaf41a566..2ee202a8a5 100644 > --- a/include/hw/core/cpu.h > +++ b/include/hw/core/cpu.h > @@ -602,6 +602,63 @@ extern CPUTailQ cpus_queue; > #define CPU_FOREACH_SAFE(cpu, next_cpu) \ > QTAILQ_FOREACH_SAFE_RCU(cpu, &cpus_queue, node, next_cpu) > =20 > + > +/** > + * CPU_FOREACH_POSSIBLE(cpu_, archid_list_) > + * > + * Iterate over all entries in a CPUArchIdList, assigning each entry=E2= =80=99s > + * CPUState* to @cpu_. This hides the loop index and reads like a normal > + * C for-loop. > + * > + * A CPUArchIdList represents the set of *possible* CPUs for a machine. > + * Each entry contains: > + * - @cpu: CPUState pointer, or NULL if not realized yet > + * - @arch_id: architecture-specific identifier (e.g. MPIDR) > + * - @vcpus_count: number of vCPUs represented (usually 1) > + * > + * The list models *possible* CPUs: it includes (a) currently plugged vC= PUs > + * made available through hotplug, (b) present (and perhaps visible to O= SPM) > + * but kept ACPI-disabled vCPUs, and (c) reserved slots for CPUs that ma= y be > + * created in the future. This supports co-existence of hotpluggable and > + * admin-disabled vCPUs if architectures permit. > + * > + * Example: > + * > + * CPUArchIdList *alist =3D machine_possible_cpus(ms); > + * CPUState *cpu; > + * > + * CPU_FOREACH_POSSIBLE(cpu, alist) { > + * if (!cpu) { > + * continue; // reserved slot for hotplug case > + * } > + * > + * < Do Something > > + * } > + * > + * Expanded equivalent: > + * > + * for (int __cpu_idx =3D 0; alist && __cpu_idx < alist->len; __cpu_id= x++) { > + * if ((cpu =3D alist->cpus[__cpu_idx].cpu, 1)) { > + * if (!cpu) { > + * continue; > + * } > + * > + * < Do Something > > + * } > + * } > + * > + * Notes: > + * - Callers must check @cpu for NULL when filtering unplugged CPUs. > + * - Mirrors the style of CPU_FOREACH(), but iterates all *possible* C= PUs > + * (plugged, ACPI-disabled, and reserved slots) rather than only pre= sent > + * and enabled vCPUs. > + */ > +#define CPU_FOREACH_POSSIBLE(cpu_, archid_list_) \ > + for (int __cpu_idx =3D 0; \ > + (archid_list_) && __cpu_idx < (archid_list_)->len; \ > + __cpu_idx++) \ > + if (((cpu_) =3D (archid_list_)->cpus[__cpu_idx].cpu, 1)) > + > extern __thread CPUState *current_cpu; make it a separate patch and refactor existing loops to use it. > =20 > /**