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([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-28e8d110d86sm55327115ad.6.2025.10.03.10.08.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Oct 2025 10:08:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v6 00/73] target/arm: Implement FEAT_GCS Date: Fri, 3 Oct 2025 10:06:47 -0700 Message-ID: <20251003170800.997167-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Changes from v5: - Master now includes the accel/tcg/ patches. - Updated TF-A/TF-RMM tests for FEAT_S1PIE and FEAT_GCS. Patches lacking review: 34-target-arm-Make-helper_exception_return-system-on.patch 35-target-arm-Export-cpsr_-read_for-write_from-_spsr.patch 38-target-arm-Add-arm_hcr_el2_nvx_eff.patch 39-target-arm-Use-arm_hcr_el2_nvx_eff-in-access_nv1.patch 40-target-arm-Split-out-access_nv1_with_nvx.patch 48-target-arm-Implement-GCSPUSHM.patch r~ Pierrick Bouvier (1): tests/functional: update tests using TF-A/TF-RMM to support FEAT_GCS Richard Henderson (72): target/arm: Add isar feature test for FEAT_S1PIE, FEAT_S2PIE target/arm: Enable TCR2_ELx.PIE target/arm: Implement PIR_ELx, PIRE0_ELx, S2PIR_EL2 registers target/arm: Force HPD for stage2 translations target/arm: Cache NV1 early in get_phys_addr_lpae target/arm: Populate PIE in aa64_va_parameters target/arm: Implement get_S1prot_indirect target/arm: Implement get_S2prot_indirect target/arm: Expand CPUARMState.exception.syndrome to 64 bits target/arm: Expand syndrome parameter to raise_exception* target/arm: Implement dirtybit check for PIE target/arm: Enable FEAT_S1PIE and FEAT_S2PIE on -cpu max include/exec/memopidx: Adjust for 32 mmu indexes include/hw/core/cpu: Widen MMUIdxMap target/arm: Split out mmuidx.h from cpu.h target/arm: Convert arm_mmu_idx_to_el from switch to table target/arm: Remove unused env argument from regime_el target/arm: Convert regime_el from switch to table target/arm: Convert regime_has_2_ranges from switch to table target/arm: Remove unused env argument from regime_is_pan target/arm: Convert regime_is_pan from switch to table target/arm: Remove unused env argument from regime_is_user target/arm: Convert regime_is_user from switch to table target/arm: Convert arm_mmu_idx_is_stage1_of_2 from switch to table target/arm: Convert regime_is_stage2 to table target/arm: Introduce mmu indexes for GCS target/arm: Introduce regime_to_gcs target/arm: Support page protections for GCS mmu indexes target/arm: Implement gcs bit for data abort target/arm: Add GCS cpregs target/arm: Add GCS enable and trap levels to DisasContext target/arm: Implement FEAT_CHK target/arm: Make helper_exception_return system-only target/arm: Export cpsr_{read_for,write_from}_spsr_elx target/arm: Expand pstate to 64 bits target/arm: Add syndrome data for EC_GCS target/arm: Add arm_hcr_el2_nvx_eff target/arm: Use arm_hcr_el2_nvx_eff in access_nv1 target/arm: Split out access_nv1_with_nvx target/arm: Implement EXLOCKException for ELR_ELx and SPSR_ELx target/arm: Split {full,core}_a64_user_mem_index target/arm: Introduce delay_exception{_el} target/arm: Emit HSTR trap exception out of line target/arm: Emit v7m LTPSIZE exception out of line target/arm: Implement GCSSTR, GCSSTTR target/arm: Implement GCSB target/arm: Implement GCSPUSHM target/arm: Implement GCSPOPM target/arm: Implement GCSPUSHX target/arm: Implement GCSPOPX target/arm: Implement GCSPOPCX target/arm: Implement GCSSS1 target/arm: Implement GCSSS2 target/arm: Add gcs record for BL target/arm: Add gcs record for BLR target/arm: Add gcs record for BLR with PAuth target/arm: Load gcs record for RET target/arm: Load gcs record for RET with PAuth target/arm: Copy EXLOCKEn to EXLOCK on exception to the same EL target/arm: Implement EXLOCK check during exception return target/arm: Enable FEAT_GCS with -cpu max linux-user/aarch64: Implement prctls for GCS linux-user/aarch64: Allocate new gcs stack on clone linux-user/aarch64: Release gcs stack on thread exit linux-user/aarch64: Implement map_shadow_stack syscall target/arm: Enable GCSPR_EL0 for read in user-mode linux-user/aarch64: Inject SIGSEGV for GCS faults linux-user/aarch64: Generate GCS signal records linux-user/aarch64: Enable GCS in HWCAP tests/tcg/aarch64: Add gcsstr tests/tcg/aarch64: Add gcspushm tests/tcg/aarch64: Add gcsss include/exec/memopidx.h | 9 +- include/hw/core/cpu.h | 7 +- linux-user/aarch64/gcs-internal.h | 38 ++ linux-user/aarch64/target_prctl.h | 96 ++++ linux-user/aarch64/target_signal.h | 1 + linux-user/qemu.h | 5 + target/arm/cpregs.h | 22 + target/arm/cpu-features.h | 15 + target/arm/cpu.h | 243 ++-------- target/arm/internals.h | 148 +----- target/arm/mmuidx-internal.h | 113 +++++ target/arm/mmuidx.h | 241 ++++++++++ target/arm/syndrome.h | 35 ++ target/arm/tcg/helper-a64.h | 5 +- target/arm/tcg/translate.h | 46 +- tests/tcg/aarch64/gcs.h | 80 ++++ accel/tcg/cputlb.c | 3 - linux-user/aarch64/cpu_loop.c | 5 + linux-user/aarch64/elfload.c | 1 + linux-user/aarch64/signal.c | 138 +++++- linux-user/syscall.c | 114 +++++ target/arm/cpregs-gcs.c | 156 +++++++ target/arm/cpu.c | 17 +- target/arm/gdbstub64.c | 2 + target/arm/helper.c | 283 ++++++++--- target/arm/machine.c | 113 ++++- target/arm/mmuidx.c | 66 +++ target/arm/ptw.c | 373 +++++++++++---- target/arm/tcg-stubs.c | 2 +- target/arm/tcg/cpu64.c | 3 + target/arm/tcg/helper-a64.c | 35 +- target/arm/tcg/hflags.c | 38 ++ target/arm/tcg/mte_helper.c | 2 +- target/arm/tcg/op_helper.c | 11 +- target/arm/tcg/tlb-insns.c | 47 +- target/arm/tcg/tlb_helper.c | 18 +- target/arm/tcg/translate-a64.c | 438 ++++++++++++++++-- target/arm/tcg/translate.c | 78 +++- tests/tcg/aarch64/gcspushm.c | 71 +++ tests/tcg/aarch64/gcsss.c | 74 +++ tests/tcg/aarch64/gcsstr.c | 48 ++ docs/system/arm/emulation.rst | 4 + target/arm/meson.build | 9 +- target/arm/tcg/a64.decode | 5 + .../aarch64/test_device_passthrough.py | 4 +- tests/functional/aarch64/test_rme_sbsaref.py | 4 +- tests/functional/aarch64/test_rme_virt.py | 4 +- tests/tcg/aarch64/Makefile.target | 5 + 48 files changed, 2666 insertions(+), 609 deletions(-) create mode 100644 linux-user/aarch64/gcs-internal.h create mode 100644 target/arm/mmuidx-internal.h create mode 100644 target/arm/mmuidx.h create mode 100644 tests/tcg/aarch64/gcs.h create mode 100644 target/arm/cpregs-gcs.c create mode 100644 target/arm/mmuidx.c create mode 100644 tests/tcg/aarch64/gcspushm.c create mode 100644 tests/tcg/aarch64/gcsss.c create mode 100644 tests/tcg/aarch64/gcsstr.c -- 2.43.0