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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4255d8f0846sm11157936f8f.45.2025.10.04.00.13.36 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 04 Oct 2025 00:13:37 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 06/41] system/memory: Split address_space_write_rom_internal Date: Sat, 4 Oct 2025 09:12:32 +0200 Message-ID: <20251004071307.37521-7-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251004071307.37521-1-philmd@linaro.org> References: <20251004071307.37521-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Richard Henderson In 2dbaf58bbe7 we conditionally skipped the increment of buf because ubsan warns incrementing NULL, and buf is always NULL for FLUSH_CACHE. However, the existence of the test for NULL caused Coverity to warn that the memcpy in the WRITE_DATA case lacked a test for NULL. Duplicate address_space_write_rom_internal into the two callers, dropping enum write_rom_type, and simplify. This eliminates buf in the flush case, and eliminates the conditional increment of buf in the write case. Coverity: CID 1621220 Fixes: 2dbaf58bbe7 ("system/physmem: Silence warning from ubsan") Signed-off-by: Richard Henderson Reviewed-by: Thomas Huth Message-ID: <20250922192940.2908002-1-richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé --- system/physmem.c | 90 ++++++++++++++++++++---------------------------- 1 file changed, 37 insertions(+), 53 deletions(-) diff --git a/system/physmem.c b/system/physmem.c index 1a74e48157b..225ab817883 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -3188,63 +3188,33 @@ void cpu_physical_memory_rw(hwaddr addr, void *buf, buf, len, is_write); } -enum write_rom_type { - WRITE_DATA, - FLUSH_CACHE, -}; - -static inline MemTxResult address_space_write_rom_internal(AddressSpace *as, - hwaddr addr, - MemTxAttrs attrs, - const void *ptr, - hwaddr len, - enum write_rom_type type) -{ - hwaddr l; - uint8_t *ram_ptr; - hwaddr addr1; - MemoryRegion *mr; - const uint8_t *buf = ptr; - - RCU_READ_LOCK_GUARD(); - while (len > 0) { - l = len; - mr = address_space_translate(as, addr, &addr1, &l, true, attrs); - - if (!memory_region_supports_direct_access(mr)) { - l = memory_access_size(mr, l, addr1); - } else { - /* ROM/RAM case */ - ram_ptr = qemu_map_ram_ptr(mr->ram_block, addr1); - switch (type) { - case WRITE_DATA: - memcpy(ram_ptr, buf, l); - invalidate_and_set_dirty(mr, addr1, l); - break; - case FLUSH_CACHE: - flush_idcache_range((uintptr_t)ram_ptr, (uintptr_t)ram_ptr, l); - break; - } - } - len -= l; - addr += l; - if (buf) { - buf += l; - } - } - return MEMTX_OK; -} - /* used for ROM loading : can write in RAM and ROM */ MemTxResult address_space_write_rom(AddressSpace *as, hwaddr addr, MemTxAttrs attrs, const void *buf, hwaddr len) { - return address_space_write_rom_internal(as, addr, attrs, - buf, len, WRITE_DATA); + RCU_READ_LOCK_GUARD(); + while (len > 0) { + hwaddr addr1, l = len; + MemoryRegion *mr = address_space_translate(as, addr, &addr1, &l, + true, attrs); + + if (!memory_region_supports_direct_access(mr)) { + l = memory_access_size(mr, l, addr1); + } else { + /* ROM/RAM case */ + void *ram_ptr = qemu_map_ram_ptr(mr->ram_block, addr1); + memcpy(ram_ptr, buf, l); + invalidate_and_set_dirty(mr, addr1, l); + } + len -= l; + addr += l; + buf += l; + } + return MEMTX_OK; } -void cpu_flush_icache_range(hwaddr start, hwaddr len) +void cpu_flush_icache_range(hwaddr addr, hwaddr len) { /* * This function should do the same thing as an icache flush that was @@ -3256,9 +3226,23 @@ void cpu_flush_icache_range(hwaddr start, hwaddr len) return; } - address_space_write_rom_internal(&address_space_memory, - start, MEMTXATTRS_UNSPECIFIED, - NULL, len, FLUSH_CACHE); + RCU_READ_LOCK_GUARD(); + while (len > 0) { + hwaddr addr1, l = len; + MemoryRegion *mr = address_space_translate(&address_space_memory, + addr, &addr1, &l, true, + MEMTXATTRS_UNSPECIFIED); + + if (!memory_region_supports_direct_access(mr)) { + l = memory_access_size(mr, l, addr1); + } else { + /* ROM/RAM case */ + void *ram_ptr = qemu_map_ram_ptr(mr->ram_block, addr1); + flush_idcache_range((uintptr_t)ram_ptr, (uintptr_t)ram_ptr, l); + } + len -= l; + addr += l; + } } /* -- 2.51.0