[PATCH 0/4] Fix Ethernet interface support for microchip-icicle-kit

[Guenter Roeck <linux@roeck-us.net>]

The Microchip PolarFire SoC Icicle Kit supports two Ethernet interfaces.
The PHY on each may be connected to separate MDIO busses, or both may be
connected on the same MDIO bus using different PHY addresses. Add support
for it to the Cadence GEM emulation.

The Linux kernel checks the PCS disabled bit in the R_DESCONF register
to determine if SGMII is supported. If the bit is set, SGMII support is
disabled. Since the Microchip Icicle devicetree file configures SGMII
interface mode, enabling the Ethernet interfaces fails when booting
the Linux kernel. Add support for clearing the PCS disabled bit.

----------------------------------------------------------------
Guenter Roeck (4):
      hw/net/cadence_gem: Support two Ethernet interfaces connected to single MDIO bus
      hw/riscv: microchip_pfsoc: Connect Ethernet PHY channels
      hw/net/cadence_gem: Add pcs-enabled property
      microchip icicle: Enable PCS on Cadence Ethernet

 hw/net/cadence_gem.c         | 31 ++++++++++++++++++++++++-------
 hw/riscv/microchip_pfsoc.c   |  6 ++++++
 include/hw/net/cadence_gem.h |  4 ++++
 3 files changed, 34 insertions(+), 7 deletions(-)