From: Guenter Roeck <linux@roeck-us.net>
To: "Edgar E . Iglesias" <edgar.iglesias@gmail.com>,
Alistair Francis <alistair@alistair23.me>,
Peter Maydell <peter.maydell@linaro.org>
Cc: Jason Wang <jasowang@redhat.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org,
qemu-riscv@nongnu.org, Guenter Roeck <linux@roeck-us.net>
Subject: [PATCH 3/4] hw/net/cadence_gem: Add pcs-enabled property
Date: Sat, 4 Oct 2025 13:00:48 -0700 [thread overview]
Message-ID: <20251004200049.871646-4-linux@roeck-us.net> (raw)
In-Reply-To: <20251004200049.871646-1-linux@roeck-us.net>
The Linux kernel checks the PCS disabled bit in the R_DESCONF register
to determine if SGMII is supported. If the bit is set, SGMII support is
disabled. Since the Microchip Icicle devicetree file configures SGMII
interface mode, enabling the Ethernet interfaces fails when booting
the Linux kernel.
Add pcs-enabled property to to let the driver know if PCS should be
enabled. Set the flag to false by default (indicating that PCS is disabled)
to match the exiting code.
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
---
hw/net/cadence_gem.c | 7 ++++++-
include/hw/net/cadence_gem.h | 1 +
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 520324adfd..44896f1801 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -1477,7 +1477,10 @@ static void gem_reset(DeviceState *d)
s->regs[R_TXPARTIALSF] = 0x000003ff;
s->regs[R_RXPARTIALSF] = 0x000003ff;
s->regs[R_MODID] = s->revision;
- s->regs[R_DESCONF] = 0x02D00111;
+ s->regs[R_DESCONF] = 0x02D00110;
+ if (!s->pcs_enabled) {
+ s->regs[R_DESCONF] |= 0x00000001;
+ }
s->regs[R_DESCONF2] = 0x2ab10000 | s->jumbo_max_len;
s->regs[R_DESCONF5] = 0x002f2045;
s->regs[R_DESCONF6] = R_DESCONF6_DMA_ADDR_64B_MASK;
@@ -1821,6 +1824,8 @@ static const Property gem_properties[] = {
num_type2_screeners, 4),
DEFINE_PROP_UINT16("jumbo-max-len", CadenceGEMState,
jumbo_max_len, 10240),
+ DEFINE_PROP_BOOL("pcs-enabled", CadenceGEMState,
+ pcs_enabled, false),
DEFINE_PROP_BOOL("phy-connected", CadenceGEMState, phy_connected, true),
DEFINE_PROP_LINK("phy-consumer", CadenceGEMState, phy_consumer,
TYPE_CADENCE_GEM, CadenceGEMState *),
diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h
index 21e7319f53..e63941f18f 100644
--- a/include/hw/net/cadence_gem.h
+++ b/include/hw/net/cadence_gem.h
@@ -62,6 +62,7 @@ struct CadenceGEMState {
uint8_t num_type2_screeners;
uint32_t revision;
uint16_t jumbo_max_len;
+ bool pcs_enabled;
/* GEM registers backing store */
uint32_t regs[CADENCE_GEM_MAXREG];
--
2.45.2
next prev parent reply other threads:[~2025-10-04 20:02 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-04 20:00 [PATCH 0/4] Fix Ethernet interface support for microchip-icicle-kit Guenter Roeck
2025-10-04 20:00 ` [PATCH 1/4] hw/net/cadence_gem: Support two Ethernet interfaces connected to single MDIO bus Guenter Roeck
2025-10-15 2:18 ` Alistair Francis
2025-10-04 20:00 ` [PATCH 2/4] hw/riscv: microchip_pfsoc: Connect Ethernet PHY channels Guenter Roeck
2025-10-15 2:20 ` Alistair Francis
2025-10-04 20:00 ` Guenter Roeck [this message]
2025-10-15 2:23 ` [PATCH 3/4] hw/net/cadence_gem: Add pcs-enabled property Alistair Francis
2025-10-04 20:00 ` [PATCH 4/4] microchip icicle: Enable PCS on Cadence Ethernet Guenter Roeck
2025-10-15 2:23 ` Alistair Francis
2025-10-15 3:03 ` [PATCH 0/4] Fix Ethernet interface support for microchip-icicle-kit Alistair Francis
2025-10-15 9:04 ` Conor Dooley
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