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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 15/62] hw/arm/xlnx-versal: bbram: refactor creation
Date: Tue,  7 Oct 2025 15:10:35 +0100	[thread overview]
Message-ID: <20251007141123.3239867-16-peter.maydell@linaro.org> (raw)
In-Reply-To: <20251007141123.3239867-1-peter.maydell@linaro.org>

From: Luc Michel <luc.michel@amd.com>

Refactor the BBRAM device creation using the VersalMap structure.

Note that the corresponding FDT node is removed. It does not correspond
to any real node in standard Versal DTBs. No matching drivers exist for
it.

Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20250926070806.292065-15-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/xlnx-versal.h |  3 +--
 hw/arm/xlnx-versal-virt.c    | 27 +++---------------------
 hw/arm/xlnx-versal.c         | 41 +++++++++++++++++++++++++-----------
 3 files changed, 33 insertions(+), 38 deletions(-)

diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
index 78442e6c2c5..9adce02f8a9 100644
--- a/include/hw/arm/xlnx-versal.h
+++ b/include/hw/arm/xlnx-versal.h
@@ -19,7 +19,6 @@
 #include "hw/intc/arm_gicv3.h"
 #include "hw/rtc/xlnx-zynqmp-rtc.h"
 #include "qom/object.h"
-#include "hw/nvram/xlnx-bbram.h"
 #include "hw/misc/xlnx-versal-crl.h"
 #include "hw/misc/xlnx-versal-trng.h"
 #include "net/can_emu.h"
@@ -85,7 +84,6 @@ struct Versal {
     struct {
         XlnxZynqMPRTC rtc;
         XlnxVersalTRng trng;
-        XlnxBBRam bbram;
         XlnxVersalCFUAPB cfu_apb;
         XlnxVersalCFUFDRO cfu_fdro;
         XlnxVersalCFUSFR cfu_sfr;
@@ -121,6 +119,7 @@ static inline void versal_set_fdt(Versal *s, void *fdt)
 
 void versal_sdhci_plug_card(Versal *s, int sd_idx, BlockBackend *blk);
 void versal_efuse_attach_drive(Versal *s, BlockBackend *blk);
+void versal_bbram_attach_drive(Versal *s, BlockBackend *blk);
 void versal_ospi_create_flash(Versal *s, int flash_idx, const char *flash_mdl,
                               BlockBackend *blk);
 
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index a948e24aea0..f766a3e1027 100644
--- a/hw/arm/xlnx-versal-virt.c
+++ b/hw/arm/xlnx-versal-virt.c
@@ -172,26 +172,6 @@ static void fdt_add_rtc_node(VersalVirt *s)
     g_free(name);
 }
 
-static void fdt_add_bbram_node(VersalVirt *s)
-{
-    const char compat[] = TYPE_XLNX_BBRAM;
-    const char interrupt_names[] = "bbram-error";
-    char *name = g_strdup_printf("/bbram@%x", MM_PMC_BBRAM_CTRL);
-
-    qemu_fdt_add_subnode(s->fdt, name);
-
-    qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
-                           GIC_FDT_IRQ_TYPE_SPI, VERSAL_PMC_APB_IRQ,
-                           GIC_FDT_IRQ_FLAGS_LEVEL_HI);
-    qemu_fdt_setprop(s->fdt, name, "interrupt-names",
-                     interrupt_names, sizeof(interrupt_names));
-    qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
-                                 2, MM_PMC_BBRAM_CTRL,
-                                 2, MM_PMC_BBRAM_CTRL_SIZE);
-    qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat));
-    g_free(name);
-}
-
 static void fdt_nop_memory_nodes(void *fdt, Error **errp)
 {
     Error *err = NULL;
@@ -346,7 +326,7 @@ static void create_virtio_regions(VersalVirt *s)
     }
 }
 
-static void bbram_attach_drive(XlnxBBRam *dev)
+static void bbram_attach_drive(VersalVirt *s)
 {
     DriveInfo *dinfo;
     BlockBackend *blk;
@@ -354,7 +334,7 @@ static void bbram_attach_drive(XlnxBBRam *dev)
     dinfo = drive_get_by_index(IF_PFLASH, 0);
     blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
     if (blk) {
-        qdev_prop_set_drive(DEVICE(dev), "drive", blk);
+        versal_bbram_attach_drive(&s->soc, blk);
     }
 }
 
@@ -447,7 +427,6 @@ static void versal_virt_init(MachineState *machine)
     fdt_add_gic_nodes(s);
     fdt_add_timer_nodes(s);
     fdt_add_rtc_node(s);
-    fdt_add_bbram_node(s);
     fdt_add_cpu_nodes(s, psci_conduit);
     fdt_add_clk_node(s, "/old-clk125", 125000000, s->phandle.clk_125Mhz);
     fdt_add_clk_node(s, "/old-clk25", 25000000, s->phandle.clk_25Mhz);
@@ -458,7 +437,7 @@ static void versal_virt_init(MachineState *machine)
                                         0, &s->soc.fpd.apu.mr, 0);
 
     /* Attach bbram backend, if given */
-    bbram_attach_drive(&s->soc.pmc.bbram);
+    bbram_attach_drive(s);
 
     /* Attach efuse backend, if given */
     efuse_attach_drive(s);
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index e71c774e72e..31ceaf61bed 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -36,6 +36,7 @@
 #include "hw/nvram/xlnx-versal-efuse.h"
 #include "hw/ssi/xlnx-versal-ospi.h"
 #include "hw/misc/xlnx-versal-pmc-iou-slcr.h"
+#include "hw/nvram/xlnx-bbram.h"
 
 #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72")
 #define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f")
@@ -119,6 +120,7 @@ typedef struct VersalMap {
     } ospi;
 
     VersalSimplePeriphMap pmc_iou_slcr;
+    VersalSimplePeriphMap bbram;
 } VersalMap;
 
 static const VersalMap VERSAL_MAP = {
@@ -161,6 +163,7 @@ static const VersalMap VERSAL_MAP = {
     },
 
     .pmc_iou_slcr = { 0xf1060000, OR_IRQ(121, 0) },
+    .bbram = { 0xf11f0000, OR_IRQ(121, 1) },
 };
 
 static const VersalMap *VERSION_TO_MAP[] = {
@@ -820,22 +823,21 @@ static void versal_create_xrams(Versal *s, const struct VersalXramMap *map)
     }
 }
 
-static void versal_create_bbram(Versal *s, qemu_irq *pic)
+static void versal_create_bbram(Versal *s,
+                                const VersalSimplePeriphMap *map)
 {
+    DeviceState *dev;
     SysBusDevice *sbd;
 
-    object_initialize_child_with_props(OBJECT(s), "bbram", &s->pmc.bbram,
-                                       sizeof(s->pmc.bbram), TYPE_XLNX_BBRAM,
-                                       &error_fatal,
-                                       "crc-zpads", "0",
-                                       NULL);
-    sbd = SYS_BUS_DEVICE(&s->pmc.bbram);
+    dev = qdev_new(TYPE_XLNX_BBRAM);
+    sbd = SYS_BUS_DEVICE(dev);
 
-    sysbus_realize(sbd, &error_fatal);
-    memory_region_add_subregion(&s->mr_ps, MM_PMC_BBRAM_CTRL,
+    object_property_add_child(OBJECT(s), "bbram", OBJECT(dev));
+    qdev_prop_set_uint32(dev, "crc-zpads", 0);
+    sysbus_realize_and_unref(sbd, &error_abort);
+    memory_region_add_subregion(&s->mr_ps, map->addr,
                                 sysbus_mmio_get_region(sbd, 0));
-    sysbus_connect_irq(sbd, 0,
-                       qdev_get_gpio_in(DEVICE(&s->pmc.apb_irq_orgate), 1));
+    versal_sysbus_connect_irq(s, sbd, 0, map->irq);
 }
 
 static void versal_create_efuse(Versal *s,
@@ -1334,10 +1336,12 @@ static void versal_realize(DeviceState *dev, Error **errp)
     qdev_connect_gpio_out_named(slcr, "ospi-mux-sel", 0,
                                 qdev_get_gpio_in_named(ospi,
                                                        "ospi-mux-sel", 0));
+
+    versal_create_bbram(s, &map->bbram);
+
     versal_create_pmc_apb_irq_orgate(s, pic);
     versal_create_rtc(s, pic);
     versal_create_trng(s, pic);
-    versal_create_bbram(s, pic);
     versal_create_crl(s, pic);
     versal_create_cfu(s, pic);
     versal_map_ddr(s);
@@ -1383,6 +1387,19 @@ void versal_efuse_attach_drive(Versal *s, BlockBackend *blk)
     qdev_prop_set_drive(efuse, "drive", blk);
 }
 
+void versal_bbram_attach_drive(Versal *s, BlockBackend *blk)
+{
+    DeviceState *bbram;
+
+    bbram = DEVICE(versal_get_child(s, "bbram"));
+
+    if (bbram == NULL) {
+        return;
+    }
+
+    qdev_prop_set_drive(bbram, "drive", blk);
+}
+
 void versal_ospi_create_flash(Versal *s, int flash_idx, const char *flash_mdl,
                               BlockBackend *blk)
 {
-- 
2.43.0



  parent reply	other threads:[~2025-10-07 14:13 UTC|newest]

Thread overview: 64+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-07 14:10 [PULL 00/62] target-arm queue Peter Maydell
2025-10-07 14:10 ` [PULL 01/62] target/arm: Don't set HCR.RW for AArch32 only CPUs Peter Maydell
2025-10-07 14:10 ` [PULL 02/62] hw/arm/xlnx-versal: split the xlnx-versal type Peter Maydell
2025-10-07 14:10 ` [PULL 03/62] hw/arm/xlnx-versal: prepare for FDT creation Peter Maydell
2025-10-07 14:10 ` [PULL 04/62] hw/arm/xlnx-versal: uart: refactor creation Peter Maydell
2025-10-07 14:10 ` [PULL 05/62] hw/arm/xlnx-versal: canfd: " Peter Maydell
2025-10-07 14:10 ` [PULL 06/62] hw/arm/xlnx-versal: sdhci: " Peter Maydell
2025-10-07 14:10 ` [PULL 07/62] hw/arm/xlnx-versal: gem: " Peter Maydell
2025-10-07 14:10 ` [PULL 08/62] hw/arm/xlnx-versal: adma: " Peter Maydell
2025-10-07 14:10 ` [PULL 09/62] hw/arm/xlnx-versal: xram: " Peter Maydell
2025-10-07 14:10 ` [PULL 10/62] hw/arm/xlnx-versal: usb: " Peter Maydell
2025-10-07 14:10 ` [PULL 11/62] hw/arm/xlnx-versal: efuse: " Peter Maydell
2025-10-07 14:10 ` [PULL 12/62] hw/arm/xlnx-versal: ospi: " Peter Maydell
2025-10-07 14:10 ` [PULL 13/62] hw/arm/xlnx-versal: VersalMap: add support for OR'ed IRQs Peter Maydell
2025-10-07 14:10 ` [PULL 14/62] hw/arm/xlnx-versal: PMC IOU SCLR: refactor creation Peter Maydell
2025-10-07 14:10 ` Peter Maydell [this message]
2025-10-07 14:10 ` [PULL 16/62] hw/arm/xlnx-versal: trng: " Peter Maydell
2025-10-07 14:10 ` [PULL 17/62] hw/arm/xlnx-versal: rtc: " Peter Maydell
2025-10-07 14:10 ` [PULL 18/62] hw/arm/xlnx-versal: cfu: " Peter Maydell
2025-10-07 14:10 ` [PULL 19/62] hw/arm/xlnx-versal: crl: " Peter Maydell
2025-10-07 14:10 ` [PULL 20/62] hw/arm/xlnx-versal-virt: virtio: " Peter Maydell
2025-10-07 14:10 ` [PULL 21/62] hw/arm/xlnx-versal: refactor CPU cluster creation Peter Maydell
2025-10-07 14:10 ` [PULL 22/62] hw/arm/xlnx-versal: add the mp_affinity property to the CPU mapping Peter Maydell
2025-10-07 14:10 ` [PULL 23/62] hw/arm/xlnx-versal: instantiate the GIC ITS in the APU Peter Maydell
2025-10-07 14:10 ` [PULL 24/62] hw/intc/arm_gicv3: Introduce a 'first-cpu-index' property Peter Maydell
2025-10-07 14:10 ` [PULL 25/62] hw/arm/xlnx-versal: add support for multiple GICs Peter Maydell
2025-10-07 14:10 ` [PULL 26/62] hw/arm/xlnx-versal: add support for GICv2 Peter Maydell
2025-10-07 14:10 ` [PULL 27/62] hw/arm/xlnx-versal: rpu: refactor creation Peter Maydell
2025-10-07 14:10 ` [PULL 28/62] hw/arm/xlnx-versal: ocm: " Peter Maydell
2025-10-07 14:10 ` [PULL 29/62] hw/arm/xlnx-versal: ddr: " Peter Maydell
2025-10-07 14:10 ` [PULL 30/62] hw/arm/xlnx-versal: add the versal_get_num_cpu accessor Peter Maydell
2025-10-07 14:10 ` [PULL 31/62] hw/misc/xlnx-versal-crl: remove unnecessary include directives Peter Maydell
2025-10-07 14:10 ` [PULL 32/62] hw/misc/xlnx-versal-crl: split into base/concrete classes Peter Maydell
2025-10-07 14:10 ` [PULL 33/62] hw/misc/xlnx-versal-crl: refactor device reset logic Peter Maydell
2025-10-07 14:10 ` [PULL 34/62] hw/arm/xlnx-versal: reconnect the CRL to the other devices Peter Maydell
2025-10-07 14:10 ` [PULL 35/62] hw/arm/xlnx-versal: use hw/arm/bsa.h for timer IRQ indices Peter Maydell
2025-10-07 14:10 ` [PULL 36/62] hw/arm/xlnx-versal: tidy up Peter Maydell
2025-10-07 14:10 ` [PULL 37/62] hw/misc/xlnx-versal-crl: add the versal2 version Peter Maydell
2025-10-07 14:10 ` [PULL 38/62] hw/arm/xlnx-versal: add a per_cluster_gic switch to VersalCpuClusterMap Peter Maydell
2025-10-07 14:10 ` [PULL 39/62] hw/arm/xlnx-versal: add the target field in IRQ descriptor Peter Maydell
2025-10-07 14:11 ` [PULL 40/62] target/arm/tcg/cpu64: add the cortex-a78ae CPU Peter Maydell
2025-10-07 14:11 ` [PULL 41/62] hw/arm/xlnx-versal: add versal2 SoC Peter Maydell
2025-10-07 14:11 ` [PULL 42/62] hw/arm/xlnx-versal-virt: rename the machine to amd-versal-virt Peter Maydell
2025-10-07 14:11 ` [PULL 43/62] hw/arm/xlnx-versal-virt: split into base/concrete classes Peter Maydell
2025-10-07 14:11 ` [PULL 44/62] hw/arm/xlnx-versal-virt: tidy up Peter Maydell
2025-10-07 14:11 ` [PULL 45/62] docs/system/arm/xlnx-versal-virt: update supported devices Peter Maydell
2025-10-07 14:11 ` [PULL 46/62] docs/system/arm/xlnx-versal-virt: add a note about dumpdtb Peter Maydell
2025-10-07 14:11 ` [PULL 47/62] hw/arm/xlnx-versal-virt: add the xlnx-versal2-virt machine Peter Maydell
2025-10-07 14:11 ` [PULL 48/62] tests/functional/test_aarch64_xlnx_versal: test the versal2 machine Peter Maydell
2025-10-07 14:11 ` [PULL 49/62] hw/arm/xlnx-zynqmp: move GIC_NUM_SPI_INTR define in header Peter Maydell
2025-10-07 14:11 ` [PULL 50/62] hw/arm/xlnx-zynqmp: introduce helper to compute RPU number Peter Maydell
2025-10-07 14:11 ` [PULL 51/62] hw/arm/xlnx-zynqmp: wire a second GIC for the Cortex-R5 Peter Maydell
2025-10-07 14:11 ` [PULL 52/62] hw/arm: Remove sl_bootparam_write() and 'hw/arm/sharpsl.h' header Peter Maydell
2025-10-07 14:11 ` [PULL 53/62] target/arm: Add isar feature test for FEAT_RME_GPC2 Peter Maydell
2025-10-07 14:11 ` [PULL 54/62] target/arm: Add GPCCR fields from ARM revision L.b Peter Maydell
2025-10-07 14:11 ` [PULL 55/62] target/arm: Enable FEAT_RME_GPC2 bits in gpccr_write Peter Maydell
2025-10-07 14:11 ` [PULL 56/62] target/arm: Add cur_space to S1Translate Peter Maydell
2025-10-07 14:11 ` [PULL 57/62] target/arm: GPT_Secure is reserved without FEAT_SEL2 Peter Maydell
2025-10-07 14:11 ` [PULL 58/62] target/arm: Implement GPT_NonSecureOnly Peter Maydell
2025-10-07 14:11 ` [PULL 59/62] target/arm: Implement SPAD, NSPAD, RLPAD Peter Maydell
2025-10-07 14:11 ` [PULL 60/62] target/arm: Fix GPT fault type for address outside PPS Peter Maydell
2025-10-07 14:11 ` [PULL 61/62] target/arm: Implement APPSAA Peter Maydell
2025-10-07 14:11 ` [PULL 62/62] target/arm: Enable FEAT_RME_GPC2 for -cpu max with x-rme Peter Maydell
2025-10-07 22:58 ` [PULL 00/62] target-arm queue Richard Henderson

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