From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 44/62] hw/arm/xlnx-versal-virt: tidy up
Date: Tue, 7 Oct 2025 15:11:04 +0100 [thread overview]
Message-ID: <20251007141123.3239867-45-peter.maydell@linaro.org> (raw)
In-Reply-To: <20251007141123.3239867-1-peter.maydell@linaro.org>
From: Luc Michel <luc.michel@amd.com>
Remove now unused clock nodes. They have been replaced by the ones
created in the SoC. Remove the unused cfg.secure VersalVirt field.
Remove unecessary include directives.
Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20250926070806.292065-44-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/xlnx-versal-virt.c | 25 -------------------------
1 file changed, 25 deletions(-)
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index f9abb9ed639..14c2d5cc924 100644
--- a/hw/arm/xlnx-versal-virt.c
+++ b/hw/arm/xlnx-versal-virt.c
@@ -19,10 +19,8 @@
#include "hw/boards.h"
#include "hw/sysbus.h"
#include "hw/arm/fdt.h"
-#include "hw/qdev-properties.h"
#include "hw/arm/xlnx-versal.h"
#include "hw/arm/boot.h"
-#include "target/arm/multiprocessing.h"
#include "qom/object.h"
#include "target/arm/cpu.h"
@@ -41,16 +39,11 @@ struct VersalVirt {
void *fdt;
int fdt_size;
- struct {
- uint32_t clk_125Mhz;
- uint32_t clk_25Mhz;
- } phandle;
struct arm_boot_info binfo;
CanBusState **canbus;
struct {
- bool secure;
char *ospi_model;
} cfg;
};
@@ -72,10 +65,6 @@ static void fdt_create(VersalVirt *s)
exit(1);
}
- /* Allocate all phandles. */
- s->phandle.clk_25Mhz = qemu_fdt_alloc_phandle(s->fdt);
- s->phandle.clk_125Mhz = qemu_fdt_alloc_phandle(s->fdt);
-
/* Create /chosen node for load_dtb. */
qemu_fdt_add_subnode(s->fdt, "/chosen");
qemu_fdt_add_subnode(s->fdt, "/aliases");
@@ -86,17 +75,6 @@ static void fdt_create(VersalVirt *s)
sizeof(versal_compat));
}
-static void fdt_add_clk_node(VersalVirt *s, const char *name,
- unsigned int freq_hz, uint32_t phandle)
-{
- qemu_fdt_add_subnode(s->fdt, name);
- qemu_fdt_setprop_cell(s->fdt, name, "phandle", phandle);
- qemu_fdt_setprop_cell(s->fdt, name, "clock-frequency", freq_hz);
- qemu_fdt_setprop_cell(s->fdt, name, "#clock-cells", 0x0);
- qemu_fdt_setprop_string(s->fdt, name, "compatible", "fixed-clock");
- qemu_fdt_setprop(s->fdt, name, "u-boot,dm-pre-reloc", NULL, 0);
-}
-
static void fdt_nop_memory_nodes(void *fdt, Error **errp)
{
Error *err = NULL;
@@ -268,9 +246,6 @@ static void versal_virt_init(MachineState *machine)
sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal);
create_virtio_regions(s);
- fdt_add_clk_node(s, "/old-clk125", 125000000, s->phandle.clk_125Mhz);
- fdt_add_clk_node(s, "/old-clk25", 25000000, s->phandle.clk_25Mhz);
-
/*
* Map the SoC address space onto system memory. This will allow virtio and
* other modules unaware of multiple address-spaces to work.
--
2.43.0
next prev parent reply other threads:[~2025-10-07 14:33 UTC|newest]
Thread overview: 64+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-07 14:10 [PULL 00/62] target-arm queue Peter Maydell
2025-10-07 14:10 ` [PULL 01/62] target/arm: Don't set HCR.RW for AArch32 only CPUs Peter Maydell
2025-10-07 14:10 ` [PULL 02/62] hw/arm/xlnx-versal: split the xlnx-versal type Peter Maydell
2025-10-07 14:10 ` [PULL 03/62] hw/arm/xlnx-versal: prepare for FDT creation Peter Maydell
2025-10-07 14:10 ` [PULL 04/62] hw/arm/xlnx-versal: uart: refactor creation Peter Maydell
2025-10-07 14:10 ` [PULL 05/62] hw/arm/xlnx-versal: canfd: " Peter Maydell
2025-10-07 14:10 ` [PULL 06/62] hw/arm/xlnx-versal: sdhci: " Peter Maydell
2025-10-07 14:10 ` [PULL 07/62] hw/arm/xlnx-versal: gem: " Peter Maydell
2025-10-07 14:10 ` [PULL 08/62] hw/arm/xlnx-versal: adma: " Peter Maydell
2025-10-07 14:10 ` [PULL 09/62] hw/arm/xlnx-versal: xram: " Peter Maydell
2025-10-07 14:10 ` [PULL 10/62] hw/arm/xlnx-versal: usb: " Peter Maydell
2025-10-07 14:10 ` [PULL 11/62] hw/arm/xlnx-versal: efuse: " Peter Maydell
2025-10-07 14:10 ` [PULL 12/62] hw/arm/xlnx-versal: ospi: " Peter Maydell
2025-10-07 14:10 ` [PULL 13/62] hw/arm/xlnx-versal: VersalMap: add support for OR'ed IRQs Peter Maydell
2025-10-07 14:10 ` [PULL 14/62] hw/arm/xlnx-versal: PMC IOU SCLR: refactor creation Peter Maydell
2025-10-07 14:10 ` [PULL 15/62] hw/arm/xlnx-versal: bbram: " Peter Maydell
2025-10-07 14:10 ` [PULL 16/62] hw/arm/xlnx-versal: trng: " Peter Maydell
2025-10-07 14:10 ` [PULL 17/62] hw/arm/xlnx-versal: rtc: " Peter Maydell
2025-10-07 14:10 ` [PULL 18/62] hw/arm/xlnx-versal: cfu: " Peter Maydell
2025-10-07 14:10 ` [PULL 19/62] hw/arm/xlnx-versal: crl: " Peter Maydell
2025-10-07 14:10 ` [PULL 20/62] hw/arm/xlnx-versal-virt: virtio: " Peter Maydell
2025-10-07 14:10 ` [PULL 21/62] hw/arm/xlnx-versal: refactor CPU cluster creation Peter Maydell
2025-10-07 14:10 ` [PULL 22/62] hw/arm/xlnx-versal: add the mp_affinity property to the CPU mapping Peter Maydell
2025-10-07 14:10 ` [PULL 23/62] hw/arm/xlnx-versal: instantiate the GIC ITS in the APU Peter Maydell
2025-10-07 14:10 ` [PULL 24/62] hw/intc/arm_gicv3: Introduce a 'first-cpu-index' property Peter Maydell
2025-10-07 14:10 ` [PULL 25/62] hw/arm/xlnx-versal: add support for multiple GICs Peter Maydell
2025-10-07 14:10 ` [PULL 26/62] hw/arm/xlnx-versal: add support for GICv2 Peter Maydell
2025-10-07 14:10 ` [PULL 27/62] hw/arm/xlnx-versal: rpu: refactor creation Peter Maydell
2025-10-07 14:10 ` [PULL 28/62] hw/arm/xlnx-versal: ocm: " Peter Maydell
2025-10-07 14:10 ` [PULL 29/62] hw/arm/xlnx-versal: ddr: " Peter Maydell
2025-10-07 14:10 ` [PULL 30/62] hw/arm/xlnx-versal: add the versal_get_num_cpu accessor Peter Maydell
2025-10-07 14:10 ` [PULL 31/62] hw/misc/xlnx-versal-crl: remove unnecessary include directives Peter Maydell
2025-10-07 14:10 ` [PULL 32/62] hw/misc/xlnx-versal-crl: split into base/concrete classes Peter Maydell
2025-10-07 14:10 ` [PULL 33/62] hw/misc/xlnx-versal-crl: refactor device reset logic Peter Maydell
2025-10-07 14:10 ` [PULL 34/62] hw/arm/xlnx-versal: reconnect the CRL to the other devices Peter Maydell
2025-10-07 14:10 ` [PULL 35/62] hw/arm/xlnx-versal: use hw/arm/bsa.h for timer IRQ indices Peter Maydell
2025-10-07 14:10 ` [PULL 36/62] hw/arm/xlnx-versal: tidy up Peter Maydell
2025-10-07 14:10 ` [PULL 37/62] hw/misc/xlnx-versal-crl: add the versal2 version Peter Maydell
2025-10-07 14:10 ` [PULL 38/62] hw/arm/xlnx-versal: add a per_cluster_gic switch to VersalCpuClusterMap Peter Maydell
2025-10-07 14:10 ` [PULL 39/62] hw/arm/xlnx-versal: add the target field in IRQ descriptor Peter Maydell
2025-10-07 14:11 ` [PULL 40/62] target/arm/tcg/cpu64: add the cortex-a78ae CPU Peter Maydell
2025-10-07 14:11 ` [PULL 41/62] hw/arm/xlnx-versal: add versal2 SoC Peter Maydell
2025-10-07 14:11 ` [PULL 42/62] hw/arm/xlnx-versal-virt: rename the machine to amd-versal-virt Peter Maydell
2025-10-07 14:11 ` [PULL 43/62] hw/arm/xlnx-versal-virt: split into base/concrete classes Peter Maydell
2025-10-07 14:11 ` Peter Maydell [this message]
2025-10-07 14:11 ` [PULL 45/62] docs/system/arm/xlnx-versal-virt: update supported devices Peter Maydell
2025-10-07 14:11 ` [PULL 46/62] docs/system/arm/xlnx-versal-virt: add a note about dumpdtb Peter Maydell
2025-10-07 14:11 ` [PULL 47/62] hw/arm/xlnx-versal-virt: add the xlnx-versal2-virt machine Peter Maydell
2025-10-07 14:11 ` [PULL 48/62] tests/functional/test_aarch64_xlnx_versal: test the versal2 machine Peter Maydell
2025-10-07 14:11 ` [PULL 49/62] hw/arm/xlnx-zynqmp: move GIC_NUM_SPI_INTR define in header Peter Maydell
2025-10-07 14:11 ` [PULL 50/62] hw/arm/xlnx-zynqmp: introduce helper to compute RPU number Peter Maydell
2025-10-07 14:11 ` [PULL 51/62] hw/arm/xlnx-zynqmp: wire a second GIC for the Cortex-R5 Peter Maydell
2025-10-07 14:11 ` [PULL 52/62] hw/arm: Remove sl_bootparam_write() and 'hw/arm/sharpsl.h' header Peter Maydell
2025-10-07 14:11 ` [PULL 53/62] target/arm: Add isar feature test for FEAT_RME_GPC2 Peter Maydell
2025-10-07 14:11 ` [PULL 54/62] target/arm: Add GPCCR fields from ARM revision L.b Peter Maydell
2025-10-07 14:11 ` [PULL 55/62] target/arm: Enable FEAT_RME_GPC2 bits in gpccr_write Peter Maydell
2025-10-07 14:11 ` [PULL 56/62] target/arm: Add cur_space to S1Translate Peter Maydell
2025-10-07 14:11 ` [PULL 57/62] target/arm: GPT_Secure is reserved without FEAT_SEL2 Peter Maydell
2025-10-07 14:11 ` [PULL 58/62] target/arm: Implement GPT_NonSecureOnly Peter Maydell
2025-10-07 14:11 ` [PULL 59/62] target/arm: Implement SPAD, NSPAD, RLPAD Peter Maydell
2025-10-07 14:11 ` [PULL 60/62] target/arm: Fix GPT fault type for address outside PPS Peter Maydell
2025-10-07 14:11 ` [PULL 61/62] target/arm: Implement APPSAA Peter Maydell
2025-10-07 14:11 ` [PULL 62/62] target/arm: Enable FEAT_RME_GPC2 for -cpu max with x-rme Peter Maydell
2025-10-07 22:58 ` [PULL 00/62] target-arm queue Richard Henderson
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