* [PATCH v1 01/16] hw/arm/aspeed: Remove AspeedSoCState dependency from aspeed_uart_first() API
2025-10-08 3:21 [PATCH v1 00/16] Introduce AspeedCoprocessor class and base implementation Jamin Lin via
@ 2025-10-08 3:21 ` Jamin Lin via
2025-10-08 3:21 ` [PATCH v1 02/16] hw/arm/aspeed: Remove AspeedSoCClass dependency from aspeed_uart_last() API Jamin Lin via
` (14 subsequent siblings)
15 siblings, 0 replies; 19+ messages in thread
From: Jamin Lin via @ 2025-10-08 3:21 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
Refactor the aspeed_uart_first() helper to remove its dependency on
AspeedSoCState and make the UART helper APIs more generic.
The function now takes uarts_base as an integer parameter instead of
requiring a full SoC class instance. Corresponding call sites in
aspeed.c and aspeed_soc_common.c are updated accordingly.
No functional change.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/arm/aspeed_soc.h | 6 +++---
hw/arm/aspeed.c | 2 +-
hw/arm/aspeed_soc_common.c | 2 +-
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index ed32efb543..5786fbbcbb 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -326,14 +326,14 @@ static inline int aspeed_uart_index(int uart_dev)
return uart_dev - ASPEED_DEV_UART0;
}
-static inline int aspeed_uart_first(AspeedSoCClass *sc)
+static inline int aspeed_uart_first(int uarts_base)
{
- return aspeed_uart_index(sc->uarts_base);
+ return aspeed_uart_index(uarts_base);
}
static inline int aspeed_uart_last(AspeedSoCClass *sc)
{
- return aspeed_uart_first(sc) + sc->uarts_num - 1;
+ return aspeed_uart_first(sc->uarts_base) + sc->uarts_num - 1;
}
#endif /* ASPEED_SOC_H */
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 6046ec0bb2..471ad7fb84 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -1310,7 +1310,7 @@ static void aspeed_set_bmc_console(Object *obj, const char *value, Error **errp)
AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name));
int val;
- int uart_first = aspeed_uart_first(sc);
+ int uart_first = aspeed_uart_first(sc->uarts_base);
int uart_last = aspeed_uart_last(sc);
if (sscanf(value, "uart%u", &val) != 1) {
diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c
index bc70e864fb..a4e74acdce 100644
--- a/hw/arm/aspeed_soc_common.c
+++ b/hw/arm/aspeed_soc_common.c
@@ -62,7 +62,7 @@ bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp)
void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr)
{
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
- int uart_first = aspeed_uart_first(sc);
+ int uart_first = aspeed_uart_first(sc->uarts_base);
int uart_index = aspeed_uart_index(dev);
int i = uart_index - uart_first;
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v1 02/16] hw/arm/aspeed: Remove AspeedSoCClass dependency from aspeed_uart_last() API
2025-10-08 3:21 [PATCH v1 00/16] Introduce AspeedCoprocessor class and base implementation Jamin Lin via
2025-10-08 3:21 ` [PATCH v1 01/16] hw/arm/aspeed: Remove AspeedSoCState dependency from aspeed_uart_first() API Jamin Lin via
@ 2025-10-08 3:21 ` Jamin Lin via
2025-10-08 3:21 ` [PATCH v1 03/16] hw/arm/aspeed: Remove AspeedSoCState dependency from aspeed_soc_uart_set_chr() API Jamin Lin via
` (13 subsequent siblings)
15 siblings, 0 replies; 19+ messages in thread
From: Jamin Lin via @ 2025-10-08 3:21 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
Refactor the aspeed_uart_last() helper to remove its dependency on
AspeedSoCClass and make the UART helper APIs more generic.
The function now takes uarts_base and uarts_num as integer
parameters instead of requiring a full SoC class instance.
All related call sites in aspeed.c are updated accordingly.
No functional change.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/arm/aspeed_soc.h | 4 ++--
hw/arm/aspeed.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 5786fbbcbb..0162738f88 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -331,9 +331,9 @@ static inline int aspeed_uart_first(int uarts_base)
return aspeed_uart_index(uarts_base);
}
-static inline int aspeed_uart_last(AspeedSoCClass *sc)
+static inline int aspeed_uart_last(int uarts_base, int uarts_num)
{
- return aspeed_uart_first(sc->uarts_base) + sc->uarts_num - 1;
+ return aspeed_uart_first(uarts_base) + uarts_num - 1;
}
#endif /* ASPEED_SOC_H */
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 471ad7fb84..19944ea026 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -1311,7 +1311,7 @@ static void aspeed_set_bmc_console(Object *obj, const char *value, Error **errp)
AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name));
int val;
int uart_first = aspeed_uart_first(sc->uarts_base);
- int uart_last = aspeed_uart_last(sc);
+ int uart_last = aspeed_uart_last(sc->uarts_base, sc->uarts_num);
if (sscanf(value, "uart%u", &val) != 1) {
error_setg(errp, "Bad value for \"uart\" property");
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v1 03/16] hw/arm/aspeed: Remove AspeedSoCState dependency from aspeed_soc_uart_set_chr() API
2025-10-08 3:21 [PATCH v1 00/16] Introduce AspeedCoprocessor class and base implementation Jamin Lin via
2025-10-08 3:21 ` [PATCH v1 01/16] hw/arm/aspeed: Remove AspeedSoCState dependency from aspeed_uart_first() API Jamin Lin via
2025-10-08 3:21 ` [PATCH v1 02/16] hw/arm/aspeed: Remove AspeedSoCClass dependency from aspeed_uart_last() API Jamin Lin via
@ 2025-10-08 3:21 ` Jamin Lin via
2025-10-08 3:21 ` [PATCH v1 04/16] hw/arm/aspeed: Remove AspeedSoCClass dependency from aspeed_soc_cpu_type() API Jamin Lin via
` (12 subsequent siblings)
15 siblings, 0 replies; 19+ messages in thread
From: Jamin Lin via @ 2025-10-08 3:21 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
Refactor the aspeed_soc_uart_set_chr() helper to remove its dependency
on AspeedSoCState and make the UART character device binding more
generic.
The function now takes SerialMM *uart, uarts_base, and uarts_num
as arguments instead of relying on AspeedSoCState. All affected call
sites in aspeed.c, aspeed_ast27x0-fc.c, and fby35.c are updated
to use the new parameter format.
This improves API flexibility and enables reuse across different Aspeed
SoC variants without requiring access to internal SoC state.
No functional change.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/arm/aspeed_soc.h | 3 ++-
hw/arm/aspeed.c | 6 ++++--
hw/arm/aspeed_ast27x0-fc.c | 13 ++++++++++---
hw/arm/aspeed_soc_common.c | 10 +++++-----
hw/arm/fby35.c | 10 ++++++++--
5 files changed, 29 insertions(+), 13 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 0162738f88..c870bf5586 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -306,7 +306,8 @@ enum {
qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev);
bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp);
-void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr);
+void aspeed_soc_uart_set_chr(SerialMM *uart, int dev, int uarts_base,
+ int uarts_num, Chardev *chr);
bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp);
void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr);
void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 19944ea026..cbd9a0932b 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -299,12 +299,14 @@ static void connect_serial_hds_to_uarts(AspeedMachineState *bmc)
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default;
- aspeed_soc_uart_set_chr(s, uart_chosen, serial_hd(0));
+ aspeed_soc_uart_set_chr(s->uart, uart_chosen, sc->uarts_base,
+ sc->uarts_num, serial_hd(0));
for (int i = 1, uart = sc->uarts_base; i < sc->uarts_num; uart++) {
if (uart == uart_chosen) {
continue;
}
- aspeed_soc_uart_set_chr(s, uart, serial_hd(i++));
+ aspeed_soc_uart_set_chr(s->uart, uart, sc->uarts_base, sc->uarts_num,
+ serial_hd(i++));
}
}
diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
index 2e16a0340a..e598f57ca2 100644
--- a/hw/arm/aspeed_ast27x0-fc.c
+++ b/hw/arm/aspeed_ast27x0-fc.c
@@ -91,7 +91,8 @@ static bool ast2700fc_ca35_init(MachineState *machine, Error **errp)
AST2700FC_HW_STRAP1, &error_abort);
object_property_set_int(OBJECT(&s->ca35), "hw-strap2",
AST2700FC_HW_STRAP2, &error_abort);
- aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART12, serial_hd(0));
+ aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART12, sc->uarts_base,
+ sc->uarts_num, serial_hd(0));
if (!qdev_realize(DEVICE(&s->ca35), NULL, errp)) {
return false;
}
@@ -115,6 +116,7 @@ static bool ast2700fc_ca35_init(MachineState *machine, Error **errp)
static bool ast2700fc_ssp_init(MachineState *machine, Error **errp)
{
AspeedSoCState *soc;
+ AspeedSoCClass *sc;
Ast2700FCState *s = AST2700A1FC(machine);
s->ssp_sysclk = clock_new(OBJECT(s), "SSP_SYSCLK");
clock_set_hz(s->ssp_sysclk, 200000000ULL);
@@ -128,7 +130,9 @@ static bool ast2700fc_ssp_init(MachineState *machine, Error **errp)
OBJECT(&s->ssp_memory), &error_abort);
soc = ASPEED_SOC(&s->ssp);
- aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART4, serial_hd(1));
+ sc = ASPEED_SOC_GET_CLASS(soc);
+ aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART4, sc->uarts_base,
+ sc->uarts_num, serial_hd(1));
if (!qdev_realize(DEVICE(&s->ssp), NULL, errp)) {
return false;
}
@@ -139,6 +143,7 @@ static bool ast2700fc_ssp_init(MachineState *machine, Error **errp)
static bool ast2700fc_tsp_init(MachineState *machine, Error **errp)
{
AspeedSoCState *soc;
+ AspeedSoCClass *sc;
Ast2700FCState *s = AST2700A1FC(machine);
s->tsp_sysclk = clock_new(OBJECT(s), "TSP_SYSCLK");
clock_set_hz(s->tsp_sysclk, 200000000ULL);
@@ -152,7 +157,9 @@ static bool ast2700fc_tsp_init(MachineState *machine, Error **errp)
OBJECT(&s->tsp_memory), &error_abort);
soc = ASPEED_SOC(&s->tsp);
- aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART7, serial_hd(2));
+ sc = ASPEED_SOC_GET_CLASS(soc);
+ aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART7, sc->uarts_base,
+ sc->uarts_num, serial_hd(2));
if (!qdev_realize(DEVICE(&s->tsp), NULL, errp)) {
return false;
}
diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c
index a4e74acdce..ddcbba0020 100644
--- a/hw/arm/aspeed_soc_common.c
+++ b/hw/arm/aspeed_soc_common.c
@@ -59,15 +59,15 @@ bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp)
return true;
}
-void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr)
+void aspeed_soc_uart_set_chr(SerialMM *uart, int dev, int uarts_base,
+ int uarts_num, Chardev *chr)
{
- AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
- int uart_first = aspeed_uart_first(sc->uarts_base);
+ int uart_first = aspeed_uart_first(uarts_base);
int uart_index = aspeed_uart_index(dev);
int i = uart_index - uart_first;
- g_assert(0 <= i && i < ARRAY_SIZE(s->uart) && i < sc->uarts_num);
- qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);
+ g_assert(0 <= i && i < ASPEED_UARTS_NUM && i < uarts_num);
+ qdev_prop_set_chr(DEVICE(&uart[i]), "chardev", chr);
}
/*
diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c
index c14fc2efe9..5a94c847d3 100644
--- a/hw/arm/fby35.c
+++ b/hw/arm/fby35.c
@@ -71,9 +71,11 @@ static void fby35_bmc_write_boot_rom(DriveInfo *dinfo, MemoryRegion *mr,
static void fby35_bmc_init(Fby35State *s)
{
AspeedSoCState *soc;
+ AspeedSoCClass *sc;
object_initialize_child(OBJECT(s), "bmc", &s->bmc, "ast2600-a3");
soc = ASPEED_SOC(&s->bmc);
+ sc = ASPEED_SOC_GET_CLASS(soc);
memory_region_init(&s->bmc_memory, OBJECT(&s->bmc), "bmc-memory",
UINT64_MAX);
@@ -91,7 +93,8 @@ static void fby35_bmc_init(Fby35State *s)
&error_abort);
object_property_set_int(OBJECT(&s->bmc), "hw-strap2", 0x00000003,
&error_abort);
- aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART5, serial_hd(0));
+ aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART5, sc->uarts_base,
+ sc->uarts_num, serial_hd(0));
qdev_realize(DEVICE(&s->bmc), NULL, &error_abort);
aspeed_board_init_flashes(&soc->fmc, "n25q00", 2, 0);
@@ -118,12 +121,14 @@ static void fby35_bmc_init(Fby35State *s)
static void fby35_bic_init(Fby35State *s)
{
AspeedSoCState *soc;
+ AspeedSoCClass *sc;
s->bic_sysclk = clock_new(OBJECT(s), "SYSCLK");
clock_set_hz(s->bic_sysclk, 200000000ULL);
object_initialize_child(OBJECT(s), "bic", &s->bic, "ast1030-a1");
soc = ASPEED_SOC(&s->bic);
+ sc = ASPEED_SOC_GET_CLASS(soc);
memory_region_init(&s->bic_memory, OBJECT(&s->bic), "bic-memory",
UINT64_MAX);
@@ -131,7 +136,8 @@ static void fby35_bic_init(Fby35State *s)
qdev_connect_clock_in(DEVICE(&s->bic), "sysclk", s->bic_sysclk);
object_property_set_link(OBJECT(&s->bic), "memory", OBJECT(&s->bic_memory),
&error_abort);
- aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART5, serial_hd(1));
+ aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART5, sc->uarts_base,
+ sc->uarts_num, serial_hd(1));
qdev_realize(DEVICE(&s->bic), NULL, &error_abort);
aspeed_board_init_flashes(&soc->fmc, "sst25vf032b", 2, 2);
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v1 04/16] hw/arm/aspeed: Remove AspeedSoCClass dependency from aspeed_soc_cpu_type() API
2025-10-08 3:21 [PATCH v1 00/16] Introduce AspeedCoprocessor class and base implementation Jamin Lin via
` (2 preceding siblings ...)
2025-10-08 3:21 ` [PATCH v1 03/16] hw/arm/aspeed: Remove AspeedSoCState dependency from aspeed_soc_uart_set_chr() API Jamin Lin via
@ 2025-10-08 3:21 ` Jamin Lin via
2025-10-08 3:21 ` [PATCH v1 05/16] hw/arm/aspeed: Remove AspeedSoCState dependency from aspeed_mmio_map() API Jamin Lin via
` (11 subsequent siblings)
15 siblings, 0 replies; 19+ messages in thread
From: Jamin Lin via @ 2025-10-08 3:21 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
Refactor the aspeed_soc_cpu_type() helper to remove its dependency on
AspeedSoCClass and make CPU type retrieval more generic.
The function now takes valid_cpu_types as a const char * const *
parameter instead of requiring a full AspeedSoCClass instance.
All corresponding call sites in various Aspeed SoC initialization files
(aspeed_ast10x0.c, aspeed_ast2400.c, aspeed_ast2600.c,
aspeed_ast27x0.c, and related variants) are updated accordingly.
This change simplifies the API, eliminates unnecessary type coupling,
and improves code reusability across different SoC families.
No functional change.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/arm/aspeed_soc.h | 3 +--
hw/arm/aspeed_ast10x0.c | 3 ++-
hw/arm/aspeed_ast2400.c | 2 +-
hw/arm/aspeed_ast2600.c | 2 +-
hw/arm/aspeed_ast27x0-ssp.c | 3 ++-
hw/arm/aspeed_ast27x0-tsp.c | 3 ++-
hw/arm/aspeed_ast27x0.c | 2 +-
hw/arm/aspeed_soc_common.c | 10 +++++-----
8 files changed, 15 insertions(+), 13 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index c870bf5586..385b657b50 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -202,8 +202,6 @@ struct AspeedSoCClass {
bool (*boot_from_emmc)(AspeedSoCState *s);
};
-const char *aspeed_soc_cpu_type(AspeedSoCClass *sc);
-
enum {
ASPEED_DEV_VBOOTROM,
ASPEED_DEV_SPI_BOOT,
@@ -304,6 +302,7 @@ enum {
ASPEED_DEV_IPC1,
};
+const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types);
qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev);
bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp);
void aspeed_soc_uart_set_chr(SerialMM *uart, int dev, int uarts_base,
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index c446e70b24..dab012aa95 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -211,7 +211,8 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
/* AST1030 CPU Core */
armv7m = DEVICE(&a->armv7m);
qdev_prop_set_uint32(armv7m, "num-irq", 256);
- qdev_prop_set_string(armv7m, "cpu-type", aspeed_soc_cpu_type(sc));
+ qdev_prop_set_string(armv7m, "cpu-type",
+ aspeed_soc_cpu_type(sc->valid_cpu_types));
qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
object_property_set_link(OBJECT(&a->armv7m), "memory",
OBJECT(s->memory), &error_abort);
diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c
index c7b0f21887..53c2a5156d 100644
--- a/hw/arm/aspeed_ast2400.c
+++ b/hw/arm/aspeed_ast2400.c
@@ -157,7 +157,7 @@ static void aspeed_ast2400_soc_init(Object *obj)
for (i = 0; i < sc->num_cpus; i++) {
object_initialize_child(obj, "cpu[*]", &a->cpu[i],
- aspeed_soc_cpu_type(sc));
+ aspeed_soc_cpu_type(sc->valid_cpu_types));
}
snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index 03e5df96bb..0299d97929 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -167,7 +167,7 @@ static void aspeed_soc_ast2600_init(Object *obj)
for (i = 0; i < sc->num_cpus; i++) {
object_initialize_child(obj, "cpu[*]", &a->cpu[i],
- aspeed_soc_cpu_type(sc));
+ aspeed_soc_cpu_type(sc->valid_cpu_types));
}
snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
index 80ec5996c1..490e98b924 100644
--- a/hw/arm/aspeed_ast27x0-ssp.c
+++ b/hw/arm/aspeed_ast27x0-ssp.c
@@ -174,7 +174,8 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
/* AST27X0 SSP Core */
armv7m = DEVICE(&a->armv7m);
qdev_prop_set_uint32(armv7m, "num-irq", 256);
- qdev_prop_set_string(armv7m, "cpu-type", aspeed_soc_cpu_type(sc));
+ qdev_prop_set_string(armv7m, "cpu-type",
+ aspeed_soc_cpu_type(sc->valid_cpu_types));
qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
object_property_set_link(OBJECT(&a->armv7m), "memory",
OBJECT(s->memory), &error_abort);
diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c
index 4e0efaef07..d83f90ef00 100644
--- a/hw/arm/aspeed_ast27x0-tsp.c
+++ b/hw/arm/aspeed_ast27x0-tsp.c
@@ -174,7 +174,8 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
/* AST27X0 TSP Core */
armv7m = DEVICE(&a->armv7m);
qdev_prop_set_uint32(armv7m, "num-irq", 256);
- qdev_prop_set_string(armv7m, "cpu-type", aspeed_soc_cpu_type(sc));
+ qdev_prop_set_string(armv7m, "cpu-type",
+ aspeed_soc_cpu_type(sc->valid_cpu_types));
qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
object_property_set_link(OBJECT(&a->armv7m), "memory",
OBJECT(s->memory), &error_abort);
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 853339119f..2f018e9e58 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -436,7 +436,7 @@ static void aspeed_soc_ast2700_init(Object *obj)
for (i = 0; i < sc->num_cpus; i++) {
object_initialize_child(obj, "cpu[*]", &a->cpu[i],
- aspeed_soc_cpu_type(sc));
+ aspeed_soc_cpu_type(sc->valid_cpu_types));
}
object_initialize_child(obj, "gic", &a->gic, gicv3_class_name());
diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c
index ddcbba0020..16c7c4bb78 100644
--- a/hw/arm/aspeed_soc_common.c
+++ b/hw/arm/aspeed_soc_common.c
@@ -22,12 +22,12 @@
#include "qemu/datadir.h"
-const char *aspeed_soc_cpu_type(AspeedSoCClass *sc)
+const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types)
{
- assert(sc->valid_cpu_types);
- assert(sc->valid_cpu_types[0]);
- assert(!sc->valid_cpu_types[1]);
- return sc->valid_cpu_types[0];
+ assert(valid_cpu_types);
+ assert(valid_cpu_types[0]);
+ assert(!valid_cpu_types[1]);
+ return valid_cpu_types[0];
}
qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v1 05/16] hw/arm/aspeed: Remove AspeedSoCState dependency from aspeed_mmio_map() API
2025-10-08 3:21 [PATCH v1 00/16] Introduce AspeedCoprocessor class and base implementation Jamin Lin via
` (3 preceding siblings ...)
2025-10-08 3:21 ` [PATCH v1 04/16] hw/arm/aspeed: Remove AspeedSoCClass dependency from aspeed_soc_cpu_type() API Jamin Lin via
@ 2025-10-08 3:21 ` Jamin Lin via
2025-10-08 3:21 ` [PATCH v1 06/16] hw/arm/aspeed: Remove AspeedSoCState dependency from aspeed_mmio_map_unimplemented() API Jamin Lin via
` (10 subsequent siblings)
15 siblings, 0 replies; 19+ messages in thread
From: Jamin Lin via @ 2025-10-08 3:21 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
Refactor aspeed_mmio_map() to take MemoryRegion * instead of
AspeedSoCState *, making the MMIO mapping helper more generic and
decoupled from SoC state.
Update all call sites to pass s->memory (or equivalent) explicitly.
Touched files include: headers, aspeed_soc_common.c, and SoC realize
paths in AST10x0/2400/2600/27x0 (SSP/TSP) and AST2700.
This reduces coupling, improves reuse across variants, and clarifies the
API boundary between SoC state and memory mapping.
No functional change.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/arm/aspeed_soc.h | 3 +-
hw/arm/aspeed_ast10x0.c | 37 ++++++++++++---------
hw/arm/aspeed_ast2400.c | 47 +++++++++++++++------------
hw/arm/aspeed_ast2600.c | 65 +++++++++++++++++++++----------------
hw/arm/aspeed_ast27x0-ssp.c | 7 ++--
hw/arm/aspeed_ast27x0-tsp.c | 7 ++--
hw/arm/aspeed_ast27x0.c | 60 +++++++++++++++++++---------------
hw/arm/aspeed_soc_common.c | 8 ++---
8 files changed, 133 insertions(+), 101 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 385b657b50..606cf6bb61 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -308,7 +308,8 @@ bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp);
void aspeed_soc_uart_set_chr(SerialMM *uart, int dev, int uarts_base,
int uarts_num, Chardev *chr);
bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp);
-void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr);
+void aspeed_mmio_map(MemoryRegion *memory, SysBusDevice *dev, int n,
+ hwaddr addr);
void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
const char *name, hwaddr addr,
uint64_t size);
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index dab012aa95..caa9feb667 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -242,7 +242,8 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->scu), 0,
+ sc->memmap[ASPEED_DEV_SCU]);
/* I2C */
@@ -251,7 +252,8 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->i2c), 0,
+ sc->memmap[ASPEED_DEV_I2C]);
for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
qemu_irq irq = qdev_get_gpio_in(DEVICE(&a->armv7m),
sc->irqmap[ASPEED_DEV_I2C] + i);
@@ -263,7 +265,8 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]);
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->i3c), 0,
+ sc->memmap[ASPEED_DEV_I3C]);
for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) {
qemu_irq irq = qdev_get_gpio_in(DEVICE(&a->armv7m),
sc->irqmap[ASPEED_DEV_I3C] + i);
@@ -275,7 +278,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->peci), 0,
sc->memmap[ASPEED_DEV_PECI]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_PECI));
@@ -284,7 +287,8 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]);
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->lpc), 0,
+ sc->memmap[ASPEED_DEV_LPC]);
/* Connect the LPC IRQ to the GIC. It is otherwise unused. */
sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0,
@@ -320,7 +324,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->timerctrl), 0,
sc->memmap[ASPEED_DEV_TIMER1]);
for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i);
@@ -331,7 +335,8 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]);
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->adc), 0,
+ sc->memmap[ASPEED_DEV_ADC]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
@@ -341,8 +346,9 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]);
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fmc), 0,
+ sc->memmap[ASPEED_DEV_FMC]);
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fmc), 1,
ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_FMC));
@@ -354,9 +360,9 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 0,
sc->memmap[ASPEED_DEV_SPI1 + i]);
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 1,
ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base);
}
@@ -364,7 +370,8 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]);
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sbc), 0,
+ sc->memmap[ASPEED_DEV_SBC]);
/* HACE */
object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(&s->sram),
@@ -372,7 +379,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->hace), 0,
sc->memmap[ASPEED_DEV_HACE]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
@@ -387,14 +394,14 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset);
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset);
}
/* GPIO */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->gpio), 0,
sc->memmap[ASPEED_DEV_GPIO]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_GPIO));
diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c
index 53c2a5156d..6690752215 100644
--- a/hw/arm/aspeed_ast2400.c
+++ b/hw/arm/aspeed_ast2400.c
@@ -289,13 +289,15 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->scu), 0,
+ sc->memmap[ASPEED_DEV_SCU]);
/* VIC */
if (!sysbus_realize(SYS_BUS_DEVICE(&a->vic), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->vic), 0, sc->memmap[ASPEED_DEV_VIC]);
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->vic), 0,
+ sc->memmap[ASPEED_DEV_VIC]);
sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 0,
qdev_get_gpio_in(DEVICE(&a->cpu), ARM_CPU_IRQ));
sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 1,
@@ -305,7 +307,8 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]);
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->rtc), 0,
+ sc->memmap[ASPEED_DEV_RTC]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_RTC));
@@ -315,7 +318,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->timerctrl), 0,
sc->memmap[ASPEED_DEV_TIMER1]);
for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i);
@@ -326,7 +329,8 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]);
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->adc), 0,
+ sc->memmap[ASPEED_DEV_ADC]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
@@ -341,7 +345,8 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->i2c), 0,
+ sc->memmap[ASPEED_DEV_I2C]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_I2C));
@@ -349,7 +354,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->peci), 0,
sc->memmap[ASPEED_DEV_PECI]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_PECI));
@@ -360,8 +365,9 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]);
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fmc), 0,
+ sc->memmap[ASPEED_DEV_FMC]);
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fmc), 1,
ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_FMC));
@@ -377,9 +383,9 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 0,
sc->memmap[ASPEED_DEV_SPI1 + i]);
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 1,
ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base);
}
@@ -388,7 +394,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->ehci[i]), 0,
sc->memmap[ASPEED_DEV_EHCI1 + i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i));
@@ -398,7 +404,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sdmc), 0,
sc->memmap[ASPEED_DEV_SDMC]);
/* Watch dog */
@@ -411,7 +417,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset);
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset);
}
/* RAM */
@@ -426,7 +432,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
sc->memmap[ASPEED_DEV_ETH1 + i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i));
@@ -436,7 +442,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->xdma), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->xdma), 0,
sc->memmap[ASPEED_DEV_XDMA]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_XDMA));
@@ -445,7 +451,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->gpio), 0,
sc->memmap[ASPEED_DEV_GPIO]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_GPIO));
@@ -454,7 +460,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sdhci), 0,
sc->memmap[ASPEED_DEV_SDHCI]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI));
@@ -463,7 +469,8 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]);
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->lpc), 0,
+ sc->memmap[ASPEED_DEV_LPC]);
/* Connect the LPC IRQ to the VIC */
sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0,
@@ -496,7 +503,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->hace), 0,
sc->memmap[ASPEED_DEV_HACE]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index 0299d97929..bf0ecde051 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -324,7 +324,7 @@ static bool aspeed_soc_ast2600_pcie_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie_phy[0]), errp)) {
return false;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->pcie_phy[0]), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->pcie_phy[0]), 0,
sc->memmap[ASPEED_DEV_PCIE_PHY1]);
object_property_set_int(OBJECT(&s->pcie[0]), "dram-base",
@@ -335,7 +335,7 @@ static bool aspeed_soc_ast2600_pcie_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie[0]), errp)) {
return false;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->pcie[0]), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->pcie[0]), 0,
sc->memmap[ASPEED_DEV_PCIE0]);
irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore),
@@ -414,7 +414,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&a->a7mpcore), &error_abort);
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->a7mpcore), 0, ASPEED_A7MPCORE_ADDR);
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->a7mpcore), 0,
+ ASPEED_A7MPCORE_ADDR);
for (i = 0; i < sc->num_cpus; i++) {
SysBusDevice *sbd = SYS_BUS_DEVICE(&a->a7mpcore);
@@ -448,13 +449,15 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->scu), 0,
+ sc->memmap[ASPEED_DEV_SCU]);
/* RTC */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]);
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->rtc), 0,
+ sc->memmap[ASPEED_DEV_RTC]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_RTC));
@@ -464,7 +467,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->timerctrl), 0,
sc->memmap[ASPEED_DEV_TIMER1]);
for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i);
@@ -475,7 +478,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]);
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->adc), 0,
+ sc->memmap[ASPEED_DEV_ADC]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
@@ -490,7 +494,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->i2c), 0,
+ sc->memmap[ASPEED_DEV_I2C]);
for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore),
sc->irqmap[ASPEED_DEV_I2C] + i);
@@ -502,7 +507,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->peci), 0,
sc->memmap[ASPEED_DEV_PECI]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_PECI));
@@ -518,8 +523,9 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]);
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fmc), 0,
+ sc->memmap[ASPEED_DEV_FMC]);
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fmc), 1,
ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_FMC));
@@ -537,9 +543,9 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 0,
sc->memmap[ASPEED_DEV_SPI1 + i]);
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 1,
ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base);
}
@@ -548,7 +554,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->ehci[i]), 0,
sc->memmap[ASPEED_DEV_EHCI1 + i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i));
@@ -558,7 +564,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sdmc), 0,
sc->memmap[ASPEED_DEV_SDMC]);
/* Watch dog */
@@ -571,7 +577,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset);
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset);
}
/* RAM */
@@ -586,7 +592,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
sc->memmap[ASPEED_DEV_ETH1 + i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i));
@@ -597,7 +603,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->mii[i]), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->mii[i]), 0,
sc->memmap[ASPEED_DEV_MII1 + i]);
}
@@ -605,7 +611,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->xdma), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->xdma), 0,
sc->memmap[ASPEED_DEV_XDMA]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_XDMA));
@@ -614,7 +620,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->gpio), 0,
sc->memmap[ASPEED_DEV_GPIO]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_GPIO));
@@ -622,7 +628,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio_1_8v), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio_1_8v), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->gpio_1_8v), 0,
sc->memmap[ASPEED_DEV_GPIO_1_8V]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_GPIO_1_8V));
@@ -631,7 +637,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sdhci), 0,
sc->memmap[ASPEED_DEV_SDHCI]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI));
@@ -640,7 +646,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->emmc), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->emmc), 0,
sc->memmap[ASPEED_DEV_EMMC]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_EMMC));
@@ -649,7 +655,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]);
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->lpc), 0,
+ sc->memmap[ASPEED_DEV_LPC]);
/* Connect the LPC IRQ to the GIC. It is otherwise unused. */
sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0,
@@ -685,7 +692,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->hace), 0,
sc->memmap[ASPEED_DEV_HACE]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
@@ -694,7 +701,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]);
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->i3c), 0,
+ sc->memmap[ASPEED_DEV_I3C]);
for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) {
irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore),
sc->irqmap[ASPEED_DEV_I3C] + i);
@@ -706,14 +714,15 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]);
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sbc), 0,
+ sc->memmap[ASPEED_DEV_SBC]);
/* FSI */
for (i = 0; i < ASPEED_FSI_NUM; i++) {
if (!sysbus_realize(SYS_BUS_DEVICE(&s->fsi[i]), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fsi[i]), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fsi[i]), 0,
sc->memmap[ASPEED_DEV_FSI1 + i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->fsi[i]), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_FSI1 + i));
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
index 490e98b924..83cf3c14b6 100644
--- a/hw/arm/aspeed_ast27x0-ssp.c
+++ b/hw/arm/aspeed_ast27x0-ssp.c
@@ -196,14 +196,15 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->scu), 0,
+ sc->memmap[ASPEED_DEV_SCU]);
/* INTC */
if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[0]), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intc[0]), 0,
sc->memmap[ASPEED_DEV_INTC]);
/* INTCIO */
@@ -211,7 +212,7 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[1]), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intc[1]), 0,
sc->memmap[ASPEED_DEV_INTCIO]);
/* irq source orgates -> INTC0 */
diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c
index d83f90ef00..86aa565608 100644
--- a/hw/arm/aspeed_ast27x0-tsp.c
+++ b/hw/arm/aspeed_ast27x0-tsp.c
@@ -196,14 +196,15 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->scu), 0,
+ sc->memmap[ASPEED_DEV_SCU]);
/* INTC */
if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[0]), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intc[0]), 0,
sc->memmap[ASPEED_DEV_INTC]);
/* INTCIO */
@@ -211,7 +212,7 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[1]), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intc[1]), 0,
sc->memmap[ASPEED_DEV_INTCIO]);
/* irq source orgates -> INTC */
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 2f018e9e58..8db67dc806 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -589,9 +589,9 @@ static bool aspeed_soc_ast2700_gic_realize(DeviceState *dev, Error **errp)
return false;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->gic), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->gic), 0,
sc->memmap[ASPEED_GIC_DIST]);
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->gic), 1,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->gic), 1,
sc->memmap[ASPEED_GIC_REDIST]);
for (i = 0; i < sc->num_cpus; i++) {
@@ -647,7 +647,7 @@ static bool aspeed_soc_ast2700_pcie_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie_phy[i]), errp)) {
return false;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->pcie_phy[i]), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->pcie_phy[i]), 0,
sc->memmap[ASPEED_DEV_PCIE_PHY0 + i]);
object_property_set_int(OBJECT(&s->pcie[i]), "dram-base",
@@ -658,7 +658,7 @@ static bool aspeed_soc_ast2700_pcie_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie[i]), errp)) {
return false;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->pcie[i]), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->pcie[i]), 0,
sc->memmap[ASPEED_DEV_PCIE0 + i]);
irq = aspeed_soc_get_irq(s, ASPEED_DEV_PCIE0 + i);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie[i].rc), 0, irq);
@@ -719,7 +719,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[0]), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intc[0]), 0,
sc->memmap[ASPEED_DEV_INTC]);
/* INTCIO */
@@ -727,7 +727,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[1]), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intc[1]), 0,
sc->memmap[ASPEED_DEV_INTCIO]);
/* irq sources -> orgates -> INTC */
@@ -777,13 +777,14 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->scu), 0,
+ sc->memmap[ASPEED_DEV_SCU]);
/* SCU1 */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scuio), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scuio), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->scuio), 0,
sc->memmap[ASPEED_DEV_SCUIO]);
/* UART */
@@ -800,8 +801,9 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]);
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fmc), 0,
+ sc->memmap[ASPEED_DEV_FMC]);
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fmc), 1,
ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_FMC));
@@ -819,9 +821,9 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 0,
sc->memmap[ASPEED_DEV_SPI0 + i]);
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 1,
ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base);
}
@@ -830,7 +832,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->ehci[i]), 0,
sc->memmap[ASPEED_DEV_EHCI1 + i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i));
@@ -848,7 +850,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sdmc), 0,
sc->memmap[ASPEED_DEV_SDMC]);
/* RAM */
@@ -865,7 +867,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
sc->memmap[ASPEED_DEV_ETH1 + i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i));
@@ -876,7 +878,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->mii[i]), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->mii[i]), 0,
sc->memmap[ASPEED_DEV_MII1 + i]);
}
@@ -890,26 +892,28 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset);
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset);
}
/* SLI */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->sli), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sli), 0, sc->memmap[ASPEED_DEV_SLI]);
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sli), 0,
+ sc->memmap[ASPEED_DEV_SLI]);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->sliio), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sliio), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sliio), 0,
sc->memmap[ASPEED_DEV_SLIIO]);
/* ADC */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]);
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->adc), 0,
+ sc->memmap[ASPEED_DEV_ADC]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
@@ -919,7 +923,8 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->i2c), 0,
+ sc->memmap[ASPEED_DEV_I2C]);
for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
/*
* The AST2700 I2C controller has one source INTC per bus.
@@ -948,7 +953,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->gpio), 0,
sc->memmap[ASPEED_DEV_GPIO]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_GPIO));
@@ -957,7 +962,8 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]);
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->rtc), 0,
+ sc->memmap[ASPEED_DEV_RTC]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_RTC));
@@ -965,7 +971,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sdhci), 0,
sc->memmap[ASPEED_DEV_SDHCI]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI));
@@ -974,7 +980,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->emmc), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->emmc), 0,
sc->memmap[ASPEED_DEV_EMMC]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_EMMC));
@@ -985,7 +991,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->timerctrl), 0,
sc->memmap[ASPEED_DEV_TIMER1]);
for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i);
@@ -998,7 +1004,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0,
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->hace), 0,
sc->memmap[ASPEED_DEV_HACE]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c
index 16c7c4bb78..ca4e589dce 100644
--- a/hw/arm/aspeed_soc_common.c
+++ b/hw/arm/aspeed_soc_common.c
@@ -53,7 +53,7 @@ bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp)
}
sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, aspeed_soc_get_irq(s, uart));
- aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]);
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]);
}
return true;
@@ -111,10 +111,10 @@ bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp)
return true;
}
-void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr)
+void aspeed_mmio_map(MemoryRegion *memory, SysBusDevice *dev, int n,
+ hwaddr addr)
{
- memory_region_add_subregion(s->memory, addr,
- sysbus_mmio_get_region(dev, n));
+ memory_region_add_subregion(memory, addr, sysbus_mmio_get_region(dev, n));
}
void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v1 06/16] hw/arm/aspeed: Remove AspeedSoCState dependency from aspeed_mmio_map_unimplemented() API
2025-10-08 3:21 [PATCH v1 00/16] Introduce AspeedCoprocessor class and base implementation Jamin Lin via
` (4 preceding siblings ...)
2025-10-08 3:21 ` [PATCH v1 05/16] hw/arm/aspeed: Remove AspeedSoCState dependency from aspeed_mmio_map() API Jamin Lin via
@ 2025-10-08 3:21 ` Jamin Lin via
2025-10-08 3:21 ` [PATCH v1 07/16] hw/arm/aspeed: Remove AspeedSoCState dependency from aspeed_soc_get_irq() API Jamin Lin via
` (9 subsequent siblings)
15 siblings, 0 replies; 19+ messages in thread
From: Jamin Lin via @ 2025-10-08 3:21 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
Refactor aspeed_mmio_map_unimplemented() to take MemoryRegion *
instead of AspeedSoCState *, removing its dependency on SoC state and
aligning it with the updated aspeed_mmio_map() interface.
All related call sites are updated to explicitly pass s->memory.
Affected files include headers, aspeed_soc_common.c, and SoC realize
functions in AST10x0, AST2400, AST2600, AST27x0 (SSP/TSP), and AST2700.
This change simplifies the MMIO mapping helpers, improves API
consistency, and reduces coupling between SoC logic and memory
operations.
No functional change.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/arm/aspeed_soc.h | 2 +-
hw/arm/aspeed_ast10x0.c | 24 ++++++++++++++++--------
hw/arm/aspeed_ast2400.c | 6 ++++--
hw/arm/aspeed_ast2600.c | 12 ++++++++----
hw/arm/aspeed_ast27x0-ssp.c | 8 ++++----
hw/arm/aspeed_ast27x0-tsp.c | 8 ++++----
hw/arm/aspeed_ast27x0.c | 10 +++++-----
hw/arm/aspeed_soc_common.c | 4 ++--
8 files changed, 44 insertions(+), 30 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 606cf6bb61..957362b88d 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -310,7 +310,7 @@ void aspeed_soc_uart_set_chr(SerialMM *uart, int dev, int uarts_base,
bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp);
void aspeed_mmio_map(MemoryRegion *memory, SysBusDevice *dev, int n,
hwaddr addr);
-void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
+void aspeed_mmio_map_unimplemented(MemoryRegion *memory, SysBusDevice *dev,
const char *name, hwaddr addr,
uint64_t size);
void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index caa9feb667..e861b6dad6 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -201,10 +201,12 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
}
/* General I/O memory space to catch all unimplemented device */
- aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io",
+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->iomem),
+ "aspeed.io",
sc->memmap[ASPEED_DEV_IOMEM],
ASPEED_SOC_IOMEM_SIZE);
- aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->sbc_unimplemented),
+ aspeed_mmio_map_unimplemented(s->memory,
+ SYS_BUS_DEVICE(&s->sbc_unimplemented),
"aspeed.sbc", sc->memmap[ASPEED_DEV_SBC],
0x40000);
@@ -406,20 +408,26 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_GPIO));
- aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->pwm), "aspeed.pwm",
+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->pwm),
+ "aspeed.pwm",
sc->memmap[ASPEED_DEV_PWM], 0x100);
- aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->espi), "aspeed.espi",
+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->espi),
+ "aspeed.espi",
sc->memmap[ASPEED_DEV_ESPI], 0x800);
- aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->udc), "aspeed.udc",
+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->udc),
+ "aspeed.udc",
sc->memmap[ASPEED_DEV_UDC], 0x1000);
- aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->sgpiom), "aspeed.sgpiom",
+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->sgpiom),
+ "aspeed.sgpiom",
sc->memmap[ASPEED_DEV_SGPIOM], 0x100);
- aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->jtag[0]), "aspeed.jtag",
+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->jtag[0]),
+ "aspeed.jtag",
sc->memmap[ASPEED_DEV_JTAG0], 0x20);
- aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->jtag[1]), "aspeed.jtag",
+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->jtag[1]),
+ "aspeed.jtag",
sc->memmap[ASPEED_DEV_JTAG1], 0x20);
}
diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c
index 6690752215..e0604851a5 100644
--- a/hw/arm/aspeed_ast2400.c
+++ b/hw/arm/aspeed_ast2400.c
@@ -259,12 +259,14 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
&s->spi_boot_container);
/* IO space */
- aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io",
+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->iomem),
+ "aspeed.io",
sc->memmap[ASPEED_DEV_IOMEM],
ASPEED_SOC_IOMEM_SIZE);
/* Video engine stub */
- aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->video), "aspeed.video",
+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->video),
+ "aspeed.video",
sc->memmap[ASPEED_DEV_VIDEO], 0x1000);
/* CPU */
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index bf0ecde051..ed0985a16e 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -370,16 +370,19 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
&s->spi_boot_container);
/* IO space */
- aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io",
+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->iomem),
+ "aspeed.io",
sc->memmap[ASPEED_DEV_IOMEM],
ASPEED_SOC_IOMEM_SIZE);
/* Video engine stub */
- aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->video), "aspeed.video",
+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->video),
+ "aspeed.video",
sc->memmap[ASPEED_DEV_VIDEO], 0x1000);
/* eMMC Boot Controller stub */
- aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->emmc_boot_controller),
+ aspeed_mmio_map_unimplemented(s->memory,
+ SYS_BUS_DEVICE(&s->emmc_boot_controller),
"aspeed.emmc-boot-controller",
sc->memmap[ASPEED_DEV_EMMC_BC], 0x1000);
@@ -441,7 +444,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
sc->memmap[ASPEED_DEV_SRAM], &s->sram);
/* DPMCU */
- aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->dpmcu), "aspeed.dpmcu",
+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu),
+ "aspeed.dpmcu",
sc->memmap[ASPEED_DEV_DPMCU],
ASPEED_SOC_DPMCU_SIZE);
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
index 83cf3c14b6..99a3de15b5 100644
--- a/hw/arm/aspeed_ast27x0-ssp.c
+++ b/hw/arm/aspeed_ast27x0-ssp.c
@@ -241,16 +241,16 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
return;
}
- aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->timerctrl),
+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->timerctrl),
"aspeed.timerctrl",
sc->memmap[ASPEED_DEV_TIMER1], 0x200);
- aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&a->ipc[0]),
+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->ipc[0]),
"aspeed.ipc0",
sc->memmap[ASPEED_DEV_IPC0], 0x1000);
- aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&a->ipc[1]),
+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->ipc[1]),
"aspeed.ipc1",
sc->memmap[ASPEED_DEV_IPC1], 0x1000);
- aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&a->scuio),
+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->scuio),
"aspeed.scuio",
sc->memmap[ASPEED_DEV_SCUIO], 0x1000);
}
diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c
index 86aa565608..568d7555e2 100644
--- a/hw/arm/aspeed_ast27x0-tsp.c
+++ b/hw/arm/aspeed_ast27x0-tsp.c
@@ -241,16 +241,16 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
return;
}
- aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->timerctrl),
+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->timerctrl),
"aspeed.timerctrl",
sc->memmap[ASPEED_DEV_TIMER1], 0x200);
- aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&a->ipc[0]),
+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->ipc[0]),
"aspeed.ipc0",
sc->memmap[ASPEED_DEV_IPC0], 0x1000);
- aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&a->ipc[1]),
+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->ipc[1]),
"aspeed.ipc1",
sc->memmap[ASPEED_DEV_IPC1], 0x1000);
- aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&a->scuio),
+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->scuio),
"aspeed.scuio",
sc->memmap[ASPEED_DEV_SCUIO], 0x1000);
}
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 8db67dc806..9b645c6c55 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -1014,23 +1014,23 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
return;
}
- aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->dpmcu),
+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu),
"aspeed.dpmcu",
sc->memmap[ASPEED_DEV_DPMCU],
AST2700_SOC_DPMCU_SIZE);
- aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->ltpi),
+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->ltpi),
"aspeed.ltpi",
sc->memmap[ASPEED_DEV_LTPI],
AST2700_SOC_LTPI_SIZE);
- aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem),
+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->iomem),
"aspeed.io",
sc->memmap[ASPEED_DEV_IOMEM],
AST2700_SOC_IO_SIZE);
- aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem0),
+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->iomem0),
"aspeed.iomem0",
sc->memmap[ASPEED_DEV_IOMEM0],
AST2700_SOC_IOMEM_SIZE);
- aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem1),
+ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->iomem1),
"aspeed.iomem1",
sc->memmap[ASPEED_DEV_IOMEM1],
AST2700_SOC_IOMEM_SIZE);
diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c
index ca4e589dce..e7d0a9c290 100644
--- a/hw/arm/aspeed_soc_common.c
+++ b/hw/arm/aspeed_soc_common.c
@@ -117,14 +117,14 @@ void aspeed_mmio_map(MemoryRegion *memory, SysBusDevice *dev, int n,
memory_region_add_subregion(memory, addr, sysbus_mmio_get_region(dev, n));
}
-void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
+void aspeed_mmio_map_unimplemented(MemoryRegion *memory, SysBusDevice *dev,
const char *name, hwaddr addr, uint64_t size)
{
qdev_prop_set_string(DEVICE(dev), "name", name);
qdev_prop_set_uint64(DEVICE(dev), "size", size);
sysbus_realize(dev, &error_abort);
- memory_region_add_subregion_overlap(s->memory, addr,
+ memory_region_add_subregion_overlap(memory, addr,
sysbus_mmio_get_region(dev, 0), -1000);
}
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v1 07/16] hw/arm/aspeed: Remove AspeedSoCState dependency from aspeed_soc_get_irq() API
2025-10-08 3:21 [PATCH v1 00/16] Introduce AspeedCoprocessor class and base implementation Jamin Lin via
` (5 preceding siblings ...)
2025-10-08 3:21 ` [PATCH v1 06/16] hw/arm/aspeed: Remove AspeedSoCState dependency from aspeed_mmio_map_unimplemented() API Jamin Lin via
@ 2025-10-08 3:21 ` Jamin Lin via
2025-10-08 3:21 ` [PATCH v1 08/16] hw/arm/aspeed: Remove AspeedSoCState dependency from aspeed_soc_uart_realize() API Jamin Lin via
` (8 subsequent siblings)
15 siblings, 0 replies; 19+ messages in thread
From: Jamin Lin via @ 2025-10-08 3:21 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
Refactor IRQ helper to decouple from SoC state. The public
aspeed_soc_get_irq() now takes a function pointer and opaque context
(qemu_irq (*fn)(void *ctx, int dev), void *ctx, int dev) instead of an
AspeedSoCState *.
Update AspeedSoCClass::get_irq signature to (void *ctx, int dev) and
convert all SoC-specific implementations (AST1030/2400/2600/27x0 SSP/TSP
and AST2700) to accept void *ctx.
Adjust all call sites to pass sc->get_irq and s explicitly, and wire
through in aspeed_soc_uart_realize() and relevant realize paths.
This change removes a hard dependency on AspeedSoCState, enabling reuse
from other classes and simplifying future refactors.
No functional change.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/arm/aspeed_soc.h | 5 +++--
hw/arm/aspeed_ast10x0.c | 18 ++++++++++--------
hw/arm/aspeed_ast2400.c | 32 ++++++++++++++++++--------------
hw/arm/aspeed_ast2600.c | 37 +++++++++++++++++++++----------------
hw/arm/aspeed_ast27x0-ssp.c | 3 ++-
hw/arm/aspeed_ast27x0-tsp.c | 3 ++-
hw/arm/aspeed_ast27x0.c | 27 +++++++++++++++------------
hw/arm/aspeed_soc_common.c | 8 +++++---
8 files changed, 76 insertions(+), 57 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 957362b88d..427708c087 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -198,7 +198,7 @@ struct AspeedSoCClass {
const int *irqmap;
const hwaddr *memmap;
uint32_t num_cpus;
- qemu_irq (*get_irq)(AspeedSoCState *s, int dev);
+ qemu_irq (*get_irq)(void *ctx, int dev);
bool (*boot_from_emmc)(AspeedSoCState *s);
};
@@ -303,7 +303,8 @@ enum {
};
const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types);
-qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev);
+qemu_irq aspeed_soc_get_irq(qemu_irq (*fn)(void *ctx, int dev),
+ void *ctx, int dev);
bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp);
void aspeed_soc_uart_set_chr(SerialMM *uart, int dev, int uarts_base,
int uarts_num, Chardev *chr);
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index e861b6dad6..3ce866c66a 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -99,8 +99,9 @@ static const int aspeed_soc_ast1030_irqmap[] = {
[ASPEED_DEV_JTAG1] = 53,
};
-static qemu_irq aspeed_soc_ast1030_get_irq(AspeedSoCState *s, int dev)
+static qemu_irq aspeed_soc_ast1030_get_irq(void *ctx, int dev)
{
+ AspeedSoCState *s = (AspeedSoCState *)ctx;
Aspeed10x0SoCState *a = ASPEED10X0_SOC(s);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
@@ -283,7 +284,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->peci), 0,
sc->memmap[ASPEED_DEV_PECI]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_PECI));
+ aspeed_soc_get_irq(sc->get_irq, s, ASPEED_DEV_PECI));
/* LPC */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) {
@@ -294,7 +295,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
/* Connect the LPC IRQ to the GIC. It is otherwise unused. */
sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_LPC));
+ aspeed_soc_get_irq(sc->get_irq, s, ASPEED_DEV_LPC));
/*
* On the AST1030 LPC subdevice IRQs are connected straight to the GIC.
@@ -329,7 +330,8 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->timerctrl), 0,
sc->memmap[ASPEED_DEV_TIMER1]);
for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
- qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i);
+ qemu_irq irq = aspeed_soc_get_irq(sc->get_irq, s,
+ ASPEED_DEV_TIMER1 + i);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
}
@@ -340,7 +342,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->adc), 0,
sc->memmap[ASPEED_DEV_ADC]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
+ aspeed_soc_get_irq(sc->get_irq, s, ASPEED_DEV_ADC));
/* FMC, The number of CS is set at the board level */
object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(&s->sram),
@@ -353,7 +355,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fmc), 1,
ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_FMC));
+ aspeed_soc_get_irq(sc->get_irq, s, ASPEED_DEV_FMC));
/* SPI */
for (i = 0; i < sc->spis_num; i++) {
@@ -384,7 +386,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->hace), 0,
sc->memmap[ASPEED_DEV_HACE]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
+ aspeed_soc_get_irq(sc->get_irq, s, ASPEED_DEV_HACE));
/* Watch dog */
for (i = 0; i < sc->wdts_num; i++) {
@@ -406,7 +408,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->gpio), 0,
sc->memmap[ASPEED_DEV_GPIO]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_GPIO));
+ aspeed_soc_get_irq(sc->get_irq, s, ASPEED_DEV_GPIO));
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->pwm),
"aspeed.pwm",
diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c
index e0604851a5..2910c40807 100644
--- a/hw/arm/aspeed_ast2400.c
+++ b/hw/arm/aspeed_ast2400.c
@@ -134,8 +134,9 @@ static const int aspeed_soc_ast2400_irqmap[] = {
#define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
-static qemu_irq aspeed_soc_ast2400_get_irq(AspeedSoCState *s, int dev)
+static qemu_irq aspeed_soc_ast2400_get_irq(void *ctx, int dev)
{
+ AspeedSoCState *s = (AspeedSoCState *)ctx;
Aspeed2400SoCState *a = ASPEED2400_SOC(s);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
@@ -312,7 +313,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->rtc), 0,
sc->memmap[ASPEED_DEV_RTC]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_RTC));
+ aspeed_soc_get_irq(sc->get_irq, s, ASPEED_DEV_RTC));
/* Timer */
object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu),
@@ -323,7 +324,8 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->timerctrl), 0,
sc->memmap[ASPEED_DEV_TIMER1]);
for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
- qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i);
+ qemu_irq irq = aspeed_soc_get_irq(sc->get_irq, s,
+ ASPEED_DEV_TIMER1 + i);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
}
@@ -334,7 +336,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->adc), 0,
sc->memmap[ASPEED_DEV_ADC]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
+ aspeed_soc_get_irq(sc->get_irq, s, ASPEED_DEV_ADC));
/* UART */
if (!aspeed_soc_uart_realize(s, errp)) {
@@ -350,7 +352,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->i2c), 0,
sc->memmap[ASPEED_DEV_I2C]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_I2C));
+ aspeed_soc_get_irq(sc->get_irq, s, ASPEED_DEV_I2C));
/* PECI */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) {
@@ -359,7 +361,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->peci), 0,
sc->memmap[ASPEED_DEV_PECI]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_PECI));
+ aspeed_soc_get_irq(sc->get_irq, s, ASPEED_DEV_PECI));
/* FMC, The number of CS is set at the board level */
object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr),
@@ -372,7 +374,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fmc), 1,
ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_FMC));
+ aspeed_soc_get_irq(sc->get_irq, s, ASPEED_DEV_FMC));
/* Set up an alias on the FMC CE0 region (boot default) */
MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio;
@@ -399,7 +401,8 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->ehci[i]), 0,
sc->memmap[ASPEED_DEV_EHCI1 + i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i));
+ aspeed_soc_get_irq(sc->get_irq, s,
+ ASPEED_DEV_EHCI1 + i));
}
/* SDMC - SDRAM Memory Controller */
@@ -437,7 +440,8 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
sc->memmap[ASPEED_DEV_ETH1 + i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i));
+ aspeed_soc_get_irq(sc->get_irq, s,
+ ASPEED_DEV_ETH1 + i));
}
/* XDMA */
@@ -447,7 +451,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->xdma), 0,
sc->memmap[ASPEED_DEV_XDMA]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_XDMA));
+ aspeed_soc_get_irq(sc->get_irq, s, ASPEED_DEV_XDMA));
/* GPIO */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
@@ -456,7 +460,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->gpio), 0,
sc->memmap[ASPEED_DEV_GPIO]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_GPIO));
+ aspeed_soc_get_irq(sc->get_irq, s, ASPEED_DEV_GPIO));
/* SDHCI */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) {
@@ -465,7 +469,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sdhci), 0,
sc->memmap[ASPEED_DEV_SDHCI]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI));
+ aspeed_soc_get_irq(sc->get_irq, s, ASPEED_DEV_SDHCI));
/* LPC */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) {
@@ -476,7 +480,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
/* Connect the LPC IRQ to the VIC */
sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_LPC));
+ aspeed_soc_get_irq(sc->get_irq, s, ASPEED_DEV_LPC));
/*
* On the AST2400 and AST2500 the one LPC IRQ is shared between all of the
@@ -508,7 +512,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->hace), 0,
sc->memmap[ASPEED_DEV_HACE]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
+ aspeed_soc_get_irq(sc->get_irq, s, ASPEED_DEV_HACE));
}
static void aspeed_soc_ast2400_class_init(ObjectClass *oc, const void *data)
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index ed0985a16e..cd14dc95bb 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -144,8 +144,9 @@ static const int aspeed_soc_ast2600_irqmap[] = {
[ASPEED_DEV_I3C] = 102, /* 102 -> 107 */
};
-static qemu_irq aspeed_soc_ast2600_get_irq(AspeedSoCState *s, int dev)
+static qemu_irq aspeed_soc_ast2600_get_irq(void *ctx, int dev)
{
+ AspeedSoCState *s = (AspeedSoCState *)ctx;
Aspeed2600SoCState *a = ASPEED2600_SOC(s);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
@@ -463,7 +464,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->rtc), 0,
sc->memmap[ASPEED_DEV_RTC]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_RTC));
+ aspeed_soc_get_irq(sc->get_irq, s, ASPEED_DEV_RTC));
/* Timer */
object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu),
@@ -474,7 +475,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->timerctrl), 0,
sc->memmap[ASPEED_DEV_TIMER1]);
for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
- irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i);
+ irq = aspeed_soc_get_irq(sc->get_irq, s, ASPEED_DEV_TIMER1 + i);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
}
@@ -485,7 +486,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->adc), 0,
sc->memmap[ASPEED_DEV_ADC]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
+ aspeed_soc_get_irq(sc->get_irq, s, ASPEED_DEV_ADC));
/* UART */
if (!aspeed_soc_uart_realize(s, errp)) {
@@ -514,7 +515,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->peci), 0,
sc->memmap[ASPEED_DEV_PECI]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_PECI));
+ aspeed_soc_get_irq(sc->get_irq, s, ASPEED_DEV_PECI));
/* PCIe Root Complex (RC) */
if (!aspeed_soc_ast2600_pcie_realize(dev, errp)) {
@@ -532,7 +533,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fmc), 1,
ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_FMC));
+ aspeed_soc_get_irq(sc->get_irq, s, ASPEED_DEV_FMC));
/* Set up an alias on the FMC CE0 region (boot default) */
MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio;
@@ -561,7 +562,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->ehci[i]), 0,
sc->memmap[ASPEED_DEV_EHCI1 + i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i));
+ aspeed_soc_get_irq(sc->get_irq, s,
+ ASPEED_DEV_EHCI1 + i));
}
/* SDMC - SDRAM Memory Controller */
@@ -599,7 +601,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
sc->memmap[ASPEED_DEV_ETH1 + i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i));
+ aspeed_soc_get_irq(sc->get_irq, s,
+ ASPEED_DEV_ETH1 + i));
object_property_set_link(OBJECT(&s->mii[i]), "nic",
OBJECT(&s->ftgmac100[i]), &error_abort);
@@ -618,7 +621,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->xdma), 0,
sc->memmap[ASPEED_DEV_XDMA]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_XDMA));
+ aspeed_soc_get_irq(sc->get_irq, s, ASPEED_DEV_XDMA));
/* GPIO */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
@@ -627,7 +630,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->gpio), 0,
sc->memmap[ASPEED_DEV_GPIO]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_GPIO));
+ aspeed_soc_get_irq(sc->get_irq, s, ASPEED_DEV_GPIO));
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio_1_8v), errp)) {
return;
@@ -635,7 +638,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->gpio_1_8v), 0,
sc->memmap[ASPEED_DEV_GPIO_1_8V]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_GPIO_1_8V));
+ aspeed_soc_get_irq(sc->get_irq, s,
+ ASPEED_DEV_GPIO_1_8V));
/* SDHCI */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) {
@@ -644,7 +648,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sdhci), 0,
sc->memmap[ASPEED_DEV_SDHCI]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI));
+ aspeed_soc_get_irq(sc->get_irq, s, ASPEED_DEV_SDHCI));
/* eMMC */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) {
@@ -653,7 +657,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->emmc), 0,
sc->memmap[ASPEED_DEV_EMMC]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_EMMC));
+ aspeed_soc_get_irq(sc->get_irq, s, ASPEED_DEV_EMMC));
/* LPC */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) {
@@ -664,7 +668,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
/* Connect the LPC IRQ to the GIC. It is otherwise unused. */
sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_LPC));
+ aspeed_soc_get_irq(sc->get_irq, s, ASPEED_DEV_LPC));
/*
* On the AST2600 LPC subdevice IRQs are connected straight to the GIC.
@@ -699,7 +703,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->hace), 0,
sc->memmap[ASPEED_DEV_HACE]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
+ aspeed_soc_get_irq(sc->get_irq, s, ASPEED_DEV_HACE));
/* I3C */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) {
@@ -729,7 +733,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fsi[i]), 0,
sc->memmap[ASPEED_DEV_FSI1 + i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->fsi[i]), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_FSI1 + i));
+ aspeed_soc_get_irq(sc->get_irq, s,
+ ASPEED_DEV_FSI1 + i));
}
}
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
index 99a3de15b5..e63a4b3ad3 100644
--- a/hw/arm/aspeed_ast27x0-ssp.c
+++ b/hw/arm/aspeed_ast27x0-ssp.c
@@ -104,8 +104,9 @@ static struct nvic_intc_irq_info ast2700_ssp_intcmap[] = {
{136, 0, 9, NULL},
};
-static qemu_irq aspeed_soc_ast27x0ssp_get_irq(AspeedSoCState *s, int dev)
+static qemu_irq aspeed_soc_ast27x0ssp_get_irq(void *ctx, int dev)
{
+ AspeedSoCState *s = (AspeedSoCState *)ctx;
Aspeed27x0SSPSoCState *a = ASPEED27X0SSP_SOC(s);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c
index 568d7555e2..9537ce121c 100644
--- a/hw/arm/aspeed_ast27x0-tsp.c
+++ b/hw/arm/aspeed_ast27x0-tsp.c
@@ -104,8 +104,9 @@ static struct nvic_intc_irq_info ast2700_tsp_intcmap[] = {
{136, 0, 9, NULL},
};
-static qemu_irq aspeed_soc_ast27x0tsp_get_irq(AspeedSoCState *s, int dev)
+static qemu_irq aspeed_soc_ast27x0tsp_get_irq(void *ctx, int dev)
{
+ AspeedSoCState *s = (AspeedSoCState *)ctx;
Aspeed27x0TSPSoCState *a = ASPEED27X0TSP_SOC(s);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 9b645c6c55..9a53f51ec5 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -286,8 +286,9 @@ static const struct gic_intc_irq_info ast2700_gic_intcmap[] = {
{136, 0, 9, NULL},
};
-static qemu_irq aspeed_soc_ast2700_get_irq(AspeedSoCState *s, int dev)
+static qemu_irq aspeed_soc_ast2700_get_irq(void *ctx, int dev)
{
+ AspeedSoCState *s = (AspeedSoCState *)ctx;
Aspeed27x0SoCState *a = ASPEED27X0_SOC(s);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
int or_idx;
@@ -660,7 +661,7 @@ static bool aspeed_soc_ast2700_pcie_realize(DeviceState *dev, Error **errp)
}
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->pcie[i]), 0,
sc->memmap[ASPEED_DEV_PCIE0 + i]);
- irq = aspeed_soc_get_irq(s, ASPEED_DEV_PCIE0 + i);
+ irq = aspeed_soc_get_irq(sc->get_irq, s, ASPEED_DEV_PCIE0 + i);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie[i].rc), 0, irq);
mmio_mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->pcie[i].rc), 1);
@@ -806,7 +807,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fmc), 1,
ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_FMC));
+ aspeed_soc_get_irq(sc->get_irq, s, ASPEED_DEV_FMC));
/* Set up an alias on the FMC CE0 region (boot default) */
MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio;
@@ -835,7 +836,8 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->ehci[i]), 0,
sc->memmap[ASPEED_DEV_EHCI1 + i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i));
+ aspeed_soc_get_irq(sc->get_irq, s,
+ ASPEED_DEV_EHCI1 + i));
}
/*
@@ -870,7 +872,8 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
sc->memmap[ASPEED_DEV_ETH1 + i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i));
+ aspeed_soc_get_irq(sc->get_irq, s,
+ ASPEED_DEV_ETH1 + i));
object_property_set_link(OBJECT(&s->mii[i]), "nic",
OBJECT(&s->ftgmac100[i]), &error_abort);
@@ -915,7 +918,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->adc), 0,
sc->memmap[ASPEED_DEV_ADC]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
+ aspeed_soc_get_irq(sc->get_irq, s, ASPEED_DEV_ADC));
/* I2C */
object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr),
@@ -956,7 +959,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->gpio), 0,
sc->memmap[ASPEED_DEV_GPIO]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_GPIO));
+ aspeed_soc_get_irq(sc->get_irq, s, ASPEED_DEV_GPIO));
/* RTC */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) {
@@ -965,7 +968,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->rtc), 0,
sc->memmap[ASPEED_DEV_RTC]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_RTC));
+ aspeed_soc_get_irq(sc->get_irq, s, ASPEED_DEV_RTC));
/* SDHCI */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) {
@@ -974,7 +977,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sdhci), 0,
sc->memmap[ASPEED_DEV_SDHCI]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI));
+ aspeed_soc_get_irq(sc->get_irq, s, ASPEED_DEV_SDHCI));
/* eMMC */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) {
@@ -983,7 +986,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->emmc), 0,
sc->memmap[ASPEED_DEV_EMMC]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_EMMC));
+ aspeed_soc_get_irq(sc->get_irq, s, ASPEED_DEV_EMMC));
/* Timer */
object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu),
@@ -994,7 +997,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->timerctrl), 0,
sc->memmap[ASPEED_DEV_TIMER1]);
for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
- irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i);
+ irq = aspeed_soc_get_irq(sc->get_irq, s, ASPEED_DEV_TIMER1 + i);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
}
@@ -1007,7 +1010,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->hace), 0,
sc->memmap[ASPEED_DEV_HACE]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
- aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
+ aspeed_soc_get_irq(sc->get_irq, s, ASPEED_DEV_HACE));
/* PCIe Root Complex (RC) */
if (!aspeed_soc_ast2700_pcie_realize(dev, errp)) {
diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c
index e7d0a9c290..2bd872d9a6 100644
--- a/hw/arm/aspeed_soc_common.c
+++ b/hw/arm/aspeed_soc_common.c
@@ -30,9 +30,10 @@ const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types)
return valid_cpu_types[0];
}
-qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
+qemu_irq aspeed_soc_get_irq(qemu_irq (*fn)(void *ctx, int dev),
+ void *ctx, int dev)
{
- return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev);
+ return fn(ctx, dev);
}
bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp)
@@ -52,7 +53,8 @@ bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp)
return false;
}
- sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, aspeed_soc_get_irq(s, uart));
+ sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0,
+ aspeed_soc_get_irq(sc->get_irq, s, uart));
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]);
}
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v1 08/16] hw/arm/aspeed: Remove AspeedSoCState dependency from aspeed_soc_uart_realize() API
2025-10-08 3:21 [PATCH v1 00/16] Introduce AspeedCoprocessor class and base implementation Jamin Lin via
` (6 preceding siblings ...)
2025-10-08 3:21 ` [PATCH v1 07/16] hw/arm/aspeed: Remove AspeedSoCState dependency from aspeed_soc_get_irq() API Jamin Lin via
@ 2025-10-08 3:21 ` Jamin Lin via
2025-10-08 3:21 ` [PATCH v1 09/16] hw/arm/aspeed: Introduce AspeedCoprocessor class and base implementation Jamin Lin via
` (7 subsequent siblings)
15 siblings, 0 replies; 19+ messages in thread
From: Jamin Lin via @ 2025-10-08 3:21 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
Refactor aspeed_soc_uart_realize() to take MemoryRegion *, SerialMM *,
and MMIO base addr instead of AspeedSoCState *, decoupling the helper
from SoC state and making it reusable per-UART.
The helper now realizes a single UART instance and maps its MMIO.
IRQ wiring and iteration over all UARTs are moved to callers.
Update call sites in AST1030, AST2400, AST2600, AST27x0 SSP/TSP, and
AST2700 to loop over UARTs, call the new helper, and connect IRQ via
aspeed_soc_get_irq(sc->get_irq, s, uart).
This simplifies the UART realize path and reduces cross-module coupling.
No functional change.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/arm/aspeed_soc.h | 3 ++-
hw/arm/aspeed_ast10x0.c | 10 ++++++++--
hw/arm/aspeed_ast2400.c | 10 ++++++++--
hw/arm/aspeed_ast2600.c | 10 ++++++++--
hw/arm/aspeed_ast27x0-ssp.c | 10 ++++++++--
hw/arm/aspeed_ast27x0-tsp.c | 10 ++++++++--
hw/arm/aspeed_ast27x0.c | 10 ++++++++--
hw/arm/aspeed_soc_common.c | 29 ++++++++++-------------------
8 files changed, 60 insertions(+), 32 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 427708c087..3cd9ad189f 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -305,7 +305,8 @@ enum {
const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types);
qemu_irq aspeed_soc_get_irq(qemu_irq (*fn)(void *ctx, int dev),
void *ctx, int dev);
-bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp);
+bool aspeed_soc_uart_realize(MemoryRegion *memory, SerialMM *smm,
+ const hwaddr addr, Error **errp);
void aspeed_soc_uart_set_chr(SerialMM *uart, int dev, int uarts_base,
int uarts_num, Chardev *chr);
bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp);
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index 3ce866c66a..80e0da526c 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -193,6 +193,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
DeviceState *armv7m;
Error *err = NULL;
+ int uart;
int i;
g_autofree char *sram_name = NULL;
@@ -317,8 +318,13 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
/* UART */
- if (!aspeed_soc_uart_realize(s, errp)) {
- return;
+ for (i = 0, uart = sc->uarts_base; i < sc->uarts_num; i++, uart++) {
+ if (!aspeed_soc_uart_realize(s->memory, &s->uart[i],
+ sc->memmap[uart], errp)) {
+ return;
+ }
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
+ aspeed_soc_get_irq(sc->get_irq, s, uart));
}
/* Timer */
diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c
index 2910c40807..33736a8988 100644
--- a/hw/arm/aspeed_ast2400.c
+++ b/hw/arm/aspeed_ast2400.c
@@ -252,6 +252,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
AspeedSoCState *s = ASPEED_SOC(dev);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
g_autofree char *sram_name = NULL;
+ int uart;
/* Default boot region (SPI memory or ROMs) */
memory_region_init(&s->spi_boot_container, OBJECT(s),
@@ -339,8 +340,13 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
aspeed_soc_get_irq(sc->get_irq, s, ASPEED_DEV_ADC));
/* UART */
- if (!aspeed_soc_uart_realize(s, errp)) {
- return;
+ for (i = 0, uart = sc->uarts_base; i < sc->uarts_num; i++, uart++) {
+ if (!aspeed_soc_uart_realize(s->memory, &s->uart[i],
+ sc->memmap[uart], errp)) {
+ return;
+ }
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
+ aspeed_soc_get_irq(sc->get_irq, s, uart));
}
/* I2C */
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index cd14dc95bb..80570698fb 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -363,6 +363,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
qemu_irq irq;
g_autofree char *sram_name = NULL;
+ int uart;
/* Default boot region (SPI memory or ROMs) */
memory_region_init(&s->spi_boot_container, OBJECT(s),
@@ -489,8 +490,13 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
aspeed_soc_get_irq(sc->get_irq, s, ASPEED_DEV_ADC));
/* UART */
- if (!aspeed_soc_uart_realize(s, errp)) {
- return;
+ for (i = 0, uart = sc->uarts_base; i < sc->uarts_num; i++, uart++) {
+ if (!aspeed_soc_uart_realize(s->memory, &s->uart[i],
+ sc->memmap[uart], errp)) {
+ return;
+ }
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
+ aspeed_soc_get_irq(sc->get_irq, s, uart));
}
/* I2C */
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
index e63a4b3ad3..57dd588af4 100644
--- a/hw/arm/aspeed_ast27x0-ssp.c
+++ b/hw/arm/aspeed_ast27x0-ssp.c
@@ -165,6 +165,7 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
DeviceState *armv7m;
g_autofree char *sram_name = NULL;
+ int uart;
int i;
if (!clock_has_source(s->sysclk)) {
@@ -238,8 +239,13 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i));
}
/* UART */
- if (!aspeed_soc_uart_realize(s, errp)) {
- return;
+ for (i = 0, uart = sc->uarts_base; i < sc->uarts_num; i++, uart++) {
+ if (!aspeed_soc_uart_realize(s->memory, &s->uart[i],
+ sc->memmap[uart], errp)) {
+ return;
+ }
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
+ aspeed_soc_get_irq(sc->get_irq, s, uart));
}
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->timerctrl),
diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c
index 9537ce121c..28376b3338 100644
--- a/hw/arm/aspeed_ast27x0-tsp.c
+++ b/hw/arm/aspeed_ast27x0-tsp.c
@@ -165,6 +165,7 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
DeviceState *armv7m;
g_autofree char *sram_name = NULL;
+ int uart;
int i;
if (!clock_has_source(s->sysclk)) {
@@ -238,8 +239,13 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i));
}
/* UART */
- if (!aspeed_soc_uart_realize(s, errp)) {
- return;
+ for (i = 0, uart = sc->uarts_base; i < sc->uarts_num; i++, uart++) {
+ if (!aspeed_soc_uart_realize(s->memory, &s->uart[i],
+ sc->memmap[uart], errp)) {
+ return;
+ }
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
+ aspeed_soc_get_irq(sc->get_irq, s, uart));
}
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->timerctrl),
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 9a53f51ec5..de2b4277ce 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -688,6 +688,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
AspeedINTCClass *icio = ASPEED_INTC_GET_CLASS(&a->intc[1]);
g_autofree char *name = NULL;
qemu_irq irq;
+ int uart;
/* Default boot region (SPI memory or ROMs) */
memory_region_init(&s->spi_boot_container, OBJECT(s),
@@ -789,8 +790,13 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
sc->memmap[ASPEED_DEV_SCUIO]);
/* UART */
- if (!aspeed_soc_uart_realize(s, errp)) {
- return;
+ for (i = 0, uart = sc->uarts_base; i < sc->uarts_num; i++, uart++) {
+ if (!aspeed_soc_uart_realize(s->memory, &s->uart[i],
+ sc->memmap[uart], errp)) {
+ return;
+ }
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
+ aspeed_soc_get_irq(sc->get_irq, s, uart));
}
/* FMC, The number of CS is set at the board level */
diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c
index 2bd872d9a6..6bb8ed730f 100644
--- a/hw/arm/aspeed_soc_common.c
+++ b/hw/arm/aspeed_soc_common.c
@@ -36,28 +36,19 @@ qemu_irq aspeed_soc_get_irq(qemu_irq (*fn)(void *ctx, int dev),
return fn(ctx, dev);
}
-bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp)
+bool aspeed_soc_uart_realize(MemoryRegion *memory, SerialMM *smm,
+ const hwaddr addr, Error **errp)
{
- AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
- SerialMM *smm;
-
- for (int i = 0, uart = sc->uarts_base; i < sc->uarts_num; i++, uart++) {
- smm = &s->uart[i];
-
- /* Chardev property is set by the machine. */
- qdev_prop_set_uint8(DEVICE(smm), "regshift", 2);
- qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400);
- qdev_set_legacy_instance_id(DEVICE(smm), sc->memmap[uart], 2);
- qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN);
- if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) {
- return false;
- }
-
- sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0,
- aspeed_soc_get_irq(sc->get_irq, s, uart));
- aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]);
+ /* Chardev property is set by the machine. */
+ qdev_prop_set_uint8(DEVICE(smm), "regshift", 2);
+ qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400);
+ qdev_set_legacy_instance_id(DEVICE(smm), addr, 2);
+ qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN);
+ if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) {
+ return false;
}
+ aspeed_mmio_map(memory, SYS_BUS_DEVICE(smm), 0, addr);
return true;
}
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v1 09/16] hw/arm/aspeed: Introduce AspeedCoprocessor class and base implementation
2025-10-08 3:21 [PATCH v1 00/16] Introduce AspeedCoprocessor class and base implementation Jamin Lin via
` (7 preceding siblings ...)
2025-10-08 3:21 ` [PATCH v1 08/16] hw/arm/aspeed: Remove AspeedSoCState dependency from aspeed_soc_uart_realize() API Jamin Lin via
@ 2025-10-08 3:21 ` Jamin Lin via
2025-10-08 16:14 ` [SPAM] " Cédric Le Goater
2025-10-08 3:21 ` [PATCH v1 10/16] hw/arm/aspeed_ast27x0-ssp: Make AST27x0 SSP inherit from AspeedCoprocessor instead of AspeedSoC Jamin Lin via
` (6 subsequent siblings)
15 siblings, 1 reply; 19+ messages in thread
From: Jamin Lin via @ 2025-10-08 3:21 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
Add a new AspeedCoprocessor class that defines the foundational structure for
ASPEED coprocessor models. This class encapsulates a base DeviceState with
links to system memory, clock, and peripheral components such as SCU, SCUIO,
Timer Controller, and UARTs.
Introduce the corresponding implementation file
aspeed_coprocessor_common.c, which provides the aspeed_coprocessor_realize()
method, property registration, and QOM type registration. The class is marked
as abstract and intended to serve as a common base for specific coprocessor
variants (e.g. SSP/TSP subsystems).
This establishes a reusable and extensible framework for modeling ASPEED
coprocessor devices.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/arm/aspeed_coprocessor.h | 45 ++++++++++++++++++++++++++
hw/arm/aspeed_coprocessor_common.c | 49 +++++++++++++++++++++++++++++
hw/arm/meson.build | 3 +-
3 files changed, 96 insertions(+), 1 deletion(-)
create mode 100644 include/hw/arm/aspeed_coprocessor.h
create mode 100644 hw/arm/aspeed_coprocessor_common.c
diff --git a/include/hw/arm/aspeed_coprocessor.h b/include/hw/arm/aspeed_coprocessor.h
new file mode 100644
index 0000000000..6938dfe24c
--- /dev/null
+++ b/include/hw/arm/aspeed_coprocessor.h
@@ -0,0 +1,45 @@
+/*
+ * ASPEED Coprocessor
+ *
+ * Copyright (C) 2025 ASPEED Technology Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef ASPEED_COPROCESSOR_H
+#define ASPEED_COPROCESSOR_H
+
+#include "qom/object.h"
+#include "hw/arm/aspeed_soc.h"
+
+struct AspeedCoprocessorState {
+ DeviceState parent;
+
+ MemoryRegion *memory;
+ MemoryRegion sram;
+ Clock *sysclk;
+
+ AspeedSCUState scu;
+ AspeedSCUState scuio;
+ AspeedTimerCtrlState timerctrl;
+ SerialMM uart[ASPEED_UARTS_NUM];
+};
+
+#define TYPE_ASPEED_COPROCESSOR "aspeed-coprocessor"
+OBJECT_DECLARE_TYPE(AspeedCoprocessorState, AspeedCoprocessorClass,
+ ASPEED_COPROCESSOR)
+
+struct AspeedCoprocessorClass {
+ DeviceClass parent_class;
+
+ /** valid_cpu_types: NULL terminated array of a single CPU type. */
+ const char * const *valid_cpu_types;
+ uint32_t silicon_rev;
+ const hwaddr *memmap;
+ const int *irqmap;
+ int uarts_base;
+ int uarts_num;
+ qemu_irq (*get_irq)(void *ctx, int dev);
+};
+
+#endif /* ASPEED_COPROCESSOR_H */
diff --git a/hw/arm/aspeed_coprocessor_common.c b/hw/arm/aspeed_coprocessor_common.c
new file mode 100644
index 0000000000..8a94b44f07
--- /dev/null
+++ b/hw/arm/aspeed_coprocessor_common.c
@@ -0,0 +1,49 @@
+/*
+ * ASPEED Coprocessor
+ *
+ * Copyright (C) 2025 ASPEED Technology Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "system/memory.h"
+#include "hw/qdev-properties.h"
+#include "hw/arm/aspeed_coprocessor.h"
+
+static void aspeed_coprocessor_realize(DeviceState *dev, Error **errp)
+{
+ AspeedCoprocessorState *s = ASPEED_COPROCESSOR(dev);
+
+ if (!s->memory) {
+ error_setg(errp, "'memory' link is not set");
+ return;
+ }
+}
+
+static const Property aspeed_coprocessor_properties[] = {
+ DEFINE_PROP_LINK("memory", AspeedCoprocessorState, memory,
+ TYPE_MEMORY_REGION, MemoryRegion *),
+};
+
+static void aspeed_coprocessor_class_init(ObjectClass *oc, const void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = aspeed_coprocessor_realize;
+ device_class_set_props(dc, aspeed_coprocessor_properties);
+}
+
+static const TypeInfo aspeed_coprocessor_types[] = {
+ {
+ .name = TYPE_ASPEED_COPROCESSOR,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(AspeedCoprocessorState),
+ .class_size = sizeof(AspeedCoprocessorClass),
+ .class_init = aspeed_coprocessor_class_init,
+ .abstract = true,
+ },
+};
+
+DEFINE_TYPES(aspeed_coprocessor_types)
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index dc68391305..0b2c66e391 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -52,7 +52,8 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
'fby35.c'))
arm_common_ss.add(when: ['CONFIG_ASPEED_SOC', 'TARGET_AARCH64'], if_true: files(
'aspeed_ast27x0.c',
- 'aspeed_ast27x0-fc.c',))
+ 'aspeed_ast27x0-fc.c',
+ 'aspeed_coprocessor_common.c',))
arm_common_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2.c'))
arm_common_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2-tz.c'))
arm_common_ss.add(when: 'CONFIG_MSF2', if_true: files('msf2-soc.c'))
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [SPAM] [PATCH v1 09/16] hw/arm/aspeed: Introduce AspeedCoprocessor class and base implementation
2025-10-08 3:21 ` [PATCH v1 09/16] hw/arm/aspeed: Introduce AspeedCoprocessor class and base implementation Jamin Lin via
@ 2025-10-08 16:14 ` Cédric Le Goater
2025-10-09 1:18 ` Jamin Lin
0 siblings, 1 reply; 19+ messages in thread
From: Cédric Le Goater @ 2025-10-08 16:14 UTC (permalink / raw)
To: Jamin Lin, Peter Maydell, Steven Lee, Troy Lee, Andrew Jeffery,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, kane_chen
Jamin,
On 10/8/25 05:21, Jamin Lin wrote:
> Add a new AspeedCoprocessor class that defines the foundational structure for
> ASPEED coprocessor models. This class encapsulates a base DeviceState with
> links to system memory, clock, and peripheral components such as SCU, SCUIO,
> Timer Controller, and UARTs.
>
> Introduce the corresponding implementation file
> aspeed_coprocessor_common.c, which provides the aspeed_coprocessor_realize()
> method, property registration, and QOM type registration. The class is marked
> as abstract and intended to serve as a common base for specific coprocessor
> variants (e.g. SSP/TSP subsystems).
>
> This establishes a reusable and extensible framework for modeling ASPEED
> coprocessor devices.
>
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> ---
> include/hw/arm/aspeed_coprocessor.h | 45 ++++++++++++++++++++++++++
> hw/arm/aspeed_coprocessor_common.c | 49 +++++++++++++++++++++++++++++
> hw/arm/meson.build | 3 +-
> 3 files changed, 96 insertions(+), 1 deletion(-)
> create mode 100644 include/hw/arm/aspeed_coprocessor.h
> create mode 100644 hw/arm/aspeed_coprocessor_common.c
>
> diff --git a/include/hw/arm/aspeed_coprocessor.h b/include/hw/arm/aspeed_coprocessor.h
> new file mode 100644
> index 0000000000..6938dfe24c
> --- /dev/null
> +++ b/include/hw/arm/aspeed_coprocessor.h
> @@ -0,0 +1,45 @@
> +/*
> + * ASPEED Coprocessor
> + *
> + * Copyright (C) 2025 ASPEED Technology Inc.
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +
> +#ifndef ASPEED_COPROCESSOR_H
> +#define ASPEED_COPROCESSOR_H
> +
> +#include "qom/object.h"
> +#include "hw/arm/aspeed_soc.h"
> +
> +struct AspeedCoprocessorState {
> + DeviceState parent;
> +
> + MemoryRegion *memory;
> + MemoryRegion sram;
> + Clock *sysclk;
> +
> + AspeedSCUState scu;
> + AspeedSCUState scuio;
> + AspeedTimerCtrlState timerctrl;
> + SerialMM uart[ASPEED_UARTS_NUM];
> +};
> +
> +#define TYPE_ASPEED_COPROCESSOR "aspeed-coprocessor"
> +OBJECT_DECLARE_TYPE(AspeedCoprocessorState, AspeedCoprocessorClass,
> + ASPEED_COPROCESSOR)
> +
> +struct AspeedCoprocessorClass {
> + DeviceClass parent_class;
> +
> + /** valid_cpu_types: NULL terminated array of a single CPU type. */
> + const char * const *valid_cpu_types;
> + uint32_t silicon_rev;
> + const hwaddr *memmap;
> + const int *irqmap;
> + int uarts_base;
> + int uarts_num;
> + qemu_irq (*get_irq)(void *ctx, int dev);
> +};
> +
> +#endif /* ASPEED_COPROCESSOR_H */
> diff --git a/hw/arm/aspeed_coprocessor_common.c b/hw/arm/aspeed_coprocessor_common.c
> new file mode 100644
> index 0000000000..8a94b44f07
> --- /dev/null
> +++ b/hw/arm/aspeed_coprocessor_common.c
> @@ -0,0 +1,49 @@
> +/*
> + * ASPEED Coprocessor
> + *
> + * Copyright (C) 2025 ASPEED Technology Inc.
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qapi/error.h"
> +#include "system/memory.h"
> +#include "hw/qdev-properties.h"
> +#include "hw/arm/aspeed_coprocessor.h"
> +
> +static void aspeed_coprocessor_realize(DeviceState *dev, Error **errp)
> +{
> + AspeedCoprocessorState *s = ASPEED_COPROCESSOR(dev);
> +
> + if (!s->memory) {
> + error_setg(errp, "'memory' link is not set");
> + return;
> + }
> +}
> +
> +static const Property aspeed_coprocessor_properties[] = {
> + DEFINE_PROP_LINK("memory", AspeedCoprocessorState, memory,
> + TYPE_MEMORY_REGION, MemoryRegion *),
> +};
> +
> +static void aspeed_coprocessor_class_init(ObjectClass *oc, const void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(oc);
> +
> + dc->realize = aspeed_coprocessor_realize;
> + device_class_set_props(dc, aspeed_coprocessor_properties);
> +}
> +
> +static const TypeInfo aspeed_coprocessor_types[] = {
> + {
> + .name = TYPE_ASPEED_COPROCESSOR,
> + .parent = TYPE_DEVICE,
> + .instance_size = sizeof(AspeedCoprocessorState),
> + .class_size = sizeof(AspeedCoprocessorClass),
> + .class_init = aspeed_coprocessor_class_init,
> + .abstract = true,
> + },
> +};
> +
> +DEFINE_TYPES(aspeed_coprocessor_types)
> diff --git a/hw/arm/meson.build b/hw/arm/meson.build
> index dc68391305..0b2c66e391 100644
> --- a/hw/arm/meson.build
> +++ b/hw/arm/meson.build
> @@ -52,7 +52,8 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
> 'fby35.c'))
> arm_common_ss.add(when: ['CONFIG_ASPEED_SOC', 'TARGET_AARCH64'], if_true: files(
> 'aspeed_ast27x0.c',
> - 'aspeed_ast27x0-fc.c',))
> + 'aspeed_ast27x0-fc.c',
> + 'aspeed_coprocessor_common.c',))
I don't think we need to keep the ending comma ','.
More important, this list lacks source files :
'aspeed_ast27x0-ssp.c',
'aspeed_ast27x0-tsp.c',
which are aarch64 specific and with the following changes of this
series, 'make check' fails with :
Type 'aspeed27x0ssp-soc' is missing its parent 'aspeed-coprocessor'
A preliminary fix is needed.
Please run 'make check' before sending.
Thanks,
C.
> arm_common_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2.c'))
> arm_common_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2-tz.c'))
> arm_common_ss.add(when: 'CONFIG_MSF2', if_true: files('msf2-soc.c'))
^ permalink raw reply [flat|nested] 19+ messages in thread* RE: [SPAM] [PATCH v1 09/16] hw/arm/aspeed: Introduce AspeedCoprocessor class and base implementation
2025-10-08 16:14 ` [SPAM] " Cédric Le Goater
@ 2025-10-09 1:18 ` Jamin Lin
0 siblings, 0 replies; 19+ messages in thread
From: Jamin Lin @ 2025-10-09 1:18 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, Kane Chen
Hi Cédric
> AspeedCoprocessor class and base implementation
>
> Jamin,
>
> On 10/8/25 05:21, Jamin Lin wrote:
> > Add a new AspeedCoprocessor class that defines the foundational
> > structure for ASPEED coprocessor models. This class encapsulates a
> > base DeviceState with links to system memory, clock, and peripheral
> > components such as SCU, SCUIO, Timer Controller, and UARTs.
> >
> > Introduce the corresponding implementation file
> > aspeed_coprocessor_common.c, which provides the
> > aspeed_coprocessor_realize() method, property registration, and QOM
> > type registration. The class is marked as abstract and intended to
> > serve as a common base for specific coprocessor variants (e.g. SSP/TSP
> subsystems).
> >
> > This establishes a reusable and extensible framework for modeling
> > ASPEED coprocessor devices.
> >
> > Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> > ---
> > include/hw/arm/aspeed_coprocessor.h | 45
> ++++++++++++++++++++++++++
> > hw/arm/aspeed_coprocessor_common.c | 49
> +++++++++++++++++++++++++++++
> > hw/arm/meson.build | 3 +-
> > 3 files changed, 96 insertions(+), 1 deletion(-)
> > create mode 100644 include/hw/arm/aspeed_coprocessor.h
> > create mode 100644 hw/arm/aspeed_coprocessor_common.c
> >
> > diff --git a/include/hw/arm/aspeed_coprocessor.h
> > b/include/hw/arm/aspeed_coprocessor.h
> > new file mode 100644
> > index 0000000000..6938dfe24c
> > --- /dev/null
> > +++ b/include/hw/arm/aspeed_coprocessor.h
> > @@ -0,0 +1,45 @@
> > +/*
> > + * ASPEED Coprocessor
> > + *
> > + * Copyright (C) 2025 ASPEED Technology Inc.
> > + *
> > + * SPDX-License-Identifier: GPL-2.0-or-later */
> > +
> > +#ifndef ASPEED_COPROCESSOR_H
> > +#define ASPEED_COPROCESSOR_H
> > +
> > +#include "qom/object.h"
> > +#include "hw/arm/aspeed_soc.h"
> > +
> > +struct AspeedCoprocessorState {
> > + DeviceState parent;
> > +
> > + MemoryRegion *memory;
> > + MemoryRegion sram;
> > + Clock *sysclk;
> > +
> > + AspeedSCUState scu;
> > + AspeedSCUState scuio;
> > + AspeedTimerCtrlState timerctrl;
> > + SerialMM uart[ASPEED_UARTS_NUM];
> > +};
> > +
> > +#define TYPE_ASPEED_COPROCESSOR "aspeed-coprocessor"
> > +OBJECT_DECLARE_TYPE(AspeedCoprocessorState, AspeedCoprocessorClass,
> > + ASPEED_COPROCESSOR)
> > +
> > +struct AspeedCoprocessorClass {
> > + DeviceClass parent_class;
> > +
> > + /** valid_cpu_types: NULL terminated array of a single CPU type. */
> > + const char * const *valid_cpu_types;
> > + uint32_t silicon_rev;
> > + const hwaddr *memmap;
> > + const int *irqmap;
> > + int uarts_base;
> > + int uarts_num;
> > + qemu_irq (*get_irq)(void *ctx, int dev); };
> > +
> > +#endif /* ASPEED_COPROCESSOR_H */
> > diff --git a/hw/arm/aspeed_coprocessor_common.c
> > b/hw/arm/aspeed_coprocessor_common.c
> > new file mode 100644
> > index 0000000000..8a94b44f07
> > --- /dev/null
> > +++ b/hw/arm/aspeed_coprocessor_common.c
> > @@ -0,0 +1,49 @@
> > +/*
> > + * ASPEED Coprocessor
> > + *
> > + * Copyright (C) 2025 ASPEED Technology Inc.
> > + *
> > + * SPDX-License-Identifier: GPL-2.0-or-later */
> > +
> > +#include "qemu/osdep.h"
> > +#include "qapi/error.h"
> > +#include "system/memory.h"
> > +#include "hw/qdev-properties.h"
> > +#include "hw/arm/aspeed_coprocessor.h"
> > +
> > +static void aspeed_coprocessor_realize(DeviceState *dev, Error
> > +**errp) {
> > + AspeedCoprocessorState *s = ASPEED_COPROCESSOR(dev);
> > +
> > + if (!s->memory) {
> > + error_setg(errp, "'memory' link is not set");
> > + return;
> > + }
> > +}
> > +
> > +static const Property aspeed_coprocessor_properties[] = {
> > + DEFINE_PROP_LINK("memory", AspeedCoprocessorState, memory,
> > + TYPE_MEMORY_REGION, MemoryRegion *), };
> > +
> > +static void aspeed_coprocessor_class_init(ObjectClass *oc, const void
> > +*data) {
> > + DeviceClass *dc = DEVICE_CLASS(oc);
> > +
> > + dc->realize = aspeed_coprocessor_realize;
> > + device_class_set_props(dc, aspeed_coprocessor_properties); }
> > +
> > +static const TypeInfo aspeed_coprocessor_types[] = {
> > + {
> > + .name = TYPE_ASPEED_COPROCESSOR,
> > + .parent = TYPE_DEVICE,
> > + .instance_size = sizeof(AspeedCoprocessorState),
> > + .class_size = sizeof(AspeedCoprocessorClass),
> > + .class_init = aspeed_coprocessor_class_init,
> > + .abstract = true,
> > + },
> > +};
> > +
> > +DEFINE_TYPES(aspeed_coprocessor_types)
> > diff --git a/hw/arm/meson.build b/hw/arm/meson.build index
> > dc68391305..0b2c66e391 100644
> > --- a/hw/arm/meson.build
> > +++ b/hw/arm/meson.build
> > @@ -52,7 +52,8 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true:
> files(
> > 'fby35.c'))
> > arm_common_ss.add(when: ['CONFIG_ASPEED_SOC',
> 'TARGET_AARCH64'], if_true: files(
> > 'aspeed_ast27x0.c',
> > - 'aspeed_ast27x0-fc.c',))
> > + 'aspeed_ast27x0-fc.c',
> > + 'aspeed_coprocessor_common.c',))
>
> I don't think we need to keep the ending comma ','.
>
>
> More important, this list lacks source files :
>
> 'aspeed_ast27x0-ssp.c',
> 'aspeed_ast27x0-tsp.c',
>
> which are aarch64 specific and with the following changes of this series, 'make
> check' fails with :
>
> Type 'aspeed27x0ssp-soc' is missing its parent 'aspeed-coprocessor'
>
> A preliminary fix is needed.
>
> Please run 'make check' before sending.
>
Thanks for reporting this issue.
I’ll run the tests and resend v2.
Jamin
> Thanks,
>
> C.
>
>
>
>
> > arm_common_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2.c'))
> > arm_common_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2-tz.c'))
> > arm_common_ss.add(when: 'CONFIG_MSF2', if_true: files('msf2-soc.c'))
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v1 10/16] hw/arm/aspeed_ast27x0-ssp: Make AST27x0 SSP inherit from AspeedCoprocessor instead of AspeedSoC
2025-10-08 3:21 [PATCH v1 00/16] Introduce AspeedCoprocessor class and base implementation Jamin Lin via
` (8 preceding siblings ...)
2025-10-08 3:21 ` [PATCH v1 09/16] hw/arm/aspeed: Introduce AspeedCoprocessor class and base implementation Jamin Lin via
@ 2025-10-08 3:21 ` Jamin Lin via
2025-10-08 3:21 ` [PATCH v1 11/16] hw/arm/aspeed_ast27x0-tsp: Make AST27x0 TSP " Jamin Lin via
` (5 subsequent siblings)
15 siblings, 0 replies; 19+ messages in thread
From: Jamin Lin via @ 2025-10-08 3:21 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
Refactor the AST27x0 SSP implementation to derive from the newly introduced
AspeedCoprocessor base class rather than AspeedSoC. The AspeedSoC class
contains many SoC-level fields and behaviors that are not applicable to
coprocessor subsystems like SSP, leading to unnecessary coupling and code size.
This change moves the Aspeed27x0SSPSoCState structure definition into
aspeed_coprocessor.h and updates related references in
aspeed_ast27x0-ssp.c and aspeed_ast27x0-fc.c to use
AspeedCoprocessorState and AspeedCoprocessorClass.
Key updates include:
- Replace inheritance from AspeedSoC -> AspeedCoprocessor.
- Replace type casts and class access macros (ASPEED_SOC_*) with
ASPEED_COPROCESSOR_*.
This refactor improves modularity, reduces memory footprint, and prepares
for future coprocessor variants to share a lighter-weight common base.
No functional change.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/arm/aspeed_coprocessor.h | 12 ++++++++++++
include/hw/arm/aspeed_soc.h | 12 ------------
hw/arm/aspeed_ast27x0-fc.c | 10 +++++-----
hw/arm/aspeed_ast27x0-ssp.c | 29 ++++++++++++-----------------
4 files changed, 29 insertions(+), 34 deletions(-)
diff --git a/include/hw/arm/aspeed_coprocessor.h b/include/hw/arm/aspeed_coprocessor.h
index 6938dfe24c..927e8675b0 100644
--- a/include/hw/arm/aspeed_coprocessor.h
+++ b/include/hw/arm/aspeed_coprocessor.h
@@ -42,4 +42,16 @@ struct AspeedCoprocessorClass {
qemu_irq (*get_irq)(void *ctx, int dev);
};
+struct Aspeed27x0SSPSoCState {
+ AspeedCoprocessorState parent;
+ AspeedINTCState intc[2];
+ UnimplementedDeviceState ipc[2];
+ UnimplementedDeviceState scuio;
+
+ ARMv7MState armv7m;
+};
+
+#define TYPE_ASPEED27X0SSP_SOC "aspeed27x0ssp-soc"
+OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SSPSoCState, ASPEED27X0SSP_SOC)
+
#endif /* ASPEED_COPROCESSOR_H */
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 3cd9ad189f..b100a404f1 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -153,18 +153,6 @@ struct Aspeed10x0SoCState {
ARMv7MState armv7m;
};
-struct Aspeed27x0SSPSoCState {
- AspeedSoCState parent;
- AspeedINTCState intc[2];
- UnimplementedDeviceState ipc[2];
- UnimplementedDeviceState scuio;
-
- ARMv7MState armv7m;
-};
-
-#define TYPE_ASPEED27X0SSP_SOC "aspeed27x0ssp-soc"
-OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SSPSoCState, ASPEED27X0SSP_SOC)
-
struct Aspeed27x0TSPSoCState {
AspeedSoCState parent;
AspeedINTCState intc[2];
diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
index e598f57ca2..4315e8da98 100644
--- a/hw/arm/aspeed_ast27x0-fc.c
+++ b/hw/arm/aspeed_ast27x0-fc.c
@@ -21,7 +21,7 @@
#include "hw/loader.h"
#include "hw/arm/boot.h"
#include "hw/block/flash.h"
-
+#include "hw/arm/aspeed_coprocessor.h"
#define TYPE_AST2700A1FC MACHINE_TYPE_NAME("ast2700fc")
OBJECT_DECLARE_SIMPLE_TYPE(Ast2700FCState, AST2700A1FC);
@@ -115,8 +115,8 @@ static bool ast2700fc_ca35_init(MachineState *machine, Error **errp)
static bool ast2700fc_ssp_init(MachineState *machine, Error **errp)
{
- AspeedSoCState *soc;
- AspeedSoCClass *sc;
+ AspeedCoprocessorState *soc;
+ AspeedCoprocessorClass *sc;
Ast2700FCState *s = AST2700A1FC(machine);
s->ssp_sysclk = clock_new(OBJECT(s), "SSP_SYSCLK");
clock_set_hz(s->ssp_sysclk, 200000000ULL);
@@ -129,8 +129,8 @@ static bool ast2700fc_ssp_init(MachineState *machine, Error **errp)
object_property_set_link(OBJECT(&s->ssp), "memory",
OBJECT(&s->ssp_memory), &error_abort);
- soc = ASPEED_SOC(&s->ssp);
- sc = ASPEED_SOC_GET_CLASS(soc);
+ soc = ASPEED_COPROCESSOR(&s->ssp);
+ sc = ASPEED_COPROCESSOR_GET_CLASS(soc);
aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART4, sc->uarts_base,
sc->uarts_num, serial_hd(1));
if (!qdev_realize(DEVICE(&s->ssp), NULL, errp)) {
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
index 57dd588af4..0e68c0f6a8 100644
--- a/hw/arm/aspeed_ast27x0-ssp.c
+++ b/hw/arm/aspeed_ast27x0-ssp.c
@@ -14,6 +14,7 @@
#include "hw/qdev-clock.h"
#include "hw/misc/unimp.h"
#include "hw/arm/aspeed_soc.h"
+#include "hw/arm/aspeed_coprocessor.h"
#define AST2700_SSP_RAM_SIZE (32 * MiB)
@@ -106,9 +107,9 @@ static struct nvic_intc_irq_info ast2700_ssp_intcmap[] = {
static qemu_irq aspeed_soc_ast27x0ssp_get_irq(void *ctx, int dev)
{
- AspeedSoCState *s = (AspeedSoCState *)ctx;
+ AspeedCoprocessorState *s = (AspeedCoprocessorState *)ctx;
Aspeed27x0SSPSoCState *a = ASPEED27X0SSP_SOC(s);
- AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+ AspeedCoprocessorClass *sc = ASPEED_COPROCESSOR_GET_CLASS(s);
int or_idx;
int idx;
@@ -130,8 +131,8 @@ static qemu_irq aspeed_soc_ast27x0ssp_get_irq(void *ctx, int dev)
static void aspeed_soc_ast27x0ssp_init(Object *obj)
{
Aspeed27x0SSPSoCState *a = ASPEED27X0SSP_SOC(obj);
- AspeedSoCState *s = ASPEED_SOC(obj);
- AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+ AspeedCoprocessorState *s = ASPEED_COPROCESSOR(obj);
+ AspeedCoprocessorClass *sc = ASPEED_COPROCESSOR_GET_CLASS(s);
int i;
object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);
@@ -161,8 +162,8 @@ static void aspeed_soc_ast27x0ssp_init(Object *obj)
static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
{
Aspeed27x0SSPSoCState *a = ASPEED27X0SSP_SOC(dev_soc);
- AspeedSoCState *s = ASPEED_SOC(dev_soc);
- AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+ AspeedCoprocessorState *s = ASPEED_COPROCESSOR(dev_soc);
+ AspeedCoprocessorClass *sc = ASPEED_COPROCESSOR_GET_CLASS(s);
DeviceState *armv7m;
g_autofree char *sram_name = NULL;
int uart;
@@ -186,8 +187,8 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
sram_name = g_strdup_printf("aspeed.dram.%d",
CPU(a->armv7m.cpu)->cpu_index);
- if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size,
- errp)) {
+ if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name,
+ AST2700_SSP_RAM_SIZE, errp)) {
return;
}
memory_region_add_subregion(s->memory,
@@ -269,31 +270,25 @@ static void aspeed_soc_ast27x0ssp_class_init(ObjectClass *klass, const void *dat
NULL
};
DeviceClass *dc = DEVICE_CLASS(klass);
- AspeedSoCClass *sc = ASPEED_SOC_CLASS(dc);
+ AspeedCoprocessorClass *sc = ASPEED_COPROCESSOR_CLASS(dc);
- /* Reason: The Aspeed SoC can only be instantiated from a board */
+ /* Reason: The Aspeed Coprocessor can only be instantiated from a board */
dc->user_creatable = false;
dc->realize = aspeed_soc_ast27x0ssp_realize;
sc->valid_cpu_types = valid_cpu_types;
sc->silicon_rev = AST2700_A1_SILICON_REV;
- sc->sram_size = AST2700_SSP_RAM_SIZE;
- sc->spis_num = 0;
- sc->ehcis_num = 0;
- sc->wdts_num = 0;
- sc->macs_num = 0;
sc->uarts_num = 13;
sc->uarts_base = ASPEED_DEV_UART0;
sc->irqmap = aspeed_soc_ast27x0ssp_irqmap;
sc->memmap = aspeed_soc_ast27x0ssp_memmap;
- sc->num_cpus = 1;
sc->get_irq = aspeed_soc_ast27x0ssp_get_irq;
}
static const TypeInfo aspeed_soc_ast27x0ssp_types[] = {
{
.name = TYPE_ASPEED27X0SSP_SOC,
- .parent = TYPE_ASPEED_SOC,
+ .parent = TYPE_ASPEED_COPROCESSOR,
.instance_size = sizeof(Aspeed27x0SSPSoCState),
.instance_init = aspeed_soc_ast27x0ssp_init,
.class_init = aspeed_soc_ast27x0ssp_class_init,
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v1 11/16] hw/arm/aspeed_ast27x0-tsp: Make AST27x0 TSP inherit from AspeedCoprocessor instead of AspeedSoC
2025-10-08 3:21 [PATCH v1 00/16] Introduce AspeedCoprocessor class and base implementation Jamin Lin via
` (9 preceding siblings ...)
2025-10-08 3:21 ` [PATCH v1 10/16] hw/arm/aspeed_ast27x0-ssp: Make AST27x0 SSP inherit from AspeedCoprocessor instead of AspeedSoC Jamin Lin via
@ 2025-10-08 3:21 ` Jamin Lin via
2025-10-08 3:21 ` [PATCH v1 12/16] hw/arm/aspeed_ast27x0-ssp: Change to use Aspeed27x0CoprocessorState Jamin Lin via
` (4 subsequent siblings)
15 siblings, 0 replies; 19+ messages in thread
From: Jamin Lin via @ 2025-10-08 3:21 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
Refactor the AST27x0 TSP implementation to derive from the newly introduced
AspeedCoprocessor base class rather than AspeedSoC. The AspeedSoC class
includes SoC-level infrastructure and peripheral definitions that are not
applicable to lightweight coprocessor subsystems such as TSP, resulting in
unnecessary coupling and complexity.
This change moves the Aspeed27x0TSPSoCState structure definition into
aspeed_coprocessor.h and updates all related references in
aspeed_ast27x0-tsp.c and aspeed_ast27x0-fc.c to use
AspeedCoprocessorState and AspeedCoprocessorClass.
Key updates include:
- Replace inheritance from AspeedSoC -> AspeedCoprocessor.
- Update type casts and macros from ASPEED_SOC_* to ASPEED_COPROCESSOR_*
This refactor improves modularity, reduces memory footprint, and prepares
for future coprocessor variants to share a lighter-weight common base.
No functional change.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/arm/aspeed_coprocessor.h | 12 ++++++++++++
include/hw/arm/aspeed_soc.h | 12 ------------
hw/arm/aspeed_ast27x0-fc.c | 8 ++++----
hw/arm/aspeed_ast27x0-tsp.c | 29 ++++++++++++-----------------
4 files changed, 28 insertions(+), 33 deletions(-)
diff --git a/include/hw/arm/aspeed_coprocessor.h b/include/hw/arm/aspeed_coprocessor.h
index 927e8675b0..2c10327456 100644
--- a/include/hw/arm/aspeed_coprocessor.h
+++ b/include/hw/arm/aspeed_coprocessor.h
@@ -54,4 +54,16 @@ struct Aspeed27x0SSPSoCState {
#define TYPE_ASPEED27X0SSP_SOC "aspeed27x0ssp-soc"
OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SSPSoCState, ASPEED27X0SSP_SOC)
+struct Aspeed27x0TSPSoCState {
+ AspeedCoprocessorState parent;
+ AspeedINTCState intc[2];
+ UnimplementedDeviceState ipc[2];
+ UnimplementedDeviceState scuio;
+
+ ARMv7MState armv7m;
+};
+
+#define TYPE_ASPEED27X0TSP_SOC "aspeed27x0tsp-soc"
+OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0TSPSoCState, ASPEED27X0TSP_SOC)
+
#endif /* ASPEED_COPROCESSOR_H */
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index b100a404f1..b6485f3d9c 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -153,18 +153,6 @@ struct Aspeed10x0SoCState {
ARMv7MState armv7m;
};
-struct Aspeed27x0TSPSoCState {
- AspeedSoCState parent;
- AspeedINTCState intc[2];
- UnimplementedDeviceState ipc[2];
- UnimplementedDeviceState scuio;
-
- ARMv7MState armv7m;
-};
-
-#define TYPE_ASPEED27X0TSP_SOC "aspeed27x0tsp-soc"
-OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0TSPSoCState, ASPEED27X0TSP_SOC)
-
#define TYPE_ASPEED10X0_SOC "aspeed10x0-soc"
OBJECT_DECLARE_SIMPLE_TYPE(Aspeed10x0SoCState, ASPEED10X0_SOC)
diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
index 4315e8da98..b34cd54e4e 100644
--- a/hw/arm/aspeed_ast27x0-fc.c
+++ b/hw/arm/aspeed_ast27x0-fc.c
@@ -142,8 +142,8 @@ static bool ast2700fc_ssp_init(MachineState *machine, Error **errp)
static bool ast2700fc_tsp_init(MachineState *machine, Error **errp)
{
- AspeedSoCState *soc;
- AspeedSoCClass *sc;
+ AspeedCoprocessorState *soc;
+ AspeedCoprocessorClass *sc;
Ast2700FCState *s = AST2700A1FC(machine);
s->tsp_sysclk = clock_new(OBJECT(s), "TSP_SYSCLK");
clock_set_hz(s->tsp_sysclk, 200000000ULL);
@@ -156,8 +156,8 @@ static bool ast2700fc_tsp_init(MachineState *machine, Error **errp)
object_property_set_link(OBJECT(&s->tsp), "memory",
OBJECT(&s->tsp_memory), &error_abort);
- soc = ASPEED_SOC(&s->tsp);
- sc = ASPEED_SOC_GET_CLASS(soc);
+ soc = ASPEED_COPROCESSOR(&s->tsp);
+ sc = ASPEED_COPROCESSOR_GET_CLASS(soc);
aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART7, sc->uarts_base,
sc->uarts_num, serial_hd(2));
if (!qdev_realize(DEVICE(&s->tsp), NULL, errp)) {
diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c
index 28376b3338..8b13ab526d 100644
--- a/hw/arm/aspeed_ast27x0-tsp.c
+++ b/hw/arm/aspeed_ast27x0-tsp.c
@@ -14,6 +14,7 @@
#include "hw/qdev-clock.h"
#include "hw/misc/unimp.h"
#include "hw/arm/aspeed_soc.h"
+#include "hw/arm/aspeed_coprocessor.h"
#define AST2700_TSP_RAM_SIZE (32 * MiB)
@@ -106,9 +107,9 @@ static struct nvic_intc_irq_info ast2700_tsp_intcmap[] = {
static qemu_irq aspeed_soc_ast27x0tsp_get_irq(void *ctx, int dev)
{
- AspeedSoCState *s = (AspeedSoCState *)ctx;
+ AspeedCoprocessorState *s = (AspeedCoprocessorState *)ctx;
Aspeed27x0TSPSoCState *a = ASPEED27X0TSP_SOC(s);
- AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+ AspeedCoprocessorClass *sc = ASPEED_COPROCESSOR_GET_CLASS(s);
int or_idx;
int idx;
@@ -130,8 +131,8 @@ static qemu_irq aspeed_soc_ast27x0tsp_get_irq(void *ctx, int dev)
static void aspeed_soc_ast27x0tsp_init(Object *obj)
{
Aspeed27x0TSPSoCState *a = ASPEED27X0TSP_SOC(obj);
- AspeedSoCState *s = ASPEED_SOC(obj);
- AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+ AspeedCoprocessorState *s = ASPEED_COPROCESSOR(obj);
+ AspeedCoprocessorClass *sc = ASPEED_COPROCESSOR_GET_CLASS(s);
int i;
object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);
@@ -161,8 +162,8 @@ static void aspeed_soc_ast27x0tsp_init(Object *obj)
static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
{
Aspeed27x0TSPSoCState *a = ASPEED27X0TSP_SOC(dev_soc);
- AspeedSoCState *s = ASPEED_SOC(dev_soc);
- AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+ AspeedCoprocessorState *s = ASPEED_COPROCESSOR(dev_soc);
+ AspeedCoprocessorClass *sc = ASPEED_COPROCESSOR_GET_CLASS(s);
DeviceState *armv7m;
g_autofree char *sram_name = NULL;
int uart;
@@ -186,8 +187,8 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
sram_name = g_strdup_printf("aspeed.dram.%d",
CPU(a->armv7m.cpu)->cpu_index);
- if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size,
- errp)) {
+ if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name,
+ AST2700_TSP_RAM_SIZE, errp)) {
return;
}
memory_region_add_subregion(s->memory,
@@ -269,31 +270,25 @@ static void aspeed_soc_ast27x0tsp_class_init(ObjectClass *klass, const void *dat
NULL
};
DeviceClass *dc = DEVICE_CLASS(klass);
- AspeedSoCClass *sc = ASPEED_SOC_CLASS(dc);
+ AspeedCoprocessorClass *sc = ASPEED_COPROCESSOR_CLASS(dc);
- /* Reason: The Aspeed SoC can only be instantiated from a board */
+ /* Reason: The Aspeed Coprocessor can only be instantiated from a board */
dc->user_creatable = false;
dc->realize = aspeed_soc_ast27x0tsp_realize;
sc->valid_cpu_types = valid_cpu_types;
sc->silicon_rev = AST2700_A1_SILICON_REV;
- sc->sram_size = AST2700_TSP_RAM_SIZE;
- sc->spis_num = 0;
- sc->ehcis_num = 0;
- sc->wdts_num = 0;
- sc->macs_num = 0;
sc->uarts_num = 13;
sc->uarts_base = ASPEED_DEV_UART0;
sc->irqmap = aspeed_soc_ast27x0tsp_irqmap;
sc->memmap = aspeed_soc_ast27x0tsp_memmap;
- sc->num_cpus = 1;
sc->get_irq = aspeed_soc_ast27x0tsp_get_irq;
}
static const TypeInfo aspeed_soc_ast27x0tsp_types[] = {
{
.name = TYPE_ASPEED27X0TSP_SOC,
- .parent = TYPE_ASPEED_SOC,
+ .parent = TYPE_ASPEED_COPROCESSOR,
.instance_size = sizeof(Aspeed27x0TSPSoCState),
.instance_init = aspeed_soc_ast27x0tsp_init,
.class_init = aspeed_soc_ast27x0tsp_class_init,
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v1 12/16] hw/arm/aspeed_ast27x0-ssp: Change to use Aspeed27x0CoprocessorState
2025-10-08 3:21 [PATCH v1 00/16] Introduce AspeedCoprocessor class and base implementation Jamin Lin via
` (10 preceding siblings ...)
2025-10-08 3:21 ` [PATCH v1 11/16] hw/arm/aspeed_ast27x0-tsp: Make AST27x0 TSP " Jamin Lin via
@ 2025-10-08 3:21 ` Jamin Lin via
2025-10-08 3:21 ` [PATCH v1 13/16] hw/arm/aspeed_ast27x0-tsp: " Jamin Lin via
` (3 subsequent siblings)
15 siblings, 0 replies; 19+ messages in thread
From: Jamin Lin via @ 2025-10-08 3:21 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
Refactor the AST27x0 SSP implementation to use the unified
Aspeed27x0CoprocessorState structure shared between SSP and TSP.
Previously, SSP and TSP each defined separate state structures
(Aspeed27x0SSPSoCState and Aspeed27x0TSPSoCState), which contained
identical members and caused unnecessary code duplication.
This change removes Aspeed27x0SSPSoCState and replaces it with
Aspeed27x0CoprocessorState, consolidating shared coprocessor state fields
into a single definition in aspeed_coprocessor.h.
This refactor unifies SSP and TSP under the same coprocessor state type,
improving code maintainability and consistency across Aspeed coprocessor
implementations.
No functional change.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/arm/aspeed_coprocessor.h | 4 ++--
hw/arm/aspeed_ast27x0-fc.c | 2 +-
hw/arm/aspeed_ast27x0-ssp.c | 8 ++++----
3 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/include/hw/arm/aspeed_coprocessor.h b/include/hw/arm/aspeed_coprocessor.h
index 2c10327456..89e46100a5 100644
--- a/include/hw/arm/aspeed_coprocessor.h
+++ b/include/hw/arm/aspeed_coprocessor.h
@@ -42,7 +42,7 @@ struct AspeedCoprocessorClass {
qemu_irq (*get_irq)(void *ctx, int dev);
};
-struct Aspeed27x0SSPSoCState {
+struct Aspeed27x0CoprocessorState {
AspeedCoprocessorState parent;
AspeedINTCState intc[2];
UnimplementedDeviceState ipc[2];
@@ -52,7 +52,7 @@ struct Aspeed27x0SSPSoCState {
};
#define TYPE_ASPEED27X0SSP_SOC "aspeed27x0ssp-soc"
-OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SSPSoCState, ASPEED27X0SSP_SOC)
+OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0CoprocessorState, ASPEED27X0SSP_SOC)
struct Aspeed27x0TSPSoCState {
AspeedCoprocessorState parent;
diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
index b34cd54e4e..cd09a2dcf0 100644
--- a/hw/arm/aspeed_ast27x0-fc.c
+++ b/hw/arm/aspeed_ast27x0-fc.c
@@ -42,7 +42,7 @@ struct Ast2700FCState {
Clock *tsp_sysclk;
Aspeed27x0SoCState ca35;
- Aspeed27x0SSPSoCState ssp;
+ Aspeed27x0CoprocessorState ssp;
Aspeed27x0TSPSoCState tsp;
bool mmio_exec;
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
index 0e68c0f6a8..e3cf4e87f3 100644
--- a/hw/arm/aspeed_ast27x0-ssp.c
+++ b/hw/arm/aspeed_ast27x0-ssp.c
@@ -108,7 +108,7 @@ static struct nvic_intc_irq_info ast2700_ssp_intcmap[] = {
static qemu_irq aspeed_soc_ast27x0ssp_get_irq(void *ctx, int dev)
{
AspeedCoprocessorState *s = (AspeedCoprocessorState *)ctx;
- Aspeed27x0SSPSoCState *a = ASPEED27X0SSP_SOC(s);
+ Aspeed27x0CoprocessorState *a = ASPEED27X0SSP_SOC(s);
AspeedCoprocessorClass *sc = ASPEED_COPROCESSOR_GET_CLASS(s);
int or_idx;
@@ -130,7 +130,7 @@ static qemu_irq aspeed_soc_ast27x0ssp_get_irq(void *ctx, int dev)
static void aspeed_soc_ast27x0ssp_init(Object *obj)
{
- Aspeed27x0SSPSoCState *a = ASPEED27X0SSP_SOC(obj);
+ Aspeed27x0CoprocessorState *a = ASPEED27X0SSP_SOC(obj);
AspeedCoprocessorState *s = ASPEED_COPROCESSOR(obj);
AspeedCoprocessorClass *sc = ASPEED_COPROCESSOR_GET_CLASS(s);
int i;
@@ -161,7 +161,7 @@ static void aspeed_soc_ast27x0ssp_init(Object *obj)
static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
{
- Aspeed27x0SSPSoCState *a = ASPEED27X0SSP_SOC(dev_soc);
+ Aspeed27x0CoprocessorState *a = ASPEED27X0SSP_SOC(dev_soc);
AspeedCoprocessorState *s = ASPEED_COPROCESSOR(dev_soc);
AspeedCoprocessorClass *sc = ASPEED_COPROCESSOR_GET_CLASS(s);
DeviceState *armv7m;
@@ -289,7 +289,7 @@ static const TypeInfo aspeed_soc_ast27x0ssp_types[] = {
{
.name = TYPE_ASPEED27X0SSP_SOC,
.parent = TYPE_ASPEED_COPROCESSOR,
- .instance_size = sizeof(Aspeed27x0SSPSoCState),
+ .instance_size = sizeof(Aspeed27x0CoprocessorState),
.instance_init = aspeed_soc_ast27x0ssp_init,
.class_init = aspeed_soc_ast27x0ssp_class_init,
},
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v1 13/16] hw/arm/aspeed_ast27x0-tsp: Change to use Aspeed27x0CoprocessorState
2025-10-08 3:21 [PATCH v1 00/16] Introduce AspeedCoprocessor class and base implementation Jamin Lin via
` (11 preceding siblings ...)
2025-10-08 3:21 ` [PATCH v1 12/16] hw/arm/aspeed_ast27x0-ssp: Change to use Aspeed27x0CoprocessorState Jamin Lin via
@ 2025-10-08 3:21 ` Jamin Lin via
2025-10-08 3:21 ` [PATCH v1 14/16] hw/arm/aspeed_ast27x0-ssp: Rename type to TYPE_ASPEED27X0SSP_COPROCESSOR Jamin Lin via
` (2 subsequent siblings)
15 siblings, 0 replies; 19+ messages in thread
From: Jamin Lin via @ 2025-10-08 3:21 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
Refactor the AST27x0 TSP implementation to use the unified
Aspeed27x0CoprocessorState, matching the prior SSP change and removing the
duplicated Aspeed27x0TSPSoCState.
Key updates:
- Delete Aspeed27x0TSPSoCState and reuse Aspeed27x0CoprocessorState.
Update Ast2700FCState to declare tsp as Aspeed27x0CoprocessorState.
This aligns TSP with SSP on a single coprocessor state type, reducing code
duplication and simplifying maintenance.
No functional change.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/arm/aspeed_coprocessor.h | 12 ++----------
hw/arm/aspeed_ast27x0-fc.c | 2 +-
hw/arm/aspeed_ast27x0-tsp.c | 8 ++++----
3 files changed, 7 insertions(+), 15 deletions(-)
diff --git a/include/hw/arm/aspeed_coprocessor.h b/include/hw/arm/aspeed_coprocessor.h
index 89e46100a5..51c0e195f9 100644
--- a/include/hw/arm/aspeed_coprocessor.h
+++ b/include/hw/arm/aspeed_coprocessor.h
@@ -54,16 +54,8 @@ struct Aspeed27x0CoprocessorState {
#define TYPE_ASPEED27X0SSP_SOC "aspeed27x0ssp-soc"
OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0CoprocessorState, ASPEED27X0SSP_SOC)
-struct Aspeed27x0TSPSoCState {
- AspeedCoprocessorState parent;
- AspeedINTCState intc[2];
- UnimplementedDeviceState ipc[2];
- UnimplementedDeviceState scuio;
-
- ARMv7MState armv7m;
-};
-
#define TYPE_ASPEED27X0TSP_SOC "aspeed27x0tsp-soc"
-OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0TSPSoCState, ASPEED27X0TSP_SOC)
+DECLARE_OBJ_CHECKERS(Aspeed27x0CoprocessorState, AspeedCoprocessorClass,
+ ASPEED27X0TSP_SOC, TYPE_ASPEED27X0TSP_SOC)
#endif /* ASPEED_COPROCESSOR_H */
diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
index cd09a2dcf0..c2fa8df33c 100644
--- a/hw/arm/aspeed_ast27x0-fc.c
+++ b/hw/arm/aspeed_ast27x0-fc.c
@@ -43,7 +43,7 @@ struct Ast2700FCState {
Aspeed27x0SoCState ca35;
Aspeed27x0CoprocessorState ssp;
- Aspeed27x0TSPSoCState tsp;
+ Aspeed27x0CoprocessorState tsp;
bool mmio_exec;
};
diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c
index 8b13ab526d..c00f7d056c 100644
--- a/hw/arm/aspeed_ast27x0-tsp.c
+++ b/hw/arm/aspeed_ast27x0-tsp.c
@@ -108,7 +108,7 @@ static struct nvic_intc_irq_info ast2700_tsp_intcmap[] = {
static qemu_irq aspeed_soc_ast27x0tsp_get_irq(void *ctx, int dev)
{
AspeedCoprocessorState *s = (AspeedCoprocessorState *)ctx;
- Aspeed27x0TSPSoCState *a = ASPEED27X0TSP_SOC(s);
+ Aspeed27x0CoprocessorState *a = ASPEED27X0TSP_SOC(s);
AspeedCoprocessorClass *sc = ASPEED_COPROCESSOR_GET_CLASS(s);
int or_idx;
@@ -130,7 +130,7 @@ static qemu_irq aspeed_soc_ast27x0tsp_get_irq(void *ctx, int dev)
static void aspeed_soc_ast27x0tsp_init(Object *obj)
{
- Aspeed27x0TSPSoCState *a = ASPEED27X0TSP_SOC(obj);
+ Aspeed27x0CoprocessorState *a = ASPEED27X0TSP_SOC(obj);
AspeedCoprocessorState *s = ASPEED_COPROCESSOR(obj);
AspeedCoprocessorClass *sc = ASPEED_COPROCESSOR_GET_CLASS(s);
int i;
@@ -161,7 +161,7 @@ static void aspeed_soc_ast27x0tsp_init(Object *obj)
static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
{
- Aspeed27x0TSPSoCState *a = ASPEED27X0TSP_SOC(dev_soc);
+ Aspeed27x0CoprocessorState *a = ASPEED27X0TSP_SOC(dev_soc);
AspeedCoprocessorState *s = ASPEED_COPROCESSOR(dev_soc);
AspeedCoprocessorClass *sc = ASPEED_COPROCESSOR_GET_CLASS(s);
DeviceState *armv7m;
@@ -289,7 +289,7 @@ static const TypeInfo aspeed_soc_ast27x0tsp_types[] = {
{
.name = TYPE_ASPEED27X0TSP_SOC,
.parent = TYPE_ASPEED_COPROCESSOR,
- .instance_size = sizeof(Aspeed27x0TSPSoCState),
+ .instance_size = sizeof(Aspeed27x0CoprocessorState),
.instance_init = aspeed_soc_ast27x0tsp_init,
.class_init = aspeed_soc_ast27x0tsp_class_init,
},
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v1 14/16] hw/arm/aspeed_ast27x0-ssp: Rename type to TYPE_ASPEED27X0SSP_COPROCESSOR
2025-10-08 3:21 [PATCH v1 00/16] Introduce AspeedCoprocessor class and base implementation Jamin Lin via
` (12 preceding siblings ...)
2025-10-08 3:21 ` [PATCH v1 13/16] hw/arm/aspeed_ast27x0-tsp: " Jamin Lin via
@ 2025-10-08 3:21 ` Jamin Lin via
2025-10-08 3:22 ` [PATCH v1 15/16] hw/arm/aspeed_ast27x0-tsp: Rename type to TYPE_ASPEED27X0TSP_COPROCESSOR Jamin Lin via
2025-10-08 3:22 ` [PATCH v1 16/16] hw/arm/aspeed_ast27x0-{ssp,tsp}: Fix coding style Jamin Lin via
15 siblings, 0 replies; 19+ messages in thread
From: Jamin Lin via @ 2025-10-08 3:21 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
Rename the AST27x0 SSP type from TYPE_ASPEED27X0SSP_SOC to
TYPE_ASPEED27X0SSP_COPROCESSOR to better reflect its role as a coprocessor
rather than a standalone SoC. This aligns naming conventions with the
coprocessor-based design introduced in earlier refactors.
This change improves naming consistency across SSP and TSP coprocessor
implementations and clarifies their relationship to the unified
Aspeed27x0CoprocessorState.
No functional change.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/arm/aspeed_coprocessor.h | 5 +++--
hw/arm/aspeed_ast27x0-fc.c | 3 ++-
hw/arm/aspeed_ast27x0-ssp.c | 10 +++++-----
3 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/include/hw/arm/aspeed_coprocessor.h b/include/hw/arm/aspeed_coprocessor.h
index 51c0e195f9..77159c230b 100644
--- a/include/hw/arm/aspeed_coprocessor.h
+++ b/include/hw/arm/aspeed_coprocessor.h
@@ -51,8 +51,9 @@ struct Aspeed27x0CoprocessorState {
ARMv7MState armv7m;
};
-#define TYPE_ASPEED27X0SSP_SOC "aspeed27x0ssp-soc"
-OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0CoprocessorState, ASPEED27X0SSP_SOC)
+#define TYPE_ASPEED27X0SSP_COPROCESSOR "aspeed27x0ssp-coprocessor"
+OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0CoprocessorState,
+ ASPEED27X0SSP_COPROCESSOR)
#define TYPE_ASPEED27X0TSP_SOC "aspeed27x0tsp-soc"
DECLARE_OBJ_CHECKERS(Aspeed27x0CoprocessorState, AspeedCoprocessorClass,
diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
index c2fa8df33c..67982d2fa0 100644
--- a/hw/arm/aspeed_ast27x0-fc.c
+++ b/hw/arm/aspeed_ast27x0-fc.c
@@ -121,7 +121,8 @@ static bool ast2700fc_ssp_init(MachineState *machine, Error **errp)
s->ssp_sysclk = clock_new(OBJECT(s), "SSP_SYSCLK");
clock_set_hz(s->ssp_sysclk, 200000000ULL);
- object_initialize_child(OBJECT(s), "ssp", &s->ssp, TYPE_ASPEED27X0SSP_SOC);
+ object_initialize_child(OBJECT(s), "ssp", &s->ssp,
+ TYPE_ASPEED27X0SSP_COPROCESSOR);
memory_region_init(&s->ssp_memory, OBJECT(&s->ssp), "ssp-memory",
UINT64_MAX);
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
index e3cf4e87f3..a0b8289c35 100644
--- a/hw/arm/aspeed_ast27x0-ssp.c
+++ b/hw/arm/aspeed_ast27x0-ssp.c
@@ -1,5 +1,5 @@
/*
- * ASPEED Ast27x0 SSP SoC
+ * ASPEED Ast27x0 SSP Coprocessor
*
* Copyright (C) 2025 ASPEED Technology Inc.
*
@@ -108,7 +108,7 @@ static struct nvic_intc_irq_info ast2700_ssp_intcmap[] = {
static qemu_irq aspeed_soc_ast27x0ssp_get_irq(void *ctx, int dev)
{
AspeedCoprocessorState *s = (AspeedCoprocessorState *)ctx;
- Aspeed27x0CoprocessorState *a = ASPEED27X0SSP_SOC(s);
+ Aspeed27x0CoprocessorState *a = ASPEED27X0SSP_COPROCESSOR(s);
AspeedCoprocessorClass *sc = ASPEED_COPROCESSOR_GET_CLASS(s);
int or_idx;
@@ -130,7 +130,7 @@ static qemu_irq aspeed_soc_ast27x0ssp_get_irq(void *ctx, int dev)
static void aspeed_soc_ast27x0ssp_init(Object *obj)
{
- Aspeed27x0CoprocessorState *a = ASPEED27X0SSP_SOC(obj);
+ Aspeed27x0CoprocessorState *a = ASPEED27X0SSP_COPROCESSOR(obj);
AspeedCoprocessorState *s = ASPEED_COPROCESSOR(obj);
AspeedCoprocessorClass *sc = ASPEED_COPROCESSOR_GET_CLASS(s);
int i;
@@ -161,7 +161,7 @@ static void aspeed_soc_ast27x0ssp_init(Object *obj)
static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
{
- Aspeed27x0CoprocessorState *a = ASPEED27X0SSP_SOC(dev_soc);
+ Aspeed27x0CoprocessorState *a = ASPEED27X0SSP_COPROCESSOR(dev_soc);
AspeedCoprocessorState *s = ASPEED_COPROCESSOR(dev_soc);
AspeedCoprocessorClass *sc = ASPEED_COPROCESSOR_GET_CLASS(s);
DeviceState *armv7m;
@@ -287,7 +287,7 @@ static void aspeed_soc_ast27x0ssp_class_init(ObjectClass *klass, const void *dat
static const TypeInfo aspeed_soc_ast27x0ssp_types[] = {
{
- .name = TYPE_ASPEED27X0SSP_SOC,
+ .name = TYPE_ASPEED27X0SSP_COPROCESSOR,
.parent = TYPE_ASPEED_COPROCESSOR,
.instance_size = sizeof(Aspeed27x0CoprocessorState),
.instance_init = aspeed_soc_ast27x0ssp_init,
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v1 15/16] hw/arm/aspeed_ast27x0-tsp: Rename type to TYPE_ASPEED27X0TSP_COPROCESSOR
2025-10-08 3:21 [PATCH v1 00/16] Introduce AspeedCoprocessor class and base implementation Jamin Lin via
` (13 preceding siblings ...)
2025-10-08 3:21 ` [PATCH v1 14/16] hw/arm/aspeed_ast27x0-ssp: Rename type to TYPE_ASPEED27X0SSP_COPROCESSOR Jamin Lin via
@ 2025-10-08 3:22 ` Jamin Lin via
2025-10-08 3:22 ` [PATCH v1 16/16] hw/arm/aspeed_ast27x0-{ssp,tsp}: Fix coding style Jamin Lin via
15 siblings, 0 replies; 19+ messages in thread
From: Jamin Lin via @ 2025-10-08 3:22 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
Rename the AST27x0 TSP type from TYPE_ASPEED27X0TSP_SOC to
TYPE_ASPEED27X0TSP_COPROCESSOR to align with the naming convention used
for the SSP coprocessor (TYPE_ASPEED27X0SSP_COPROCESSOR).
This change clarifies that TSP is implemented as a coprocessor rather than
a full SoC.
This ensures consistent terminology between SSP and TSP components and
improves clarity within the coprocessor subsystem code.
No functional change.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/arm/aspeed_coprocessor.h | 4 ++--
hw/arm/aspeed_ast27x0-fc.c | 3 ++-
hw/arm/aspeed_ast27x0-tsp.c | 10 +++++-----
3 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/include/hw/arm/aspeed_coprocessor.h b/include/hw/arm/aspeed_coprocessor.h
index 77159c230b..d274e8e20e 100644
--- a/include/hw/arm/aspeed_coprocessor.h
+++ b/include/hw/arm/aspeed_coprocessor.h
@@ -55,8 +55,8 @@ struct Aspeed27x0CoprocessorState {
OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0CoprocessorState,
ASPEED27X0SSP_COPROCESSOR)
-#define TYPE_ASPEED27X0TSP_SOC "aspeed27x0tsp-soc"
+#define TYPE_ASPEED27X0TSP_COPROCESSOR "aspeed27x0tsp-coprocessor"
DECLARE_OBJ_CHECKERS(Aspeed27x0CoprocessorState, AspeedCoprocessorClass,
- ASPEED27X0TSP_SOC, TYPE_ASPEED27X0TSP_SOC)
+ ASPEED27X0TSP_COPROCESSOR, TYPE_ASPEED27X0TSP_COPROCESSOR)
#endif /* ASPEED_COPROCESSOR_H */
diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
index 67982d2fa0..a61ecff390 100644
--- a/hw/arm/aspeed_ast27x0-fc.c
+++ b/hw/arm/aspeed_ast27x0-fc.c
@@ -149,7 +149,8 @@ static bool ast2700fc_tsp_init(MachineState *machine, Error **errp)
s->tsp_sysclk = clock_new(OBJECT(s), "TSP_SYSCLK");
clock_set_hz(s->tsp_sysclk, 200000000ULL);
- object_initialize_child(OBJECT(s), "tsp", &s->tsp, TYPE_ASPEED27X0TSP_SOC);
+ object_initialize_child(OBJECT(s), "tsp", &s->tsp,
+ TYPE_ASPEED27X0TSP_COPROCESSOR);
memory_region_init(&s->tsp_memory, OBJECT(&s->tsp), "tsp-memory",
UINT64_MAX);
diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c
index c00f7d056c..8d3d457919 100644
--- a/hw/arm/aspeed_ast27x0-tsp.c
+++ b/hw/arm/aspeed_ast27x0-tsp.c
@@ -1,5 +1,5 @@
/*
- * ASPEED Ast27x0 TSP SoC
+ * ASPEED Ast27x0 TSP Coprocessor
*
* Copyright (C) 2025 ASPEED Technology Inc.
*
@@ -108,7 +108,7 @@ static struct nvic_intc_irq_info ast2700_tsp_intcmap[] = {
static qemu_irq aspeed_soc_ast27x0tsp_get_irq(void *ctx, int dev)
{
AspeedCoprocessorState *s = (AspeedCoprocessorState *)ctx;
- Aspeed27x0CoprocessorState *a = ASPEED27X0TSP_SOC(s);
+ Aspeed27x0CoprocessorState *a = ASPEED27X0TSP_COPROCESSOR(s);
AspeedCoprocessorClass *sc = ASPEED_COPROCESSOR_GET_CLASS(s);
int or_idx;
@@ -130,7 +130,7 @@ static qemu_irq aspeed_soc_ast27x0tsp_get_irq(void *ctx, int dev)
static void aspeed_soc_ast27x0tsp_init(Object *obj)
{
- Aspeed27x0CoprocessorState *a = ASPEED27X0TSP_SOC(obj);
+ Aspeed27x0CoprocessorState *a = ASPEED27X0TSP_COPROCESSOR(obj);
AspeedCoprocessorState *s = ASPEED_COPROCESSOR(obj);
AspeedCoprocessorClass *sc = ASPEED_COPROCESSOR_GET_CLASS(s);
int i;
@@ -161,7 +161,7 @@ static void aspeed_soc_ast27x0tsp_init(Object *obj)
static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
{
- Aspeed27x0CoprocessorState *a = ASPEED27X0TSP_SOC(dev_soc);
+ Aspeed27x0CoprocessorState *a = ASPEED27X0TSP_COPROCESSOR(dev_soc);
AspeedCoprocessorState *s = ASPEED_COPROCESSOR(dev_soc);
AspeedCoprocessorClass *sc = ASPEED_COPROCESSOR_GET_CLASS(s);
DeviceState *armv7m;
@@ -287,7 +287,7 @@ static void aspeed_soc_ast27x0tsp_class_init(ObjectClass *klass, const void *dat
static const TypeInfo aspeed_soc_ast27x0tsp_types[] = {
{
- .name = TYPE_ASPEED27X0TSP_SOC,
+ .name = TYPE_ASPEED27X0TSP_COPROCESSOR,
.parent = TYPE_ASPEED_COPROCESSOR,
.instance_size = sizeof(Aspeed27x0CoprocessorState),
.instance_init = aspeed_soc_ast27x0tsp_init,
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v1 16/16] hw/arm/aspeed_ast27x0-{ssp,tsp}: Fix coding style
2025-10-08 3:21 [PATCH v1 00/16] Introduce AspeedCoprocessor class and base implementation Jamin Lin via
` (14 preceding siblings ...)
2025-10-08 3:22 ` [PATCH v1 15/16] hw/arm/aspeed_ast27x0-tsp: Rename type to TYPE_ASPEED27X0TSP_COPROCESSOR Jamin Lin via
@ 2025-10-08 3:22 ` Jamin Lin via
15 siblings, 0 replies; 19+ messages in thread
From: Jamin Lin via @ 2025-10-08 3:22 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
Fix coding style warnings in aspeed_ast27x0-ssp.c and aspeed_ast27x0-tsp.c
reported by checkpatch.pl regarding line length exceeding 80 characters.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed_ast27x0-ssp.c | 3 ++-
hw/arm/aspeed_ast27x0-tsp.c | 3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
index a0b8289c35..6800d7b6b2 100644
--- a/hw/arm/aspeed_ast27x0-ssp.c
+++ b/hw/arm/aspeed_ast27x0-ssp.c
@@ -263,7 +263,8 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
sc->memmap[ASPEED_DEV_SCUIO], 0x1000);
}
-static void aspeed_soc_ast27x0ssp_class_init(ObjectClass *klass, const void *data)
+static void aspeed_soc_ast27x0ssp_class_init(ObjectClass *klass,
+ const void *data)
{
static const char * const valid_cpu_types[] = {
ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO: cortex-m4f */
diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c
index 8d3d457919..e409d94e28 100644
--- a/hw/arm/aspeed_ast27x0-tsp.c
+++ b/hw/arm/aspeed_ast27x0-tsp.c
@@ -263,7 +263,8 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
sc->memmap[ASPEED_DEV_SCUIO], 0x1000);
}
-static void aspeed_soc_ast27x0tsp_class_init(ObjectClass *klass, const void *data)
+static void aspeed_soc_ast27x0tsp_class_init(ObjectClass *klass,
+ const void *data)
{
static const char * const valid_cpu_types[] = {
ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO cortex-m4f */
--
2.43.0
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