[PATCH 0/5] target/microblaze: Remove all uses of target_ulong type

[PATCH 0/5] target/microblaze: Remove all uses of target_ulong type

[Philippe Mathieu-Daudé]

Remove the left over target_ulong uses in MicroBlaze frontend.

Philippe Mathieu-Daudé (5):
  target/microblaze: Remove target_ulong use in cpu_handle_mmu_fault()
  target/microblaze: Remove target_ulong uses in
    get_phys_page_attrs_debug
  target/microblaze: Remove target_ulong use in gen_goto_tb()
  target/microblaze: Remove target_ulong use in helper_stackprot()
  target/microblaze: Convert CPUMBState::res_addr field to uint32_t type

 target/microblaze/cpu.h       |  2 +-
 target/microblaze/helper.h    |  2 +-
 target/microblaze/mmu.h       |  2 +-
 target/microblaze/helper.c    |  3 ++-
 target/microblaze/machine.c   |  6 +++---
 target/microblaze/mmu.c       |  4 ++--
 target/microblaze/op_helper.c |  4 ++--
 target/microblaze/translate.c | 19 ++++++++++---------
 8 files changed, 22 insertions(+), 20 deletions(-)

-- 
2.51.0

[PATCH 1/5] target/microblaze: Remove target_ulong use in cpu_handle_mmu_fault()

[Philippe Mathieu-Daudé]

cpu_handle_mmu_fault() -- renamed in commit f429d607c71 -- expects
a vaddr type for its address argument since commit 7510454e3e7
("cpu: Turn cpu_handle_mmu_fault() into a CPUClass hook").

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/microblaze/mmu.h | 2 +-
 target/microblaze/mmu.c | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/target/microblaze/mmu.h b/target/microblaze/mmu.h
index 1068bd2d52b..2aca39c923b 100644
--- a/target/microblaze/mmu.h
+++ b/target/microblaze/mmu.h
@@ -86,7 +86,7 @@ typedef struct {
 } MicroBlazeMMULookup;
 
 unsigned int mmu_translate(MicroBlazeCPU *cpu, MicroBlazeMMULookup *lu,
-                           target_ulong vaddr, MMUAccessType rw, int mmu_idx);
+                           vaddr vaddr, MMUAccessType rw, int mmu_idx);
 uint32_t mmu_read(CPUMBState *env, bool ea, uint32_t rn);
 void mmu_write(CPUMBState *env, bool ea, uint32_t rn, uint32_t v);
 void mmu_init(MicroBlazeMMU *mmu);
diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c
index 8703ff5c657..db24cb399ce 100644
--- a/target/microblaze/mmu.c
+++ b/target/microblaze/mmu.c
@@ -78,7 +78,7 @@ static void mmu_change_pid(CPUMBState *env, unsigned int newpid)
 
 /* rw - 0 = read, 1 = write, 2 = fetch.  */
 unsigned int mmu_translate(MicroBlazeCPU *cpu, MicroBlazeMMULookup *lu,
-                           target_ulong vaddr, MMUAccessType rw, int mmu_idx)
+                           vaddr vaddr, MMUAccessType rw, int mmu_idx)
 {
     MicroBlazeMMU *mmu = &cpu->env.mmu;
     unsigned int i, hit = 0;
@@ -172,7 +172,7 @@ unsigned int mmu_translate(MicroBlazeCPU *cpu, MicroBlazeMMULookup *lu,
     }
 done:
     qemu_log_mask(CPU_LOG_MMU,
-                  "MMU vaddr=0x" TARGET_FMT_lx
+                  "MMU vaddr=0x%" VADDR_PRIx
                   " rw=%d tlb_wr=%d tlb_ex=%d hit=%d\n",
                   vaddr, rw, tlb_wr, tlb_ex, hit);
     return hit;
-- 
2.51.0

[PATCH 2/5] target/microblaze: Remove target_ulong uses in get_phys_page_attrs_debug

[Philippe Mathieu-Daudé]

The CPUClass::get_phys_page_debug() handler takes a 'vaddr' address
and return a 'hwaddr' type since commit 00b941e581b ("cpu: Turn
cpu_get_phys_page_debug() into a CPUClass hook").

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/microblaze/helper.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c
index ef0e2f973fa..cf577a72268 100644
--- a/target/microblaze/helper.c
+++ b/target/microblaze/helper.c
@@ -274,7 +274,8 @@ hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
                                         MemTxAttrs *attrs)
 {
     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
-    target_ulong vaddr, paddr = 0;
+    vaddr vaddr;
+    hwaddr paddr = 0;
     MicroBlazeMMULookup lu;
     int mmu_idx = cpu_mmu_index(cs, false);
     unsigned int hit;
-- 
2.51.0

[PATCH 3/5] target/microblaze: Remove target_ulong use in gen_goto_tb()

[Philippe Mathieu-Daudé]

translator_use_goto_tb() expects a vaddr type since commit
b1c09220b4c ("accel/tcg: Replace target_ulong with vaddr in
translator_*()").

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/microblaze/translate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 5098a1db4dc..ff33e64a710 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -116,7 +116,7 @@ static void gen_raise_hw_excp(DisasContext *dc, uint32_t esr_ec)
     gen_raise_exception_sync(dc, EXCP_HW_EXCP);
 }
 
-static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
+static void gen_goto_tb(DisasContext *dc, int n, vaddr dest)
 {
     if (translator_use_goto_tb(&dc->base, dest)) {
         tcg_gen_goto_tb(n);
-- 
2.51.0

[PATCH 4/5] target/microblaze: Remove target_ulong use in helper_stackprot()

[Philippe Mathieu-Daudé]

Since commit 36a9529e60e ("target/microblaze: Simplify
compute_ldst_addr_type{a,b}"), helper_stackprot() takes
a TCGv_i32 argument.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/microblaze/helper.h    | 2 +-
 target/microblaze/op_helper.c | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h
index ef4fad9b91e..01eba592b26 100644
--- a/target/microblaze/helper.h
+++ b/target/microblaze/helper.h
@@ -20,7 +20,7 @@ DEF_HELPER_FLAGS_3(fcmp_ne, TCG_CALL_NO_WG, i32, env, i32, i32)
 DEF_HELPER_FLAGS_3(fcmp_ge, TCG_CALL_NO_WG, i32, env, i32, i32)
 
 DEF_HELPER_FLAGS_2(pcmpbf, TCG_CALL_NO_RWG_SE, i32, i32, i32)
-DEF_HELPER_FLAGS_2(stackprot, TCG_CALL_NO_WG, void, env, tl)
+DEF_HELPER_FLAGS_2(stackprot, TCG_CALL_NO_WG, void, env, i32)
 DEF_HELPER_FLAGS_2(get, TCG_CALL_NO_RWG, i32, i32, i32)
 DEF_HELPER_FLAGS_3(put, TCG_CALL_NO_RWG, void, i32, i32, i32)
 
diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c
index b8365b3b1d2..df93c4229d6 100644
--- a/target/microblaze/op_helper.c
+++ b/target/microblaze/op_helper.c
@@ -365,13 +365,13 @@ uint32_t helper_pcmpbf(uint32_t a, uint32_t b)
     return 0;
 }
 
-void helper_stackprot(CPUMBState *env, target_ulong addr)
+void helper_stackprot(CPUMBState *env, uint32_t addr)
 {
     if (addr < env->slr || addr > env->shr) {
         CPUState *cs = env_cpu(env);
 
         qemu_log_mask(CPU_LOG_INT, "Stack protector violation at "
-                      TARGET_FMT_lx " %x %x\n",
+                                   "0x%x 0x%x 0x%x\n",
                       addr, env->slr, env->shr);
 
         env->ear = addr;
-- 
2.51.0

[PATCH 5/5] target/microblaze: Convert CPUMBState::res_addr field to uint32_t type

[Philippe Mathieu-Daudé]

CPUMBState::@res_addr field is used as u32 since commit
cfeea807e5a ("target-microblaze: Tighten up TCGv_i32 vs
TCGv type usage"). Convert it as such, bumping the migration
version. Use the RES_ADDR_NONE definition when appropriate.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/microblaze/cpu.h       |  2 +-
 target/microblaze/machine.c   |  6 +++---
 target/microblaze/translate.c | 17 +++++++++--------
 3 files changed, 13 insertions(+), 12 deletions(-)

diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 3ce28b302fe..14b107876a4 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -259,7 +259,7 @@ struct CPUArchState {
 
     /* lwx/swx reserved address */
 #define RES_ADDR_NONE 0xffffffff /* Use 0xffffffff to indicate no reservation */
-    target_ulong res_addr;
+    uint32_t res_addr;
     uint32_t res_val;
 
     /* Internal flags.  */
diff --git a/target/microblaze/machine.c b/target/microblaze/machine.c
index a4cf38dc891..48efa546d39 100644
--- a/target/microblaze/machine.c
+++ b/target/microblaze/machine.c
@@ -78,7 +78,7 @@ static const VMStateField vmstate_env_fields[] = {
     VMSTATE_UINT32(iflags, CPUMBState),
 
     VMSTATE_UINT32(res_val, CPUMBState),
-    VMSTATE_UINTTL(res_addr, CPUMBState),
+    VMSTATE_UINT32(res_addr, CPUMBState),
 
     VMSTATE_STRUCT(mmu, CPUMBState, 0, vmstate_mmu, MicroBlazeMMU),
 
@@ -87,8 +87,8 @@ static const VMStateField vmstate_env_fields[] = {
 
 static const VMStateDescription vmstate_env = {
     .name = "env",
-    .version_id = 0,
-    .minimum_version_id = 0,
+    .version_id = 1,
+    .minimum_version_id = 1,
     .fields = vmstate_env_fields,
 };
 
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index ff33e64a710..04fbd4fe17f 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -55,7 +55,7 @@ static TCGv_i32 cpu_imm;
 static TCGv_i32 cpu_bvalue;
 static TCGv_i32 cpu_btarget;
 static TCGv_i32 cpu_iflags;
-static TCGv cpu_res_addr;
+static TCGv_i32 cpu_res_addr;
 static TCGv_i32 cpu_res_val;
 
 /* This is the state at translation time.  */
@@ -857,7 +857,7 @@ static bool trans_lwx(DisasContext *dc, arg_typea *arg)
 
     tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index,
                         mo_endian(dc) | MO_UL);
-    tcg_gen_mov_tl(cpu_res_addr, addr);
+    tcg_gen_mov_i32(cpu_res_addr, addr);
 
     if (arg->rd) {
         tcg_gen_mov_i32(cpu_R[arg->rd], cpu_res_val);
@@ -1024,7 +1024,7 @@ static bool trans_swx(DisasContext *dc, arg_typea *arg)
      * branch, but we know we can use the equal version in the global.
      * In either case, addr is no longer needed.
      */
-    tcg_gen_brcond_tl(TCG_COND_NE, cpu_res_addr, addr, swx_fail);
+    tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_addr, addr, swx_fail);
 
     /*
      * Compare the value loaded during lwx with current contents of
@@ -1052,7 +1052,7 @@ static bool trans_swx(DisasContext *dc, arg_typea *arg)
      * Prevent the saved address from working again without another ldx.
      * Akin to the pseudocode setting reservation = 0.
      */
-    tcg_gen_movi_tl(cpu_res_addr, -1);
+    tcg_gen_movi_i32(cpu_res_addr, RES_ADDR_NONE);
     return true;
 }
 
@@ -1173,7 +1173,7 @@ static bool trans_brk(DisasContext *dc, arg_typea_br *arg)
         tcg_gen_movi_i32(cpu_R[arg->rd], dc->base.pc_next);
     }
     tcg_gen_ori_i32(cpu_msr, cpu_msr, MSR_BIP);
-    tcg_gen_movi_tl(cpu_res_addr, -1);
+    tcg_gen_movi_i32(cpu_res_addr, RES_ADDR_NONE);
 
     dc->base.is_jmp = DISAS_EXIT;
     return true;
@@ -1194,7 +1194,7 @@ static bool trans_brki(DisasContext *dc, arg_typeb_br *arg)
     if (arg->rd) {
         tcg_gen_movi_i32(cpu_R[arg->rd], dc->base.pc_next);
     }
-    tcg_gen_movi_tl(cpu_res_addr, -1);
+    tcg_gen_movi_i32(cpu_res_addr, RES_ADDR_NONE);
 
 #ifdef CONFIG_USER_ONLY
     switch (imm) {
@@ -1885,6 +1885,7 @@ void mb_tcg_init(void)
           tcg_global_mem_new_i32(tcg_env, i32s[i].ofs, i32s[i].name);
     }
 
-    cpu_res_addr =
-        tcg_global_mem_new(tcg_env, offsetof(CPUMBState, res_addr), "res_addr");
+    cpu_res_addr = tcg_global_mem_new_i32(tcg_env,
+                                          offsetof(CPUMBState, res_addr),
+                                          "res_addr");
 }
-- 
2.51.0

Re: [PATCH 1/5] target/microblaze: Remove target_ulong use in cpu_handle_mmu_fault()

[Anton Johansson via]

On 08/10/25, Philippe Mathieu-Daudé wrote:
> cpu_handle_mmu_fault() -- renamed in commit f429d607c71 -- expects
> a vaddr type for its address argument since commit 7510454e3e7
> ("cpu: Turn cpu_handle_mmu_fault() into a CPUClass hook").
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/microblaze/mmu.h | 2 +-
>  target/microblaze/mmu.c | 4 ++--
>  2 files changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/target/microblaze/mmu.h b/target/microblaze/mmu.h
> index 1068bd2d52b..2aca39c923b 100644
> --- a/target/microblaze/mmu.h
> +++ b/target/microblaze/mmu.h
> @@ -86,7 +86,7 @@ typedef struct {
>  } MicroBlazeMMULookup;
>  
>  unsigned int mmu_translate(MicroBlazeCPU *cpu, MicroBlazeMMULookup *lu,
> -                           target_ulong vaddr, MMUAccessType rw, int mmu_idx);
> +                           vaddr vaddr, MMUAccessType rw, int mmu_idx);
>  uint32_t mmu_read(CPUMBState *env, bool ea, uint32_t rn);
>  void mmu_write(CPUMBState *env, bool ea, uint32_t rn, uint32_t v);
>  void mmu_init(MicroBlazeMMU *mmu);
> diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c
> index 8703ff5c657..db24cb399ce 100644
> --- a/target/microblaze/mmu.c
> +++ b/target/microblaze/mmu.c
> @@ -78,7 +78,7 @@ static void mmu_change_pid(CPUMBState *env, unsigned int newpid)
>  
>  /* rw - 0 = read, 1 = write, 2 = fetch.  */
>  unsigned int mmu_translate(MicroBlazeCPU *cpu, MicroBlazeMMULookup *lu,
> -                           target_ulong vaddr, MMUAccessType rw, int mmu_idx)
> +                           vaddr vaddr, MMUAccessType rw, int mmu_idx)

`vaddr vaddr` looks a bit awkward, but very nitty and not like it really matters.

Reviewed-by: Anton Johansson <anjo@rev.ng>

Re: [PATCH 3/5] target/microblaze: Remove target_ulong use in gen_goto_tb()

[Anton Johansson via]

On 08/10/25, Philippe Mathieu-Daudé wrote:
> translator_use_goto_tb() expects a vaddr type since commit
> b1c09220b4c ("accel/tcg: Replace target_ulong with vaddr in
> translator_*()").
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/microblaze/translate.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
> index 5098a1db4dc..ff33e64a710 100644
> --- a/target/microblaze/translate.c
> +++ b/target/microblaze/translate.c
> @@ -116,7 +116,7 @@ static void gen_raise_hw_excp(DisasContext *dc, uint32_t esr_ec)
>      gen_raise_exception_sync(dc, EXCP_HW_EXCP);
>  }
>  
> -static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
> +static void gen_goto_tb(DisasContext *dc, int n, vaddr dest)
>  {
>      if (translator_use_goto_tb(&dc->base, dest)) {
>          tcg_gen_goto_tb(n);
> -- 
> 2.51.0
> 

Reviewed-by: Anton Johansson <anjo@rev.ng>

Re: [PATCH 4/5] target/microblaze: Remove target_ulong use in helper_stackprot()

[Anton Johansson via]

On 08/10/25, Philippe Mathieu-Daudé wrote:
> Since commit 36a9529e60e ("target/microblaze: Simplify
> compute_ldst_addr_type{a,b}"), helper_stackprot() takes
> a TCGv_i32 argument.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/microblaze/helper.h    | 2 +-
>  target/microblaze/op_helper.c | 4 ++--
>  2 files changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h
> index ef4fad9b91e..01eba592b26 100644
> --- a/target/microblaze/helper.h
> +++ b/target/microblaze/helper.h
> @@ -20,7 +20,7 @@ DEF_HELPER_FLAGS_3(fcmp_ne, TCG_CALL_NO_WG, i32, env, i32, i32)
>  DEF_HELPER_FLAGS_3(fcmp_ge, TCG_CALL_NO_WG, i32, env, i32, i32)
>  
>  DEF_HELPER_FLAGS_2(pcmpbf, TCG_CALL_NO_RWG_SE, i32, i32, i32)
> -DEF_HELPER_FLAGS_2(stackprot, TCG_CALL_NO_WG, void, env, tl)
> +DEF_HELPER_FLAGS_2(stackprot, TCG_CALL_NO_WG, void, env, i32)
>  DEF_HELPER_FLAGS_2(get, TCG_CALL_NO_RWG, i32, i32, i32)
>  DEF_HELPER_FLAGS_3(put, TCG_CALL_NO_RWG, void, i32, i32, i32)
>  
> diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c
> index b8365b3b1d2..df93c4229d6 100644
> --- a/target/microblaze/op_helper.c
> +++ b/target/microblaze/op_helper.c
> @@ -365,13 +365,13 @@ uint32_t helper_pcmpbf(uint32_t a, uint32_t b)
>      return 0;
>  }
>  
> -void helper_stackprot(CPUMBState *env, target_ulong addr)
> +void helper_stackprot(CPUMBState *env, uint32_t addr)
>  {
>      if (addr < env->slr || addr > env->shr) {
>          CPUState *cs = env_cpu(env);
>  
>          qemu_log_mask(CPU_LOG_INT, "Stack protector violation at "
> -                      TARGET_FMT_lx " %x %x\n",
> +                                   "0x%x 0x%x 0x%x\n",
>                        addr, env->slr, env->shr);
>  
>          env->ear = addr;
> -- 
> 2.51.0
> 

Might as well update call sites to gen_helper_stackprot() as well.
compute_ldst_addr_type[ab]() calls into gen_helper_stackprot() but
returns TCGv.  That return value is passed to do_load() and
do_store() as TCGv, but the bodies of these function clearly expect
TCG_i32.

Otherwise

Reviewed-by: Anton Johansson <anjo@rev.ng>

Re: [PATCH 5/5] target/microblaze: Convert CPUMBState::res_addr field to uint32_t type

[Anton Johansson via]

On 08/10/25, Philippe Mathieu-Daudé wrote:
> CPUMBState::@res_addr field is used as u32 since commit
> cfeea807e5a ("target-microblaze: Tighten up TCGv_i32 vs
> TCGv type usage"). Convert it as such, bumping the migration
> version. Use the RES_ADDR_NONE definition when appropriate.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/microblaze/cpu.h       |  2 +-
>  target/microblaze/machine.c   |  6 +++---
>  target/microblaze/translate.c | 17 +++++++++--------
>  3 files changed, 13 insertions(+), 12 deletions(-)

Reviewed-by: Anton Johansson <anjo@rev.ng>

Re: [PATCH 1/5] target/microblaze: Remove target_ulong use in cpu_handle_mmu_fault()

[Pierrick Bouvier]

On 10/7/25 11:01 PM, Philippe Mathieu-Daudé wrote:
> cpu_handle_mmu_fault() -- renamed in commit f429d607c71 -- expects
> a vaddr type for its address argument since commit 7510454e3e7
> ("cpu: Turn cpu_handle_mmu_fault() into a CPUClass hook").
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/microblaze/mmu.h | 2 +-
>   target/microblaze/mmu.c | 4 ++--
>   2 files changed, 3 insertions(+), 3 deletions(-)

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>

Re: [PATCH 2/5] target/microblaze: Remove target_ulong uses in get_phys_page_attrs_debug

[Pierrick Bouvier]

On 10/7/25 11:01 PM, Philippe Mathieu-Daudé wrote:
> The CPUClass::get_phys_page_debug() handler takes a 'vaddr' address
> and return a 'hwaddr' type since commit 00b941e581b ("cpu: Turn
> cpu_get_phys_page_debug() into a CPUClass hook").
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/microblaze/helper.c | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c
> index ef0e2f973fa..cf577a72268 100644
> --- a/target/microblaze/helper.c
> +++ b/target/microblaze/helper.c
> @@ -274,7 +274,8 @@ hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
>                                           MemTxAttrs *attrs)
>   {
>       MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
> -    target_ulong vaddr, paddr = 0;
> +    vaddr vaddr;
> +    hwaddr paddr = 0;
>       MicroBlazeMMULookup lu;
>       int mmu_idx = cpu_mmu_index(cs, false);
>       unsigned int hit;

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>

Re: [PATCH 3/5] target/microblaze: Remove target_ulong use in gen_goto_tb()

[Pierrick Bouvier]

On 10/7/25 11:01 PM, Philippe Mathieu-Daudé wrote:
> translator_use_goto_tb() expects a vaddr type since commit
> b1c09220b4c ("accel/tcg: Replace target_ulong with vaddr in
> translator_*()").
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/microblaze/translate.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
> index 5098a1db4dc..ff33e64a710 100644
> --- a/target/microblaze/translate.c
> +++ b/target/microblaze/translate.c
> @@ -116,7 +116,7 @@ static void gen_raise_hw_excp(DisasContext *dc, uint32_t esr_ec)
>       gen_raise_exception_sync(dc, EXCP_HW_EXCP);
>   }
>   
> -static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
> +static void gen_goto_tb(DisasContext *dc, int n, vaddr dest)
>   {
>       if (translator_use_goto_tb(&dc->base, dest)) {
>           tcg_gen_goto_tb(n);

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>

Re: [PATCH 4/5] target/microblaze: Remove target_ulong use in helper_stackprot()

[Pierrick Bouvier]

On 10/7/25 11:01 PM, Philippe Mathieu-Daudé wrote:
> Since commit 36a9529e60e ("target/microblaze: Simplify
> compute_ldst_addr_type{a,b}"), helper_stackprot() takes
> a TCGv_i32 argument.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/microblaze/helper.h    | 2 +-
>   target/microblaze/op_helper.c | 4 ++--
>   2 files changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h
> index ef4fad9b91e..01eba592b26 100644
> --- a/target/microblaze/helper.h
> +++ b/target/microblaze/helper.h
> @@ -20,7 +20,7 @@ DEF_HELPER_FLAGS_3(fcmp_ne, TCG_CALL_NO_WG, i32, env, i32, i32)
>   DEF_HELPER_FLAGS_3(fcmp_ge, TCG_CALL_NO_WG, i32, env, i32, i32)
>   
>   DEF_HELPER_FLAGS_2(pcmpbf, TCG_CALL_NO_RWG_SE, i32, i32, i32)
> -DEF_HELPER_FLAGS_2(stackprot, TCG_CALL_NO_WG, void, env, tl)
> +DEF_HELPER_FLAGS_2(stackprot, TCG_CALL_NO_WG, void, env, i32)
>   DEF_HELPER_FLAGS_2(get, TCG_CALL_NO_RWG, i32, i32, i32)
>   DEF_HELPER_FLAGS_3(put, TCG_CALL_NO_RWG, void, i32, i32, i32)
>   
> diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c
> index b8365b3b1d2..df93c4229d6 100644
> --- a/target/microblaze/op_helper.c
> +++ b/target/microblaze/op_helper.c
> @@ -365,13 +365,13 @@ uint32_t helper_pcmpbf(uint32_t a, uint32_t b)
>       return 0;
>   }
>   
> -void helper_stackprot(CPUMBState *env, target_ulong addr)
> +void helper_stackprot(CPUMBState *env, uint32_t addr)
>   {
>       if (addr < env->slr || addr > env->shr) {
>           CPUState *cs = env_cpu(env);
>   
>           qemu_log_mask(CPU_LOG_INT, "Stack protector violation at "
> -                      TARGET_FMT_lx " %x %x\n",
> +                                   "0x%x 0x%x 0x%x\n",
>                         addr, env->slr, env->shr);
>   
>           env->ear = addr;

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>

Re: [PATCH 5/5] target/microblaze: Convert CPUMBState::res_addr field to uint32_t type

[Pierrick Bouvier]

On 10/7/25 11:01 PM, Philippe Mathieu-Daudé wrote:
> CPUMBState::@res_addr field is used as u32 since commit
> cfeea807e5a ("target-microblaze: Tighten up TCGv_i32 vs
> TCGv type usage"). Convert it as such, bumping the migration
> version. Use the RES_ADDR_NONE definition when appropriate.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/microblaze/cpu.h       |  2 +-
>   target/microblaze/machine.c   |  6 +++---
>   target/microblaze/translate.c | 17 +++++++++--------
>   3 files changed, 13 insertions(+), 12 deletions(-)
> 
> diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
> index 3ce28b302fe..14b107876a4 100644
> --- a/target/microblaze/cpu.h
> +++ b/target/microblaze/cpu.h
> @@ -259,7 +259,7 @@ struct CPUArchState {
>   
>       /* lwx/swx reserved address */
>   #define RES_ADDR_NONE 0xffffffff /* Use 0xffffffff to indicate no reservation */
> -    target_ulong res_addr;
> +    uint32_t res_addr;
>       uint32_t res_val;
>   
>       /* Internal flags.  */
> diff --git a/target/microblaze/machine.c b/target/microblaze/machine.c
> index a4cf38dc891..48efa546d39 100644
> --- a/target/microblaze/machine.c
> +++ b/target/microblaze/machine.c
> @@ -78,7 +78,7 @@ static const VMStateField vmstate_env_fields[] = {
>       VMSTATE_UINT32(iflags, CPUMBState),
>   
>       VMSTATE_UINT32(res_val, CPUMBState),
> -    VMSTATE_UINTTL(res_addr, CPUMBState),
> +    VMSTATE_UINT32(res_addr, CPUMBState),
>   
>       VMSTATE_STRUCT(mmu, CPUMBState, 0, vmstate_mmu, MicroBlazeMMU),
>   
> @@ -87,8 +87,8 @@ static const VMStateField vmstate_env_fields[] = {
>   
>   static const VMStateDescription vmstate_env = {
>       .name = "env",
> -    .version_id = 0,
> -    .minimum_version_id = 0,
> +    .version_id = 1,
> +    .minimum_version_id = 1,
>       .fields = vmstate_env_fields,
>   };
>   
> diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
> index ff33e64a710..04fbd4fe17f 100644
> --- a/target/microblaze/translate.c
> +++ b/target/microblaze/translate.c
> @@ -55,7 +55,7 @@ static TCGv_i32 cpu_imm;
>   static TCGv_i32 cpu_bvalue;
>   static TCGv_i32 cpu_btarget;
>   static TCGv_i32 cpu_iflags;
> -static TCGv cpu_res_addr;
> +static TCGv_i32 cpu_res_addr;
>   static TCGv_i32 cpu_res_val;
>   
>   /* This is the state at translation time.  */
> @@ -857,7 +857,7 @@ static bool trans_lwx(DisasContext *dc, arg_typea *arg)
>   
>       tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index,
>                           mo_endian(dc) | MO_UL);
> -    tcg_gen_mov_tl(cpu_res_addr, addr);
> +    tcg_gen_mov_i32(cpu_res_addr, addr);
>   
>       if (arg->rd) {
>           tcg_gen_mov_i32(cpu_R[arg->rd], cpu_res_val);
> @@ -1024,7 +1024,7 @@ static bool trans_swx(DisasContext *dc, arg_typea *arg)
>        * branch, but we know we can use the equal version in the global.
>        * In either case, addr is no longer needed.
>        */
> -    tcg_gen_brcond_tl(TCG_COND_NE, cpu_res_addr, addr, swx_fail);
> +    tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_addr, addr, swx_fail);
>   
>       /*
>        * Compare the value loaded during lwx with current contents of
> @@ -1052,7 +1052,7 @@ static bool trans_swx(DisasContext *dc, arg_typea *arg)
>        * Prevent the saved address from working again without another ldx.
>        * Akin to the pseudocode setting reservation = 0.
>        */
> -    tcg_gen_movi_tl(cpu_res_addr, -1);
> +    tcg_gen_movi_i32(cpu_res_addr, RES_ADDR_NONE);
>       return true;
>   }
>   
> @@ -1173,7 +1173,7 @@ static bool trans_brk(DisasContext *dc, arg_typea_br *arg)
>           tcg_gen_movi_i32(cpu_R[arg->rd], dc->base.pc_next);
>       }
>       tcg_gen_ori_i32(cpu_msr, cpu_msr, MSR_BIP);
> -    tcg_gen_movi_tl(cpu_res_addr, -1);
> +    tcg_gen_movi_i32(cpu_res_addr, RES_ADDR_NONE);
>   
>       dc->base.is_jmp = DISAS_EXIT;
>       return true;
> @@ -1194,7 +1194,7 @@ static bool trans_brki(DisasContext *dc, arg_typeb_br *arg)
>       if (arg->rd) {
>           tcg_gen_movi_i32(cpu_R[arg->rd], dc->base.pc_next);
>       }
> -    tcg_gen_movi_tl(cpu_res_addr, -1);
> +    tcg_gen_movi_i32(cpu_res_addr, RES_ADDR_NONE);
>   
>   #ifdef CONFIG_USER_ONLY
>       switch (imm) {
> @@ -1885,6 +1885,7 @@ void mb_tcg_init(void)
>             tcg_global_mem_new_i32(tcg_env, i32s[i].ofs, i32s[i].name);
>       }
>   
> -    cpu_res_addr =
> -        tcg_global_mem_new(tcg_env, offsetof(CPUMBState, res_addr), "res_addr");
> +    cpu_res_addr = tcg_global_mem_new_i32(tcg_env,
> +                                          offsetof(CPUMBState, res_addr),
> +                                          "res_addr");
>   }

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>