[PATCH 0/6] target/sh4: Remove all uses of target_ulong type

[PATCH 0/6] target/sh4: Remove all uses of target_ulong type

[Philippe Mathieu-Daudé]

Remove the left over target_ulong uses in SH4 frontend.

Philippe Mathieu-Daudé (6):
  target/sh4: Convert CPUSH4State::sr register to uint32_t type
  target/sh4: Remove target_ulong use in cpu_sh4_is_cached()
  target/sh4: Use hwaddr type for hardware addresses
  target/sh4: Remove target_ulong uses in superh_cpu_get_phys_page_debug
  target/sh4: Use vaddr type for TLB virtual addresses
  target/sh4: Remove target_ulong use in gen_goto_tb()

 target/sh4/cpu.h       |  6 +++---
 target/sh4/helper.c    | 34 +++++++++++++++++-----------------
 target/sh4/translate.c |  6 +++---
 3 files changed, 23 insertions(+), 23 deletions(-)

-- 
2.51.0

[PATCH 1/6] target/sh4: Convert CPUSH4State::sr register to uint32_t type

[Philippe Mathieu-Daudé]

Since its introduction in commit fdf9b3e831e the %SR register
is a uint32_t type.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/sh4/cpu.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index c41ab70dd7c..db27a693f12 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -365,14 +365,14 @@ static inline int cpu_ptel_pr (uint32_t ptel)
 #define PTEA_TC        (1 << 3)
 #define cpu_ptea_tc(ptea) (((ptea) & PTEA_TC) >> 3)
 
-static inline target_ulong cpu_read_sr(CPUSH4State *env)
+static inline uint32_t cpu_read_sr(CPUSH4State *env)
 {
     return env->sr | (env->sr_m << SR_M) |
                      (env->sr_q << SR_Q) |
                      (env->sr_t << SR_T);
 }
 
-static inline void cpu_write_sr(CPUSH4State *env, target_ulong sr)
+static inline void cpu_write_sr(CPUSH4State *env, uint32_t sr)
 {
     env->sr_m = (sr >> SR_M) & 1;
     env->sr_q = (sr >> SR_Q) & 1;
-- 
2.51.0

[PATCH 2/6] target/sh4: Remove target_ulong use in cpu_sh4_is_cached()

[Philippe Mathieu-Daudé]

Since commit 852d481faf7 ("SH: Improve movca.l/ocbi emulation")
helper_movcal() pass a uint32_t type to cpu_sh4_is_cached().

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/sh4/cpu.h    | 2 +-
 target/sh4/helper.c | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index db27a693f12..41f634fe162 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -277,7 +277,7 @@ void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr,
                                     uint32_t mem_value);
 #endif
 
-int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr);
+int cpu_sh4_is_cached(CPUSH4State * env, uint32_t addr);
 
 void cpu_load_tlb(CPUSH4State * env);
 
diff --git a/target/sh4/helper.c b/target/sh4/helper.c
index 1744ef0e6d8..42e324589e8 100644
--- a/target/sh4/helper.c
+++ b/target/sh4/helper.c
@@ -47,7 +47,7 @@
 
 #if defined(CONFIG_USER_ONLY)
 
-int cpu_sh4_is_cached(CPUSH4State *env, target_ulong addr)
+int cpu_sh4_is_cached(CPUSH4State *env, uint32_t addr)
 {
     /* For user mode, only U0 area is cacheable. */
     return !(addr & 0x80000000);
@@ -735,7 +735,7 @@ void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr,
     }
 }
 
-int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
+int cpu_sh4_is_cached(CPUSH4State * env, uint32_t addr)
 {
     int n;
     int use_asid = !(env->mmucr & MMUCR_SV) || !(env->sr & (1u << SR_MD));
-- 
2.51.0

[PATCH 3/6] target/sh4: Use hwaddr type for hardware addresses

[Philippe Mathieu-Daudé]

The CPUClass::get_phys_page_debug() handler returns a 'hwaddr' type.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/sh4/helper.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/target/sh4/helper.c b/target/sh4/helper.c
index 42e324589e8..0e13339b33b 100644
--- a/target/sh4/helper.c
+++ b/target/sh4/helper.c
@@ -325,7 +325,7 @@ static int find_utlb_entry(CPUSH4State * env, target_ulong address, int use_asid
    MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION,
    MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE.
 */
-static int get_mmu_address(CPUSH4State * env, target_ulong * physical,
+static int get_mmu_address(CPUSH4State *env, hwaddr *physical,
                            int *prot, target_ulong address,
                            MMUAccessType access_type)
 {
@@ -392,7 +392,7 @@ static int get_mmu_address(CPUSH4State * env, target_ulong * physical,
     return n;
 }
 
-static int get_physical_address(CPUSH4State * env, target_ulong * physical,
+static int get_physical_address(CPUSH4State *env, hwaddr* physical,
                                 int *prot, target_ulong address,
                                 MMUAccessType access_type)
 {
@@ -433,7 +433,7 @@ static int get_physical_address(CPUSH4State * env, target_ulong * physical,
 
 hwaddr superh_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 {
-    target_ulong physical;
+    hwaddr physical;
     int prot;
 
     if (get_physical_address(cpu_env(cs), &physical, &prot, addr, MMU_DATA_LOAD)
@@ -800,7 +800,7 @@ bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
     CPUSH4State *env = cpu_env(cs);
     int ret;
 
-    target_ulong physical;
+    hwaddr physical;
     int prot;
 
     ret = get_physical_address(env, &physical, &prot, address, access_type);
-- 
2.51.0

[PATCH 4/6] target/sh4: Remove target_ulong uses in superh_cpu_get_phys_page_debug

[Philippe Mathieu-Daudé]

The CPUClass::get_phys_page_debug() handler takes a 'vaddr' address
type since commit 00b941e581b ("cpu: Turn cpu_get_phys_page_debug()
into a CPUClass hook").

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/sh4/helper.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/target/sh4/helper.c b/target/sh4/helper.c
index 0e13339b33b..345efbfdd0e 100644
--- a/target/sh4/helper.c
+++ b/target/sh4/helper.c
@@ -231,11 +231,11 @@ static int itlb_replacement(CPUSH4State * env)
 /* Find the corresponding entry in the right TLB
    Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
 */
-static int find_tlb_entry(CPUSH4State * env, target_ulong address,
+static int find_tlb_entry(CPUSH4State * env, vaddr address,
                           tlb_t * entries, uint8_t nbtlb, int use_asid)
 {
     int match = MMU_DTLB_MISS;
-    uint32_t start, end;
+    vaddr start, end;
     uint8_t asid;
     int i;
 
@@ -291,7 +291,7 @@ static int copy_utlb_entry_itlb(CPUSH4State *env, int utlb)
 /* Find itlb entry
    Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
 */
-static int find_itlb_entry(CPUSH4State * env, target_ulong address,
+static int find_itlb_entry(CPUSH4State *env, vaddr address,
                            int use_asid)
 {
     int e;
@@ -309,7 +309,7 @@ static int find_itlb_entry(CPUSH4State * env, target_ulong address,
 
 /* Find utlb entry
    Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
-static int find_utlb_entry(CPUSH4State * env, target_ulong address, int use_asid)
+static int find_utlb_entry(CPUSH4State *env, vaddr address, int use_asid)
 {
     /* per utlb access */
     increment_urc(env);
@@ -326,7 +326,7 @@ static int find_utlb_entry(CPUSH4State * env, target_ulong address, int use_asid
    MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE.
 */
 static int get_mmu_address(CPUSH4State *env, hwaddr *physical,
-                           int *prot, target_ulong address,
+                           int *prot, vaddr address,
                            MMUAccessType access_type)
 {
     int use_asid, n;
@@ -393,7 +393,7 @@ static int get_mmu_address(CPUSH4State *env, hwaddr *physical,
 }
 
 static int get_physical_address(CPUSH4State *env, hwaddr* physical,
-                                int *prot, target_ulong address,
+                                int *prot, vaddr address,
                                 MMUAccessType access_type)
 {
     /* P1, P2 and P4 areas do not use translation */
-- 
2.51.0

[PATCH 5/6] target/sh4: Use vaddr type for TLB virtual addresses

[Philippe Mathieu-Daudé]

tlb_flush_page() expects a vaddr type since commit 732d548732e
("accel: Replace target_ulong in tlb_*()").

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/sh4/helper.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/target/sh4/helper.c b/target/sh4/helper.c
index 345efbfdd0e..507ec78368d 100644
--- a/target/sh4/helper.c
+++ b/target/sh4/helper.c
@@ -452,7 +452,7 @@ void cpu_load_tlb(CPUSH4State * env)
 
     if (entry->v) {
         /* Overwriting valid entry in utlb. */
-        target_ulong address = entry->vpn << 10;
+        vaddr address = entry->vpn << 10;
         tlb_flush_page(cs, address);
     }
 
@@ -528,7 +528,7 @@ void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr,
     tlb_t * entry = &s->itlb[index];
     if (entry->v) {
         /* Overwriting valid entry in itlb. */
-        target_ulong address = entry->vpn << 10;
+        vaddr address = entry->vpn << 10;
         tlb_flush_page(env_cpu(s), address);
     }
     entry->asid = asid;
@@ -570,7 +570,7 @@ void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr,
         /* ITLB Data Array 1 */
         if (entry->v) {
             /* Overwriting valid entry in utlb. */
-            target_ulong address = entry->vpn << 10;
+            vaddr address = entry->vpn << 10;
             tlb_flush_page(env_cpu(s), address);
         }
         entry->ppn = (mem_value & 0x1ffffc00) >> 10;
@@ -665,7 +665,7 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
             CPUState *cs = env_cpu(s);
 
             /* Overwriting valid entry in utlb. */
-            target_ulong address = entry->vpn << 10;
+            vaddr address = entry->vpn << 10;
             tlb_flush_page(cs, address);
         }
         entry->asid = asid;
@@ -716,7 +716,7 @@ void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr,
         /* UTLB Data Array 1 */
         if (entry->v) {
             /* Overwriting valid entry in utlb. */
-            target_ulong address = entry->vpn << 10;
+            vaddr address = entry->vpn << 10;
             tlb_flush_page(env_cpu(s), address);
         }
         entry->ppn = (mem_value & 0x1ffffc00) >> 10;
-- 
2.51.0

[PATCH 6/6] target/sh4: Remove target_ulong use in gen_goto_tb()

[Philippe Mathieu-Daudé]

translator_use_goto_tb() expects a vaddr type since commit
b1c09220b4c ("accel/tcg: Replace target_ulong with vaddr in
translator_*()").

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/sh4/translate.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 70fd13aa3f5..038c8e37063 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -223,7 +223,7 @@ static inline bool use_exit_tb(DisasContext *ctx)
     return (ctx->tbflags & TB_FLAG_GUSA_EXCLUSIVE) != 0;
 }
 
-static bool use_goto_tb(DisasContext *ctx, target_ulong dest)
+static bool use_goto_tb(DisasContext *ctx, vaddr dest)
 {
     if (use_exit_tb(ctx)) {
         return false;
@@ -231,7 +231,7 @@ static bool use_goto_tb(DisasContext *ctx, target_ulong dest)
     return translator_use_goto_tb(&ctx->base, dest);
 }
 
-static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
+static void gen_goto_tb(DisasContext *ctx, int n, vaddr dest)
 {
     if (use_goto_tb(ctx, dest)) {
         tcg_gen_goto_tb(n);
@@ -267,7 +267,7 @@ static void gen_jump(DisasContext * ctx)
 }
 
 /* Immediate conditional jump (bt or bf) */
-static void gen_conditional_jump(DisasContext *ctx, target_ulong dest,
+static void gen_conditional_jump(DisasContext *ctx, vaddr dest,
                                  bool jump_if_true)
 {
     TCGLabel *l1 = gen_new_label();
-- 
2.51.0

Re: [PATCH 1/6] target/sh4: Convert CPUSH4State::sr register to uint32_t type

[Anton Johansson via]

On 08/10/25, Philippe Mathieu-Daudé wrote:
> Since its introduction in commit fdf9b3e831e the %SR register
> is a uint32_t type.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/sh4/cpu.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
 
Reviewed-by: Anton Johansson <anjo@rev.ng>

Re: [PATCH 2/6] target/sh4: Remove target_ulong use in cpu_sh4_is_cached()

[Anton Johansson via]

On 08/10/25, Philippe Mathieu-Daudé wrote:
> Since commit 852d481faf7 ("SH: Improve movca.l/ocbi emulation")
> helper_movcal() pass a uint32_t type to cpu_sh4_is_cached().
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/sh4/cpu.h    | 2 +-
>  target/sh4/helper.c | 4 ++--
>  2 files changed, 3 insertions(+), 3 deletions(-)

Reviewed-by: Anton Johansson <anjo@rev.ng>

Re: [PATCH 3/6] target/sh4: Use hwaddr type for hardware addresses

[Anton Johansson via]

On 08/10/25, Philippe Mathieu-Daudé wrote:
> The CPUClass::get_phys_page_debug() handler returns a 'hwaddr' type.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/sh4/helper.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)

Reviewed-by: Anton Johansson <anjo@rev.ng>

Re: [PATCH 4/6] target/sh4: Remove target_ulong uses in superh_cpu_get_phys_page_debug

[Anton Johansson via]

On 08/10/25, Philippe Mathieu-Daudé wrote:
> The CPUClass::get_phys_page_debug() handler takes a 'vaddr' address
> type since commit 00b941e581b ("cpu: Turn cpu_get_phys_page_debug()
> into a CPUClass hook").
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/sh4/helper.c | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)

Reviewed-by: Anton Johansson <anjo@rev.ng>

Re: [PATCH 5/6] target/sh4: Use vaddr type for TLB virtual addresses

[Anton Johansson via]

On 08/10/25, Philippe Mathieu-Daudé wrote:
> tlb_flush_page() expects a vaddr type since commit 732d548732e
> ("accel: Replace target_ulong in tlb_*()").
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/sh4/helper.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)

Reviewed-by: Anton Johansson <anjo@rev.ng>

Re: [PATCH 6/6] target/sh4: Remove target_ulong use in gen_goto_tb()

[Anton Johansson via]

On 08/10/25, Philippe Mathieu-Daudé wrote:
> translator_use_goto_tb() expects a vaddr type since commit
> b1c09220b4c ("accel/tcg: Replace target_ulong with vaddr in
> translator_*()").
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/sh4/translate.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)

Reviewed-by: Anton Johansson <anjo@rev.ng>