From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Anton Johansson" <anjo@rev.ng>,
"Pierrick Bouvier" <pierrick.bouvier@linaro.org>,
"Yoshinori Sato" <yoshinori.sato@nifty.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PATCH 4/6] target/sh4: Remove target_ulong uses in superh_cpu_get_phys_page_debug
Date: Wed, 8 Oct 2025 08:48:11 +0200 [thread overview]
Message-ID: <20251008064814.90520-5-philmd@linaro.org> (raw)
In-Reply-To: <20251008064814.90520-1-philmd@linaro.org>
The CPUClass::get_phys_page_debug() handler takes a 'vaddr' address
type since commit 00b941e581b ("cpu: Turn cpu_get_phys_page_debug()
into a CPUClass hook").
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/sh4/helper.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/sh4/helper.c b/target/sh4/helper.c
index 0e13339b33b..345efbfdd0e 100644
--- a/target/sh4/helper.c
+++ b/target/sh4/helper.c
@@ -231,11 +231,11 @@ static int itlb_replacement(CPUSH4State * env)
/* Find the corresponding entry in the right TLB
Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
*/
-static int find_tlb_entry(CPUSH4State * env, target_ulong address,
+static int find_tlb_entry(CPUSH4State * env, vaddr address,
tlb_t * entries, uint8_t nbtlb, int use_asid)
{
int match = MMU_DTLB_MISS;
- uint32_t start, end;
+ vaddr start, end;
uint8_t asid;
int i;
@@ -291,7 +291,7 @@ static int copy_utlb_entry_itlb(CPUSH4State *env, int utlb)
/* Find itlb entry
Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
*/
-static int find_itlb_entry(CPUSH4State * env, target_ulong address,
+static int find_itlb_entry(CPUSH4State *env, vaddr address,
int use_asid)
{
int e;
@@ -309,7 +309,7 @@ static int find_itlb_entry(CPUSH4State * env, target_ulong address,
/* Find utlb entry
Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
-static int find_utlb_entry(CPUSH4State * env, target_ulong address, int use_asid)
+static int find_utlb_entry(CPUSH4State *env, vaddr address, int use_asid)
{
/* per utlb access */
increment_urc(env);
@@ -326,7 +326,7 @@ static int find_utlb_entry(CPUSH4State * env, target_ulong address, int use_asid
MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE.
*/
static int get_mmu_address(CPUSH4State *env, hwaddr *physical,
- int *prot, target_ulong address,
+ int *prot, vaddr address,
MMUAccessType access_type)
{
int use_asid, n;
@@ -393,7 +393,7 @@ static int get_mmu_address(CPUSH4State *env, hwaddr *physical,
}
static int get_physical_address(CPUSH4State *env, hwaddr* physical,
- int *prot, target_ulong address,
+ int *prot, vaddr address,
MMUAccessType access_type)
{
/* P1, P2 and P4 areas do not use translation */
--
2.51.0
next prev parent reply other threads:[~2025-10-08 6:49 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-08 6:48 [PATCH 0/6] target/sh4: Remove all uses of target_ulong type Philippe Mathieu-Daudé
2025-10-08 6:48 ` [PATCH 1/6] target/sh4: Convert CPUSH4State::sr register to uint32_t type Philippe Mathieu-Daudé
2025-10-08 10:46 ` Anton Johansson via
2025-10-08 6:48 ` [PATCH 2/6] target/sh4: Remove target_ulong use in cpu_sh4_is_cached() Philippe Mathieu-Daudé
2025-10-08 10:48 ` Anton Johansson via
2025-10-08 6:48 ` [PATCH 3/6] target/sh4: Use hwaddr type for hardware addresses Philippe Mathieu-Daudé
2025-10-08 10:52 ` Anton Johansson via
2025-10-08 6:48 ` Philippe Mathieu-Daudé [this message]
2025-10-08 10:57 ` [PATCH 4/6] target/sh4: Remove target_ulong uses in superh_cpu_get_phys_page_debug Anton Johansson via
2025-10-08 6:48 ` [PATCH 5/6] target/sh4: Use vaddr type for TLB virtual addresses Philippe Mathieu-Daudé
2025-10-08 11:00 ` Anton Johansson via
2025-10-08 6:48 ` [PATCH 6/6] target/sh4: Remove target_ulong use in gen_goto_tb() Philippe Mathieu-Daudé
2025-10-08 11:03 ` Anton Johansson via
2025-10-15 17:15 ` [PATCH 0/6] target/sh4: Remove all uses of target_ulong type Philippe Mathieu-Daudé
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