From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Stafford Horne" <shorne@gmail.com>,
"Pierrick Bouvier" <pierrick.bouvier@linaro.org>,
"Anton Johansson" <anjo@rev.ng>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PATCH 6/7] target/openrisc: Inline tcg_gen_trunc_i64_tl()
Date: Wed, 8 Oct 2025 09:56:10 +0200 [thread overview]
Message-ID: <20251008075612.94193-7-philmd@linaro.org> (raw)
In-Reply-To: <20251008075612.94193-1-philmd@linaro.org>
The OpenRISC targets are only built as 32-bit, so tcg_gen_trunc_i64_tl
expands to tcg_gen_extrl_i64_i32(). Use the latter to simplify the
next commit mechanical change.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
Squash in following?
---
target/openrisc/translate.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 9f61f917b3b..695e11642f7 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -307,7 +307,7 @@ static void gen_muld(DisasContext *dc, TCGv srca, TCGv srcb)
tcg_gen_muls2_i64(cpu_mac, high, t1, t2);
tcg_gen_sari_i64(t1, cpu_mac, 63);
tcg_gen_negsetcond_i64(TCG_COND_NE, t1, t1, high);
- tcg_gen_trunc_i64_tl(cpu_sr_ov, t1);
+ tcg_gen_extrl_i64_i32(cpu_sr_ov, t1);
gen_ove_ov(dc);
}
@@ -328,7 +328,7 @@ static void gen_muldu(DisasContext *dc, TCGv srca, TCGv srcb)
tcg_gen_mulu2_i64(cpu_mac, high, t1, t2);
tcg_gen_setcondi_i64(TCG_COND_NE, high, high, 0);
- tcg_gen_trunc_i64_tl(cpu_sr_cy, high);
+ tcg_gen_extrl_i64_i32(cpu_sr_cy, high);
gen_ove_cy(dc);
}
@@ -370,7 +370,7 @@ static void gen_macu(DisasContext *dc, TCGv srca, TCGv srcb)
/* Note that overflow is only computed during addition stage. */
tcg_gen_add_i64(cpu_mac, cpu_mac, t1);
tcg_gen_setcond_i64(TCG_COND_LTU, t1, cpu_mac, t1);
- tcg_gen_trunc_i64_tl(cpu_sr_cy, t1);
+ tcg_gen_extrl_i64_i32(cpu_sr_cy, t1);
gen_ove_cy(dc);
}
@@ -411,7 +411,7 @@ static void gen_msbu(DisasContext *dc, TCGv srca, TCGv srcb)
/* Note that overflow is only computed during subtraction stage. */
tcg_gen_setcond_i64(TCG_COND_LTU, t2, cpu_mac, t1);
tcg_gen_sub_i64(cpu_mac, cpu_mac, t1);
- tcg_gen_trunc_i64_tl(cpu_sr_cy, t2);
+ tcg_gen_extrl_i64_i32(cpu_sr_cy, t2);
gen_ove_cy(dc);
}
@@ -929,7 +929,7 @@ static bool trans_l_movhi(DisasContext *dc, arg_l_movhi *a)
static bool trans_l_macrc(DisasContext *dc, arg_l_macrc *a)
{
check_r0_write(dc, a->d);
- tcg_gen_trunc_i64_tl(cpu_R(dc, a->d), cpu_mac);
+ tcg_gen_extrl_i64_i32(cpu_R(dc, a->d), cpu_mac);
tcg_gen_movi_i64(cpu_mac, 0);
return true;
}
--
2.51.0
next prev parent reply other threads:[~2025-10-08 7:57 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-08 7:56 [PATCH 0/7] target/openrisc: Remove all uses of target_[u]long types Philippe Mathieu-Daudé
2025-10-08 7:56 ` [PATCH 1/7] target/openrisc: Replace VMSTATE_UINTTL() -> VMSTATE_UINT32() Philippe Mathieu-Daudé
2025-10-08 7:56 ` [PATCH 2/7] target/openrisc: Do not use target_ulong for @mr in MTSPR helper Philippe Mathieu-Daudé
2025-10-08 11:08 ` Anton Johansson via
2025-10-08 7:56 ` [PATCH 3/7] target/openrisc: Remove unused cpu_openrisc_map_address_*() handlers Philippe Mathieu-Daudé
2025-10-08 11:10 ` Anton Johansson via
2025-10-08 7:56 ` [PATCH 4/7] target/openrisc: Remove target_ulong use in raise_mmu_exception() Philippe Mathieu-Daudé
2025-10-08 11:14 ` Anton Johansson via
2025-10-08 7:56 ` [PATCH 5/7] target/openrisc: Use vaddr type for $pc jumps Philippe Mathieu-Daudé
2025-10-08 11:18 ` Anton Johansson via
2025-10-08 7:56 ` Philippe Mathieu-Daudé [this message]
2025-10-08 11:20 ` [PATCH 6/7] target/openrisc: Inline tcg_gen_trunc_i64_tl() Anton Johansson via
2025-10-08 7:56 ` [RFC PATCH 7/7] target/openrisc: Replace target_ulong -> uint32_t Philippe Mathieu-Daudé
2025-10-08 7:59 ` Philippe Mathieu-Daudé
2025-10-08 12:16 ` Anton Johansson via
2025-10-09 8:17 ` Philippe Mathieu-Daudé
2025-10-09 10:00 ` Philippe Mathieu-Daudé
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