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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-46fab3d2c1asm8584585e9.1.2025.10.08.00.56.41 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 08 Oct 2025 00:56:41 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Stafford Horne , Pierrick Bouvier , Anton Johansson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 6/7] target/openrisc: Inline tcg_gen_trunc_i64_tl() Date: Wed, 8 Oct 2025 09:56:10 +0200 Message-ID: <20251008075612.94193-7-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251008075612.94193-1-philmd@linaro.org> References: <20251008075612.94193-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The OpenRISC targets are only built as 32-bit, so tcg_gen_trunc_i64_tl expands to tcg_gen_extrl_i64_i32(). Use the latter to simplify the next commit mechanical change. Signed-off-by: Philippe Mathieu-Daudé --- Squash in following? --- target/openrisc/translate.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 9f61f917b3b..695e11642f7 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -307,7 +307,7 @@ static void gen_muld(DisasContext *dc, TCGv srca, TCGv srcb) tcg_gen_muls2_i64(cpu_mac, high, t1, t2); tcg_gen_sari_i64(t1, cpu_mac, 63); tcg_gen_negsetcond_i64(TCG_COND_NE, t1, t1, high); - tcg_gen_trunc_i64_tl(cpu_sr_ov, t1); + tcg_gen_extrl_i64_i32(cpu_sr_ov, t1); gen_ove_ov(dc); } @@ -328,7 +328,7 @@ static void gen_muldu(DisasContext *dc, TCGv srca, TCGv srcb) tcg_gen_mulu2_i64(cpu_mac, high, t1, t2); tcg_gen_setcondi_i64(TCG_COND_NE, high, high, 0); - tcg_gen_trunc_i64_tl(cpu_sr_cy, high); + tcg_gen_extrl_i64_i32(cpu_sr_cy, high); gen_ove_cy(dc); } @@ -370,7 +370,7 @@ static void gen_macu(DisasContext *dc, TCGv srca, TCGv srcb) /* Note that overflow is only computed during addition stage. */ tcg_gen_add_i64(cpu_mac, cpu_mac, t1); tcg_gen_setcond_i64(TCG_COND_LTU, t1, cpu_mac, t1); - tcg_gen_trunc_i64_tl(cpu_sr_cy, t1); + tcg_gen_extrl_i64_i32(cpu_sr_cy, t1); gen_ove_cy(dc); } @@ -411,7 +411,7 @@ static void gen_msbu(DisasContext *dc, TCGv srca, TCGv srcb) /* Note that overflow is only computed during subtraction stage. */ tcg_gen_setcond_i64(TCG_COND_LTU, t2, cpu_mac, t1); tcg_gen_sub_i64(cpu_mac, cpu_mac, t1); - tcg_gen_trunc_i64_tl(cpu_sr_cy, t2); + tcg_gen_extrl_i64_i32(cpu_sr_cy, t2); gen_ove_cy(dc); } @@ -929,7 +929,7 @@ static bool trans_l_movhi(DisasContext *dc, arg_l_movhi *a) static bool trans_l_macrc(DisasContext *dc, arg_l_macrc *a) { check_r0_write(dc, a->d); - tcg_gen_trunc_i64_tl(cpu_R(dc, a->d), cpu_mac); + tcg_gen_extrl_i64_i32(cpu_R(dc, a->d), cpu_mac); tcg_gen_movi_i64(cpu_mac, 0); return true; } -- 2.51.0