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* [PATCH] i2c/smbus_eeprom: Add minimum write recovery time for DDR2
@ 2025-10-08 12:25 BALATON Zoltan
  2025-10-18 11:27 ` BALATON Zoltan
                   ` (2 more replies)
  0 siblings, 3 replies; 5+ messages in thread
From: BALATON Zoltan @ 2025-10-08 12:25 UTC (permalink / raw)
  To: qemu-devel; +Cc: Corey Minyard

This is needed for newer u-boot-sam460ex versions to pass the DRAM
setup.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
 hw/i2c/smbus_eeprom.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/i2c/smbus_eeprom.c b/hw/i2c/smbus_eeprom.c
index 0a1088fbb0..26e211b31a 100644
--- a/hw/i2c/smbus_eeprom.c
+++ b/hw/i2c/smbus_eeprom.c
@@ -288,6 +288,7 @@ uint8_t *spd_data_generate(enum sdram_type type, ram_addr_t ram_size)
     spd[33] = 8;    /* addr/cmd hold time */
     spd[34] = 20;   /* data input setup time */
     spd[35] = 8;    /* data input hold time */
+    spd[36] = (type == DDR2 ? 13 << 2 : 0); /* min. write recovery time */
 
     /* checksum */
     for (i = 0; i < 63; i++) {
-- 
2.41.3



^ permalink raw reply related	[flat|nested] 5+ messages in thread

* Re: [PATCH] i2c/smbus_eeprom: Add minimum write recovery time for DDR2
  2025-10-08 12:25 [PATCH] i2c/smbus_eeprom: Add minimum write recovery time for DDR2 BALATON Zoltan
@ 2025-10-18 11:27 ` BALATON Zoltan
  2025-10-20  9:22 ` Philippe Mathieu-Daudé
  2025-10-20 20:11 ` Philippe Mathieu-Daudé
  2 siblings, 0 replies; 5+ messages in thread
From: BALATON Zoltan @ 2025-10-18 11:27 UTC (permalink / raw)
  To: qemu-devel; +Cc: Corey Minyard

On Wed, 8 Oct 2025, BALATON Zoltan wrote:
> This is needed for newer u-boot-sam460ex versions to pass the DRAM
> setup.
>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>

Ping? Will somebody review and merge this?

Regards,
BALATON Zoltan

> ---
> hw/i2c/smbus_eeprom.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/hw/i2c/smbus_eeprom.c b/hw/i2c/smbus_eeprom.c
> index 0a1088fbb0..26e211b31a 100644
> --- a/hw/i2c/smbus_eeprom.c
> +++ b/hw/i2c/smbus_eeprom.c
> @@ -288,6 +288,7 @@ uint8_t *spd_data_generate(enum sdram_type type, ram_addr_t ram_size)
>     spd[33] = 8;    /* addr/cmd hold time */
>     spd[34] = 20;   /* data input setup time */
>     spd[35] = 8;    /* data input hold time */
> +    spd[36] = (type == DDR2 ? 13 << 2 : 0); /* min. write recovery time */
>
>     /* checksum */
>     for (i = 0; i < 63; i++) {
>


^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH] i2c/smbus_eeprom: Add minimum write recovery time for DDR2
  2025-10-08 12:25 [PATCH] i2c/smbus_eeprom: Add minimum write recovery time for DDR2 BALATON Zoltan
  2025-10-18 11:27 ` BALATON Zoltan
@ 2025-10-20  9:22 ` Philippe Mathieu-Daudé
  2025-10-20 14:03   ` BALATON Zoltan
  2025-10-20 20:11 ` Philippe Mathieu-Daudé
  2 siblings, 1 reply; 5+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-20  9:22 UTC (permalink / raw)
  To: BALATON Zoltan, qemu-devel; +Cc: Corey Minyard

On 8/10/25 14:25, BALATON Zoltan wrote:
> This is needed for newer u-boot-sam460ex versions to pass the DRAM
> setup.
> 
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
>   hw/i2c/smbus_eeprom.c | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/hw/i2c/smbus_eeprom.c b/hw/i2c/smbus_eeprom.c
> index 0a1088fbb0..26e211b31a 100644
> --- a/hw/i2c/smbus_eeprom.c
> +++ b/hw/i2c/smbus_eeprom.c
> @@ -288,6 +288,7 @@ uint8_t *spd_data_generate(enum sdram_type type, ram_addr_t ram_size)
>       spd[33] = 8;    /* addr/cmd hold time */
>       spd[34] = 20;   /* data input setup time */
>       spd[35] = 8;    /* data input hold time */
> +    spd[36] = (type == DDR2 ? 13 << 2 : 0); /* min. write recovery time */

We are adapting DDR2 values on a method written for SDR/DDR[1].
Better would be to split and correctly document each format,
using proper values.

Anyhow, for this patch:
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>



^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH] i2c/smbus_eeprom: Add minimum write recovery time for DDR2
  2025-10-20  9:22 ` Philippe Mathieu-Daudé
@ 2025-10-20 14:03   ` BALATON Zoltan
  0 siblings, 0 replies; 5+ messages in thread
From: BALATON Zoltan @ 2025-10-20 14:03 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé; +Cc: qemu-devel, Corey Minyard

[-- Attachment #1: Type: text/plain, Size: 1492 bytes --]

On Mon, 20 Oct 2025, Philippe Mathieu-Daudé wrote:
> On 8/10/25 14:25, BALATON Zoltan wrote:
>> This is needed for newer u-boot-sam460ex versions to pass the DRAM
>> setup.
>> 
>> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
>> ---
>>   hw/i2c/smbus_eeprom.c | 1 +
>>   1 file changed, 1 insertion(+)
>> 
>> diff --git a/hw/i2c/smbus_eeprom.c b/hw/i2c/smbus_eeprom.c
>> index 0a1088fbb0..26e211b31a 100644
>> --- a/hw/i2c/smbus_eeprom.c
>> +++ b/hw/i2c/smbus_eeprom.c
>> @@ -288,6 +288,7 @@ uint8_t *spd_data_generate(enum sdram_type type, 
>> ram_addr_t ram_size)
>>       spd[33] = 8;    /* addr/cmd hold time */
>>       spd[34] = 20;   /* data input setup time */
>>       spd[35] = 8;    /* data input hold time */
>> +    spd[36] = (type == DDR2 ? 13 << 2 : 0); /* min. write recovery time */
>
> We are adapting DDR2 values on a method written for SDR/DDR[1].
> Better would be to split and correctly document each format,
> using proper values.

I plan to add separate function for DDR3 which is different from these 
(Bernhard had a patch for that which we can adopt but I haven't got to 
that yet). Maybe a split could be considered then but these formats up to 
DDR2 are quite similar with a lot of common values and only a few 
differences to have them in a single function. As a documentation better 
consult something else, e.g. wikipedia has a good summary.

> Anyhow, for this patch:
> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Thank you,
BALATON Zoltan

^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH] i2c/smbus_eeprom: Add minimum write recovery time for DDR2
  2025-10-08 12:25 [PATCH] i2c/smbus_eeprom: Add minimum write recovery time for DDR2 BALATON Zoltan
  2025-10-18 11:27 ` BALATON Zoltan
  2025-10-20  9:22 ` Philippe Mathieu-Daudé
@ 2025-10-20 20:11 ` Philippe Mathieu-Daudé
  2 siblings, 0 replies; 5+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-20 20:11 UTC (permalink / raw)
  To: BALATON Zoltan, qemu-devel; +Cc: Corey Minyard

On 8/10/25 14:25, BALATON Zoltan wrote:
> This is needed for newer u-boot-sam460ex versions to pass the DRAM
> setup.
> 
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
>   hw/i2c/smbus_eeprom.c | 1 +
>   1 file changed, 1 insertion(+)

Patch queued, thanks.


^ permalink raw reply	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2025-10-20 20:11 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-10-08 12:25 [PATCH] i2c/smbus_eeprom: Add minimum write recovery time for DDR2 BALATON Zoltan
2025-10-18 11:27 ` BALATON Zoltan
2025-10-20  9:22 ` Philippe Mathieu-Daudé
2025-10-20 14:03   ` BALATON Zoltan
2025-10-20 20:11 ` Philippe Mathieu-Daudé

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