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([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29034e44ef9sm7354285ad.52.2025.10.08.14.56.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Oct 2025 14:56:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v7 20/73] target/arm: Convert regime_has_2_ranges from switch to table Date: Wed, 8 Oct 2025 14:55:20 -0700 Message-ID: <20251008215613.300150-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251008215613.300150-1-richard.henderson@linaro.org> References: <20251008215613.300150-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/internals.h | 28 ---------------------------- target/arm/mmuidx-internal.h | 17 +++++++++++++++++ target/arm/mmuidx.c | 19 ++++++++++--------- 3 files changed, 27 insertions(+), 37 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 319c39a4ac..061472a943 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1027,34 +1027,6 @@ static inline void arm_call_el_change_hook(ARMCPU *cpu) } } -/* - * Return true if this address translation regime has two ranges. - * Note that this will not return the correct answer for AArch32 - * Secure PL1&0 (i.e. mmu indexes E3, E30_0, E30_3_PAN), but it is - * never called from a context where EL3 can be AArch32. (The - * correct return value for ARMMMUIdx_E3 would be different for - * that case, so we can't just make the function return the - * correct value anyway; we would need an extra "bool e3_is_aarch32" - * argument which all the current callsites would pass as 'false'.) - */ -static inline bool regime_has_2_ranges(ARMMMUIdx mmu_idx) -{ - switch (mmu_idx) { - case ARMMMUIdx_Stage1_E0: - case ARMMMUIdx_Stage1_E1: - case ARMMMUIdx_Stage1_E1_PAN: - case ARMMMUIdx_E10_0: - case ARMMMUIdx_E10_1: - case ARMMMUIdx_E10_1_PAN: - case ARMMMUIdx_E20_0: - case ARMMMUIdx_E20_2: - case ARMMMUIdx_E20_2_PAN: - return true; - default: - return false; - } -} - static inline bool regime_is_pan(CPUARMState *env, ARMMMUIdx mmu_idx) { switch (mmu_idx) { diff --git a/target/arm/mmuidx-internal.h b/target/arm/mmuidx-internal.h index d8d64a14d6..f03a2ab94c 100644 --- a/target/arm/mmuidx-internal.h +++ b/target/arm/mmuidx-internal.h @@ -15,6 +15,7 @@ FIELD(MMUIDXINFO, EL, 0, 2) FIELD(MMUIDXINFO, ELVALID, 2, 1) FIELD(MMUIDXINFO, REL, 3, 2) FIELD(MMUIDXINFO, RELVALID, 5, 1) +FIELD(MMUIDXINFO, 2RANGES, 6, 1) extern const uint32_t arm_mmuidx_table[ARM_MMU_IDX_M + 8]; @@ -39,4 +40,20 @@ static inline uint32_t regime_el(ARMMMUIdx idx) return FIELD_EX32(arm_mmuidx_table[idx], MMUIDXINFO, REL); } +/* + * Return true if this address translation regime has two ranges. + * Note that this will not return the correct answer for AArch32 + * Secure PL1&0 (i.e. mmu indexes E3, E30_0, E30_3_PAN), but it is + * never called from a context where EL3 can be AArch32. (The + * correct return value for ARMMMUIdx_E3 would be different for + * that case, so we can't just make the function return the + * correct value anyway; we would need an extra "bool e3_is_aarch32" + * argument which all the current callsites would pass as 'false'.) + */ +static inline bool regime_has_2_ranges(ARMMMUIdx idx) +{ + tcg_debug_assert(arm_mmuidx_is_valid(idx)); + return FIELD_EX32(arm_mmuidx_table[idx], MMUIDXINFO, 2RANGES); +} + #endif /* TARGET_ARM_MMUIDX_INTERNAL_H */ diff --git a/target/arm/mmuidx.c b/target/arm/mmuidx.c index 6dfefa56c2..f880d21606 100644 --- a/target/arm/mmuidx.c +++ b/target/arm/mmuidx.c @@ -9,18 +9,19 @@ #define EL(X) ((X << R_MMUIDXINFO_EL_SHIFT) | R_MMUIDXINFO_ELVALID_MASK) #define REL(X) ((X << R_MMUIDXINFO_REL_SHIFT) | R_MMUIDXINFO_RELVALID_MASK) +#define R2 R_MMUIDXINFO_2RANGES_MASK const uint32_t arm_mmuidx_table[ARM_MMU_IDX_M + 8] = { /* * A-profile. */ - [ARMMMUIdx_E10_0] = EL(0) | REL(1), - [ARMMMUIdx_E10_1] = EL(1) | REL(1), - [ARMMMUIdx_E10_1_PAN] = EL(1) | REL(1), + [ARMMMUIdx_E10_0] = EL(0) | REL(1) | R2, + [ARMMMUIdx_E10_1] = EL(1) | REL(1) | R2, + [ARMMMUIdx_E10_1_PAN] = EL(1) | REL(1) | R2, - [ARMMMUIdx_E20_0] = EL(0) | REL(2), - [ARMMMUIdx_E20_2] = EL(2) | REL(2), - [ARMMMUIdx_E20_2_PAN] = EL(2) | REL(2), + [ARMMMUIdx_E20_0] = EL(0) | REL(2) | R2, + [ARMMMUIdx_E20_2] = EL(2) | REL(2) | R2, + [ARMMMUIdx_E20_2_PAN] = EL(2) | REL(2) | R2, [ARMMMUIdx_E2] = EL(2) | REL(2), @@ -31,9 +32,9 @@ const uint32_t arm_mmuidx_table[ARM_MMU_IDX_M + 8] = { [ARMMMUIdx_Stage2_S] = REL(2), [ARMMMUIdx_Stage2] = REL(2), - [ARMMMUIdx_Stage1_E0] = REL(1), - [ARMMMUIdx_Stage1_E1] = REL(1), - [ARMMMUIdx_Stage1_E1_PAN] = REL(1), + [ARMMMUIdx_Stage1_E0] = REL(1) | R2, + [ARMMMUIdx_Stage1_E1] = REL(1) | R2, + [ARMMMUIdx_Stage1_E1_PAN] = REL(1) | R2, /* * M-profile. -- 2.43.0