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([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29034e44ef9sm7354285ad.52.2025.10.08.14.56.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Oct 2025 14:56:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v7 22/73] target/arm: Convert regime_is_pan from switch to table Date: Wed, 8 Oct 2025 14:55:22 -0700 Message-ID: <20251008215613.300150-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251008215613.300150-1-richard.henderson@linaro.org> References: <20251008215613.300150-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/internals.h | 13 ------------- target/arm/mmuidx-internal.h | 8 ++++++++ target/arm/mmuidx.c | 9 +++++---- 3 files changed, 13 insertions(+), 17 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index cb2ffeff59..819ada7a5d 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1027,19 +1027,6 @@ static inline void arm_call_el_change_hook(ARMCPU *cpu) } } -static inline bool regime_is_pan(ARMMMUIdx mmu_idx) -{ - switch (mmu_idx) { - case ARMMMUIdx_Stage1_E1_PAN: - case ARMMMUIdx_E10_1_PAN: - case ARMMMUIdx_E20_2_PAN: - case ARMMMUIdx_E30_3_PAN: - return true; - default: - return false; - } -} - static inline bool regime_is_stage2(ARMMMUIdx mmu_idx) { return mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S; diff --git a/target/arm/mmuidx-internal.h b/target/arm/mmuidx-internal.h index f03a2ab94c..41baf1a003 100644 --- a/target/arm/mmuidx-internal.h +++ b/target/arm/mmuidx-internal.h @@ -16,6 +16,7 @@ FIELD(MMUIDXINFO, ELVALID, 2, 1) FIELD(MMUIDXINFO, REL, 3, 2) FIELD(MMUIDXINFO, RELVALID, 5, 1) FIELD(MMUIDXINFO, 2RANGES, 6, 1) +FIELD(MMUIDXINFO, PAN, 7, 1) extern const uint32_t arm_mmuidx_table[ARM_MMU_IDX_M + 8]; @@ -56,4 +57,11 @@ static inline bool regime_has_2_ranges(ARMMMUIdx idx) return FIELD_EX32(arm_mmuidx_table[idx], MMUIDXINFO, 2RANGES); } +/* Return true if Privileged Access Never is enabled for this mmu index. */ +static inline bool regime_is_pan(ARMMMUIdx idx) +{ + tcg_debug_assert(arm_mmuidx_is_valid(idx)); + return FIELD_EX32(arm_mmuidx_table[idx], MMUIDXINFO, PAN); +} + #endif /* TARGET_ARM_MMUIDX_INTERNAL_H */ diff --git a/target/arm/mmuidx.c b/target/arm/mmuidx.c index f880d21606..98db02b8e5 100644 --- a/target/arm/mmuidx.c +++ b/target/arm/mmuidx.c @@ -10,6 +10,7 @@ #define EL(X) ((X << R_MMUIDXINFO_EL_SHIFT) | R_MMUIDXINFO_ELVALID_MASK) #define REL(X) ((X << R_MMUIDXINFO_REL_SHIFT) | R_MMUIDXINFO_RELVALID_MASK) #define R2 R_MMUIDXINFO_2RANGES_MASK +#define PAN R_MMUIDXINFO_PAN_MASK const uint32_t arm_mmuidx_table[ARM_MMU_IDX_M + 8] = { /* @@ -17,24 +18,24 @@ const uint32_t arm_mmuidx_table[ARM_MMU_IDX_M + 8] = { */ [ARMMMUIdx_E10_0] = EL(0) | REL(1) | R2, [ARMMMUIdx_E10_1] = EL(1) | REL(1) | R2, - [ARMMMUIdx_E10_1_PAN] = EL(1) | REL(1) | R2, + [ARMMMUIdx_E10_1_PAN] = EL(1) | REL(1) | R2 | PAN, [ARMMMUIdx_E20_0] = EL(0) | REL(2) | R2, [ARMMMUIdx_E20_2] = EL(2) | REL(2) | R2, - [ARMMMUIdx_E20_2_PAN] = EL(2) | REL(2) | R2, + [ARMMMUIdx_E20_2_PAN] = EL(2) | REL(2) | R2 | PAN, [ARMMMUIdx_E2] = EL(2) | REL(2), [ARMMMUIdx_E3] = EL(3) | REL(3), [ARMMMUIdx_E30_0] = EL(0) | REL(3), - [ARMMMUIdx_E30_3_PAN] = EL(3) | REL(3), + [ARMMMUIdx_E30_3_PAN] = EL(3) | REL(3) | PAN, [ARMMMUIdx_Stage2_S] = REL(2), [ARMMMUIdx_Stage2] = REL(2), [ARMMMUIdx_Stage1_E0] = REL(1) | R2, [ARMMMUIdx_Stage1_E1] = REL(1) | R2, - [ARMMMUIdx_Stage1_E1_PAN] = REL(1) | R2, + [ARMMMUIdx_Stage1_E1_PAN] = REL(1) | R2 | PAN, /* * M-profile. -- 2.43.0