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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, Pierrick Bouvier <pierrick.bouvier@linaro.org>
Subject: [PATCH v7 63/73] linux-user/aarch64: Implement prctls for GCS
Date: Wed,  8 Oct 2025 14:56:03 -0700	[thread overview]
Message-ID: <20251008215613.300150-64-richard.henderson@linaro.org> (raw)
In-Reply-To: <20251008215613.300150-1-richard.henderson@linaro.org>

This is PR_GET_SHADOW_STACK_STATUS, PR_SET_SHADOW_STACK_STATUS,
and PR_LOCK_SHADOW_STACK_STATUS.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 linux-user/aarch64/gcs-internal.h | 38 ++++++++++++
 linux-user/aarch64/target_prctl.h | 96 +++++++++++++++++++++++++++++++
 linux-user/qemu.h                 |  5 ++
 linux-user/syscall.c              | 29 ++++++++++
 4 files changed, 168 insertions(+)
 create mode 100644 linux-user/aarch64/gcs-internal.h

diff --git a/linux-user/aarch64/gcs-internal.h b/linux-user/aarch64/gcs-internal.h
new file mode 100644
index 0000000000..e586c7e80e
--- /dev/null
+++ b/linux-user/aarch64/gcs-internal.h
@@ -0,0 +1,38 @@
+/*
+ * AArch64 gcs functions for linux-user
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#ifndef AARCH64_GCS_INTERNAL_H
+#define AARCH64_GCS_INTERNAL_H
+
+#ifndef PR_SHADOW_STACK_ENABLE
+# define PR_SHADOW_STACK_ENABLE  (1U << 0)
+# define PR_SHADOW_STACK_WRITE   (1U << 1)
+# define PR_SHADOW_STACK_PUSH    (1U << 2)
+#endif
+
+static inline uint64_t gcs_get_el0_mode(CPUArchState *env)
+{
+    uint64_t cr = env->cp15.gcscr_el[0];
+    abi_ulong flags = 0;
+
+    flags |= cr & GCSCR_PCRSEL ? PR_SHADOW_STACK_ENABLE : 0;
+    flags |= cr & GCSCR_STREN ? PR_SHADOW_STACK_WRITE : 0;
+    flags |= cr & GCSCR_PUSHMEN ? PR_SHADOW_STACK_PUSH : 0;
+
+    return flags;
+}
+
+static inline void gcs_set_el0_mode(CPUArchState *env, uint64_t flags)
+{
+    uint64_t cr = GCSCRE0_NTR;
+
+    cr |= flags & PR_SHADOW_STACK_ENABLE ? GCSCR_RVCHKEN | GCSCR_PCRSEL : 0;
+    cr |= flags & PR_SHADOW_STACK_WRITE ? GCSCR_STREN : 0;
+    cr |= flags & PR_SHADOW_STACK_PUSH ? GCSCR_PUSHMEN : 0;
+
+    env->cp15.gcscr_el[0] = cr;
+}
+
+#endif
diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_prctl.h
index ed75b9e4b5..621be5727f 100644
--- a/linux-user/aarch64/target_prctl.h
+++ b/linux-user/aarch64/target_prctl.h
@@ -6,8 +6,10 @@
 #ifndef AARCH64_TARGET_PRCTL_H
 #define AARCH64_TARGET_PRCTL_H
 
+#include "qemu/units.h"
 #include "target/arm/cpu-features.h"
 #include "mte_user_helper.h"
+#include "gcs-internal.h"
 
 static abi_long do_prctl_sve_get_vl(CPUArchState *env)
 {
@@ -206,4 +208,98 @@ static abi_long do_prctl_get_tagged_addr_ctrl(CPUArchState *env)
 }
 #define do_prctl_get_tagged_addr_ctrl do_prctl_get_tagged_addr_ctrl
 
+static abi_long do_prctl_get_shadow_stack_status(CPUArchState *env,
+                                                 abi_long arg2)
+{
+    ARMCPU *cpu = env_archcpu(env);
+
+    if (!cpu_isar_feature(aa64_gcs, cpu)) {
+        return -TARGET_EINVAL;
+    }
+    return put_user_ual(gcs_get_el0_mode(env), arg2);
+}
+#define do_prctl_get_shadow_stack_status do_prctl_get_shadow_stack_status
+
+static abi_long gcs_alloc(abi_ulong hint, abi_ulong size)
+{
+    /*
+     * Without softmmu, we cannot protect GCS memory properly.
+     * Make do with normal read/write permissions.  This at least allows
+     * emulation of correct programs which don't access the gcs stack
+     * with normal instructions.
+     */
+    return target_mmap(hint, size, PROT_READ | PROT_WRITE,
+                       MAP_PRIVATE | MAP_ANONYMOUS |
+                       (hint ? MAP_FIXED_NOREPLACE : 0), -1, 0);
+}
+
+static abi_ulong gcs_new_stack(TaskState *ts)
+{
+    /* Use guest_stack_size as a proxy for RLIMIT_STACK. */
+    abi_ulong size = MIN(MAX(guest_stack_size / 2, TARGET_PAGE_SIZE), 2 * GiB);
+    abi_ulong base = gcs_alloc(0, size);
+
+    if (base == -1) {
+        return -1;
+    }
+
+    ts->gcs_base = base;
+    ts->gcs_size = size;
+    return base + size - 8;
+}
+
+static abi_long do_prctl_set_shadow_stack_status(CPUArchState *env,
+                                                 abi_long new_mode)
+{
+    ARMCPU *cpu = env_archcpu(env);
+    TaskState *ts = get_task_state(env_cpu(env));
+    abi_long cur_mode;
+
+    if (!cpu_isar_feature(aa64_gcs, cpu)) {
+        return -TARGET_EINVAL;
+    }
+    if (new_mode & ~(PR_SHADOW_STACK_ENABLE |
+                     PR_SHADOW_STACK_WRITE |
+                     PR_SHADOW_STACK_PUSH)) {
+        return -TARGET_EINVAL;
+    }
+
+    cur_mode = gcs_get_el0_mode(env);
+    if ((new_mode ^ cur_mode) & ts->gcs_el0_locked) {
+        return -TARGET_EBUSY;
+    }
+
+    if (new_mode & ~cur_mode & PR_SHADOW_STACK_ENABLE) {
+        abi_long gcspr;
+
+        if (ts->gcs_base || env->cp15.gcspr_el[0]) {
+            return -EINVAL;
+        }
+        gcspr = gcs_new_stack(ts);
+        if (gcspr == -1) {
+            return -TARGET_ENOMEM;
+        }
+        env->cp15.gcspr_el[0] = gcspr;
+    }
+
+    gcs_set_el0_mode(env, new_mode);
+    arm_rebuild_hflags(env);
+    return 0;
+}
+#define do_prctl_set_shadow_stack_status do_prctl_set_shadow_stack_status
+
+static abi_long do_prctl_lock_shadow_stack_status(CPUArchState *env,
+                                                  abi_long arg2)
+{
+    ARMCPU *cpu = env_archcpu(env);
+    TaskState *ts = get_task_state(env_cpu(env));
+
+    if (!cpu_isar_feature(aa64_gcs, cpu)) {
+        return -EINVAL;
+    }
+    ts->gcs_el0_locked |= arg2;
+    return 0;
+}
+#define do_prctl_lock_shadow_stack_status do_prctl_lock_shadow_stack_status
+
 #endif /* AARCH64_TARGET_PRCTL_H */
diff --git a/linux-user/qemu.h b/linux-user/qemu.h
index cabb7bd6a8..85e68eff7b 100644
--- a/linux-user/qemu.h
+++ b/linux-user/qemu.h
@@ -121,6 +121,11 @@ struct TaskState {
     abi_ulong child_tidptr;
 #ifdef TARGET_M68K
     abi_ulong tp_value;
+#endif
+#if defined(TARGET_AARCH64)
+    vaddr gcs_base;
+    abi_ulong gcs_size;
+    abi_ulong gcs_el0_locked;
 #endif
     int used; /* non zero if used */
     struct image_info *info;
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index d78b2029fa..56695de680 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -6353,6 +6353,11 @@ abi_long do_arch_prctl(CPUX86State *env, int code, abi_ulong addr)
 # define PR_SME_VL_LEN_MASK  0xffff
 # define PR_SME_VL_INHERIT   (1 << 17)
 #endif
+#ifndef PR_GET_SHADOW_STACK_STATUS
+# define PR_GET_SHADOW_STACK_STATUS  74
+# define PR_SET_SHADOW_STACK_STATUS  75
+# define PR_LOCK_SHADOW_STACK_STATUS 76
+#endif
 
 #include "target_prctl.h"
 
@@ -6399,6 +6404,15 @@ static abi_long do_prctl_inval1(CPUArchState *env, abi_long arg2)
 #ifndef do_prctl_sme_set_vl
 #define do_prctl_sme_set_vl do_prctl_inval1
 #endif
+#ifndef do_prctl_get_shadow_stack_status
+#define do_prctl_get_shadow_stack_status do_prctl_inval1
+#endif
+#ifndef do_prctl_set_shadow_stack_status
+#define do_prctl_set_shadow_stack_status do_prctl_inval1
+#endif
+#ifndef do_prctl_lock_shadow_stack_status
+#define do_prctl_lock_shadow_stack_status do_prctl_inval1
+#endif
 
 static abi_long do_prctl_syscall_user_dispatch(CPUArchState *env,
                                                abi_ulong arg2, abi_ulong arg3,
@@ -6499,6 +6513,21 @@ static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2,
             return -TARGET_EINVAL;
         }
         return do_prctl_get_tagged_addr_ctrl(env);
+    case PR_GET_SHADOW_STACK_STATUS:
+        if (arg3 || arg4 || arg5) {
+            return -TARGET_EINVAL;
+        }
+        return do_prctl_get_shadow_stack_status(env, arg2);
+    case PR_SET_SHADOW_STACK_STATUS:
+        if (arg3 || arg4 || arg5) {
+            return -TARGET_EINVAL;
+        }
+        return do_prctl_set_shadow_stack_status(env, arg2);
+    case PR_LOCK_SHADOW_STACK_STATUS:
+        if (arg3 || arg4 || arg5) {
+            return -TARGET_EINVAL;
+        }
+        return do_prctl_lock_shadow_stack_status(env, arg2);
 
     case PR_GET_UNALIGN:
         return do_prctl_get_unalign(env, arg2);
-- 
2.43.0



  parent reply	other threads:[~2025-10-08 22:09 UTC|newest]

Thread overview: 85+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-08 21:55 [PATCH v7 00/73] target/arm: Implement FEAT_GCS Richard Henderson
2025-10-08 21:55 ` [PATCH v7 01/73] tests/functional: update tests using TF-A/TF-RMM to support FEAT_GCS Richard Henderson
2025-10-08 21:55 ` [PATCH v7 02/73] target/arm: Add isar feature test for FEAT_S1PIE, FEAT_S2PIE Richard Henderson
2025-10-08 21:55 ` [PATCH v7 03/73] target/arm: Enable TCR2_ELx.PIE Richard Henderson
2025-10-08 21:55 ` [PATCH v7 04/73] target/arm: Implement PIR_ELx, PIRE0_ELx, S2PIR_EL2 registers Richard Henderson
2025-10-08 21:55 ` [PATCH v7 05/73] target/arm: Force HPD for stage2 translations Richard Henderson
2025-10-08 21:55 ` [PATCH v7 06/73] target/arm: Cache NV1 early in get_phys_addr_lpae Richard Henderson
2025-10-08 21:55 ` [PATCH v7 07/73] target/arm: Populate PIE in aa64_va_parameters Richard Henderson
2025-10-08 21:55 ` [PATCH v7 08/73] target/arm: Implement get_S1prot_indirect Richard Henderson
2025-10-08 21:55 ` [PATCH v7 09/73] target/arm: Implement get_S2prot_indirect Richard Henderson
2025-10-08 21:55 ` [PATCH v7 10/73] target/arm: Expand CPUARMState.exception.syndrome to 64 bits Richard Henderson
2025-10-09 14:14   ` Philippe Mathieu-Daudé
2025-10-09 17:43     ` Richard Henderson
2025-10-08 21:55 ` [PATCH v7 11/73] target/arm: Expand syndrome parameter to raise_exception* Richard Henderson
2025-10-08 21:55 ` [PATCH v7 12/73] target/arm: Implement dirtybit check for PIE Richard Henderson
2025-10-08 21:55 ` [PATCH v7 13/73] target/arm: Enable FEAT_S1PIE and FEAT_S2PIE on -cpu max Richard Henderson
2025-10-08 21:55 ` [PATCH v7 14/73] include/exec/memopidx: Adjust for 32 mmu indexes Richard Henderson
2025-10-09 14:03   ` Philippe Mathieu-Daudé
2025-10-08 21:55 ` [PATCH v7 15/73] include/hw/core/cpu: Widen MMUIdxMap Richard Henderson
2025-10-08 21:55 ` [PATCH v7 16/73] target/arm: Split out mmuidx.h from cpu.h Richard Henderson
2025-10-08 21:55 ` [PATCH v7 17/73] target/arm: Convert arm_mmu_idx_to_el from switch to table Richard Henderson
2025-10-08 21:55 ` [PATCH v7 18/73] target/arm: Remove unused env argument from regime_el Richard Henderson
2025-10-08 21:55 ` [PATCH v7 19/73] target/arm: Convert regime_el from switch to table Richard Henderson
2025-10-08 21:55 ` [PATCH v7 20/73] target/arm: Convert regime_has_2_ranges " Richard Henderson
2025-10-08 21:55 ` [PATCH v7 21/73] target/arm: Remove unused env argument from regime_is_pan Richard Henderson
2025-10-08 21:55 ` [PATCH v7 22/73] target/arm: Convert regime_is_pan from switch to table Richard Henderson
2025-10-08 21:55 ` [PATCH v7 23/73] target/arm: Remove unused env argument from regime_is_user Richard Henderson
2025-10-08 21:55 ` [PATCH v7 24/73] target/arm: Convert regime_is_user from switch to table Richard Henderson
2025-10-08 21:55 ` [PATCH v7 25/73] target/arm: Convert arm_mmu_idx_is_stage1_of_2 " Richard Henderson
2025-10-08 21:55 ` [PATCH v7 26/73] target/arm: Convert regime_is_stage2 " Richard Henderson
2025-10-08 21:55 ` [PATCH v7 27/73] target/arm: Introduce mmu indexes for GCS Richard Henderson
2025-10-08 21:55 ` [PATCH v7 28/73] target/arm: Introduce regime_to_gcs Richard Henderson
2025-10-08 21:55 ` [PATCH v7 29/73] target/arm: Support page protections for GCS mmu indexes Richard Henderson
2025-10-08 21:55 ` [PATCH v7 30/73] target/arm: Implement gcs bit for data abort Richard Henderson
2025-10-08 21:55 ` [PATCH v7 31/73] target/arm: Add GCS cpregs Richard Henderson
2025-10-08 21:55 ` [PATCH v7 32/73] target/arm: Add GCS enable and trap levels to DisasContext Richard Henderson
2025-10-08 21:55 ` [PATCH v7 33/73] target/arm: Implement FEAT_CHK Richard Henderson
2025-10-08 21:55 ` [PATCH v7 34/73] target/arm: Make helper_exception_return system-only Richard Henderson
2025-10-09 14:38   ` Philippe Mathieu-Daudé
2025-10-08 21:55 ` [PATCH v7 35/73] target/arm: Export cpsr_{read_for, write_from}_spsr_elx Richard Henderson
2025-10-09 14:37   ` Philippe Mathieu-Daudé
2025-10-08 21:55 ` [PATCH v7 36/73] target/arm: Expand pstate to 64 bits Richard Henderson
2025-10-08 21:55 ` [PATCH v7 37/73] target/arm: Add syndrome data for EC_GCS Richard Henderson
2025-10-08 21:55 ` [PATCH v7 38/73] target/arm: Add arm_hcr_el2_nvx_eff Richard Henderson
2025-10-09 14:34   ` Philippe Mathieu-Daudé
2025-10-08 21:55 ` [PATCH v7 39/73] target/arm: Use arm_hcr_el2_nvx_eff in access_nv1 Richard Henderson
2025-10-09 14:34   ` Philippe Mathieu-Daudé
2025-10-08 21:55 ` [PATCH v7 40/73] target/arm: Split out access_nv1_with_nvx Richard Henderson
2025-10-09 14:04   ` Philippe Mathieu-Daudé
2025-10-08 21:55 ` [PATCH v7 41/73] target/arm: Implement EXLOCKException for ELR_ELx and SPSR_ELx Richard Henderson
2025-10-08 21:55 ` [PATCH v7 42/73] target/arm: Split {full,core}_a64_user_mem_index Richard Henderson
2025-10-09 14:05   ` [PATCH v7 42/73] target/arm: Split {full, core}_a64_user_mem_index Philippe Mathieu-Daudé
2025-10-08 21:55 ` [PATCH v7 43/73] target/arm: Introduce delay_exception{_el} Richard Henderson
2025-10-08 21:55 ` [PATCH v7 44/73] target/arm: Emit HSTR trap exception out of line Richard Henderson
2025-10-08 21:55 ` [PATCH v7 45/73] target/arm: Emit v7m LTPSIZE " Richard Henderson
2025-10-08 21:55 ` [PATCH v7 46/73] target/arm: Implement GCSSTR, GCSSTTR Richard Henderson
2025-10-08 21:55 ` [PATCH v7 47/73] target/arm: Implement GCSB Richard Henderson
2025-10-08 21:55 ` [PATCH v7 48/73] target/arm: Implement GCSPUSHM Richard Henderson
2025-10-08 21:55 ` [PATCH v7 49/73] target/arm: Implement GCSPOPM Richard Henderson
2025-10-08 21:55 ` [PATCH v7 50/73] target/arm: Implement GCSPUSHX Richard Henderson
2025-10-08 21:55 ` [PATCH v7 51/73] target/arm: Implement GCSPOPX Richard Henderson
2025-10-08 21:55 ` [PATCH v7 52/73] target/arm: Implement GCSPOPCX Richard Henderson
2025-10-08 21:55 ` [PATCH v7 53/73] target/arm: Implement GCSSS1 Richard Henderson
2025-10-08 21:55 ` [PATCH v7 54/73] target/arm: Implement GCSSS2 Richard Henderson
2025-10-08 21:55 ` [PATCH v7 55/73] target/arm: Add gcs record for BL Richard Henderson
2025-10-08 21:55 ` [PATCH v7 56/73] target/arm: Add gcs record for BLR Richard Henderson
2025-10-08 21:55 ` [PATCH v7 57/73] target/arm: Add gcs record for BLR with PAuth Richard Henderson
2025-10-08 21:55 ` [PATCH v7 58/73] target/arm: Load gcs record for RET Richard Henderson
2025-10-08 21:55 ` [PATCH v7 59/73] target/arm: Load gcs record for RET with PAuth Richard Henderson
2025-10-08 21:56 ` [PATCH v7 60/73] target/arm: Copy EXLOCKEn to EXLOCK on exception to the same EL Richard Henderson
2025-10-08 21:56 ` [PATCH v7 61/73] target/arm: Implement EXLOCK check during exception return Richard Henderson
2025-10-08 21:56 ` [PATCH v7 62/73] target/arm: Enable FEAT_GCS with -cpu max Richard Henderson
2025-10-09 14:33   ` Philippe Mathieu-Daudé
2025-10-08 21:56 ` Richard Henderson [this message]
2025-10-08 21:56 ` [PATCH v7 64/73] linux-user/aarch64: Allocate new gcs stack on clone Richard Henderson
2025-10-08 21:56 ` [PATCH v7 65/73] linux-user/aarch64: Release gcs stack on thread exit Richard Henderson
2025-10-08 21:56 ` [PATCH v7 66/73] linux-user/aarch64: Implement map_shadow_stack syscall Richard Henderson
2025-10-08 21:56 ` [PATCH v7 67/73] target/arm: Enable GCSPR_EL0 for read in user-mode Richard Henderson
2025-10-08 21:56 ` [PATCH v7 68/73] linux-user/aarch64: Inject SIGSEGV for GCS faults Richard Henderson
2025-10-08 21:56 ` [PATCH v7 69/73] linux-user/aarch64: Generate GCS signal records Richard Henderson
2025-10-08 21:56 ` [PATCH v7 70/73] linux-user/aarch64: Enable GCS in HWCAP Richard Henderson
2025-10-08 21:56 ` [PATCH v7 71/73] tests/tcg/aarch64: Add gcsstr Richard Henderson
2025-10-08 21:56 ` [PATCH v7 72/73] tests/tcg/aarch64: Add gcspushm Richard Henderson
2025-10-08 21:56 ` [PATCH v7 73/73] tests/tcg/aarch64: Add gcsss Richard Henderson
2025-10-10 11:40 ` [PATCH v7 00/73] target/arm: Implement FEAT_GCS Peter Maydell

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