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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, Pierrick Bouvier <pierrick.bouvier@linaro.org>
Subject: [PATCH v7 71/73] tests/tcg/aarch64: Add gcsstr
Date: Wed,  8 Oct 2025 14:56:11 -0700	[thread overview]
Message-ID: <20251008215613.300150-72-richard.henderson@linaro.org> (raw)
In-Reply-To: <20251008215613.300150-1-richard.henderson@linaro.org>

Add some infrastructure for testing gcs in userspace.
Validate successful and trapped executions of GCSSTR.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tests/tcg/aarch64/gcs.h           | 71 +++++++++++++++++++++++++++++++
 tests/tcg/aarch64/gcsstr.c        | 48 +++++++++++++++++++++
 tests/tcg/aarch64/Makefile.target |  5 +++
 3 files changed, 124 insertions(+)
 create mode 100644 tests/tcg/aarch64/gcs.h
 create mode 100644 tests/tcg/aarch64/gcsstr.c

diff --git a/tests/tcg/aarch64/gcs.h b/tests/tcg/aarch64/gcs.h
new file mode 100644
index 0000000000..99cb4d4e38
--- /dev/null
+++ b/tests/tcg/aarch64/gcs.h
@@ -0,0 +1,71 @@
+/*
+ * Linux kernel fallback API definitions for GCS and test helpers.
+ *
+ * Copyright (c) 2025 Linaro Ltd
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <assert.h>
+#include <string.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <stdint.h>
+#include <unistd.h>
+#include <errno.h>
+#include <signal.h>
+#include <sys/mman.h>
+#include <sys/prctl.h>
+#include <sys/syscall.h>
+
+#ifndef PR_GET_SHADOW_STACK_STATUS
+#define PR_GET_SHADOW_STACK_STATUS	74
+#endif
+#ifndef PR_SET_SHADOW_STACK_STATUS
+#define PR_SET_SHADOW_STACK_STATUS      75
+#endif
+#ifndef PR_LOCK_SHADOW_STACK_STATUS
+#define PR_LOCK_SHADOW_STACK_STATUS     76
+#endif
+#ifndef PR_SHADOW_STACK_ENABLE
+# define PR_SHADOW_STACK_ENABLE         (1 << 0)
+# define PR_SHADOW_STACK_WRITE		(1 << 1)
+# define PR_SHADOW_STACK_PUSH		(1 << 2)
+#endif
+#ifndef SHADOW_STACK_SET_TOKEN
+#define SHADOW_STACK_SET_TOKEN          (1 << 0)
+#endif
+#ifndef SHADOW_STACK_SET_MARKER
+#define SHADOW_STACK_SET_MARKER         (1 << 1)
+#endif
+#ifndef SEGV_CPERR
+#define SEGV_CPERR  10
+#endif
+#ifndef __NR_map_shadow_stack
+#define __NR_map_shadow_stack  453
+#endif
+
+/*
+ * Macros, and implement the syscall inline, lest we fail
+ * the checked return from any function call.
+ */
+#define enable_gcs(flags) \
+    do {                                                                     \
+        register long num  __asm__ ("x8") = __NR_prctl;                      \
+        register long arg1 __asm__ ("x0") = PR_SET_SHADOW_STACK_STATUS;      \
+        register long arg2 __asm__ ("x1") = PR_SHADOW_STACK_ENABLE | flags;  \
+        register long arg3 __asm__ ("x2") = 0;                               \
+        register long arg4 __asm__ ("x3") = 0;                               \
+        register long arg5 __asm__ ("x4") = 0;                               \
+        asm volatile("svc #0"                                                \
+                     : "+r"(arg1)                                            \
+                     : "r"(arg2), "r"(arg3), "r"(arg4), "r"(arg5), "r"(num)  \
+                     : "memory", "cc");                                      \
+        if (arg1) {                                                          \
+            errno = -arg1;                                                   \
+            perror("PR_SET_SHADOW_STACK_STATUS");                            \
+            exit(2);                                                         \
+        }                                                                    \
+    } while (0)
+
+#define gcspr() \
+    ({ uint64_t *r; asm volatile("mrs %0, s3_3_c2_c5_1" : "=r"(r)); r; })
diff --git a/tests/tcg/aarch64/gcsstr.c b/tests/tcg/aarch64/gcsstr.c
new file mode 100644
index 0000000000..b045aee925
--- /dev/null
+++ b/tests/tcg/aarch64/gcsstr.c
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include "gcs.h"
+
+/*
+ * A single garbage store to the gcs stack.
+ * The asm inside must be unique, so disallow inlining.
+ */
+void __attribute__((noinline))
+test_gcsstr(void)
+{
+    register uint64_t *ptr __asm__("x0") = gcspr();
+    /* GCSSTR x1, x0 */
+    __asm__("inst_gcsstr: .inst 0xd91f1c01" : : "r"(--ptr));
+}
+
+static void test_sigsegv(int sig, siginfo_t *info, void *vuc)
+{
+    ucontext_t *uc = vuc;
+    uint64_t inst_gcsstr;
+
+    __asm__("adr %0, inst_gcsstr" : "=r"(inst_gcsstr));
+    assert(uc->uc_mcontext.pc == inst_gcsstr);
+    assert(info->si_code == SEGV_CPERR);
+    /* TODO: Dig for ESR and verify syndrome. */
+    exit(0);
+}
+
+int main()
+{
+    struct sigaction sa = {
+        .sa_sigaction = test_sigsegv,
+        .sa_flags = SA_SIGINFO,
+    };
+
+    /* Enable GCSSTR and test the store succeeds. */
+    enable_gcs(PR_SHADOW_STACK_WRITE);
+    test_gcsstr();
+
+    /* Disable GCSSTR and test the resulting sigsegv. */
+    enable_gcs(0);
+    if (sigaction(SIGSEGV, &sa, NULL) < 0) {
+        perror("sigaction");
+        exit(1);
+    }
+    test_gcsstr();
+    abort();
+}
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
index 1755874bee..5e1b3a3385 100644
--- a/tests/tcg/aarch64/Makefile.target
+++ b/tests/tcg/aarch64/Makefile.target
@@ -75,6 +75,11 @@ AARCH64_TESTS += $(SME_TESTS)
 $(SME_TESTS): CFLAGS += $(CROSS_AS_HAS_ARMV9_SME)
 endif
 
+# GCS Tests
+GCS_TESTS += gcsstr
+AARCH64_TESTS += $(GCS_TESTS)
+$(GCS_TESTS): gcs.h
+
 # System Registers Tests
 AARCH64_TESTS += sysregs
 
-- 
2.43.0



  parent reply	other threads:[~2025-10-08 22:09 UTC|newest]

Thread overview: 85+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-08 21:55 [PATCH v7 00/73] target/arm: Implement FEAT_GCS Richard Henderson
2025-10-08 21:55 ` [PATCH v7 01/73] tests/functional: update tests using TF-A/TF-RMM to support FEAT_GCS Richard Henderson
2025-10-08 21:55 ` [PATCH v7 02/73] target/arm: Add isar feature test for FEAT_S1PIE, FEAT_S2PIE Richard Henderson
2025-10-08 21:55 ` [PATCH v7 03/73] target/arm: Enable TCR2_ELx.PIE Richard Henderson
2025-10-08 21:55 ` [PATCH v7 04/73] target/arm: Implement PIR_ELx, PIRE0_ELx, S2PIR_EL2 registers Richard Henderson
2025-10-08 21:55 ` [PATCH v7 05/73] target/arm: Force HPD for stage2 translations Richard Henderson
2025-10-08 21:55 ` [PATCH v7 06/73] target/arm: Cache NV1 early in get_phys_addr_lpae Richard Henderson
2025-10-08 21:55 ` [PATCH v7 07/73] target/arm: Populate PIE in aa64_va_parameters Richard Henderson
2025-10-08 21:55 ` [PATCH v7 08/73] target/arm: Implement get_S1prot_indirect Richard Henderson
2025-10-08 21:55 ` [PATCH v7 09/73] target/arm: Implement get_S2prot_indirect Richard Henderson
2025-10-08 21:55 ` [PATCH v7 10/73] target/arm: Expand CPUARMState.exception.syndrome to 64 bits Richard Henderson
2025-10-09 14:14   ` Philippe Mathieu-Daudé
2025-10-09 17:43     ` Richard Henderson
2025-10-08 21:55 ` [PATCH v7 11/73] target/arm: Expand syndrome parameter to raise_exception* Richard Henderson
2025-10-08 21:55 ` [PATCH v7 12/73] target/arm: Implement dirtybit check for PIE Richard Henderson
2025-10-08 21:55 ` [PATCH v7 13/73] target/arm: Enable FEAT_S1PIE and FEAT_S2PIE on -cpu max Richard Henderson
2025-10-08 21:55 ` [PATCH v7 14/73] include/exec/memopidx: Adjust for 32 mmu indexes Richard Henderson
2025-10-09 14:03   ` Philippe Mathieu-Daudé
2025-10-08 21:55 ` [PATCH v7 15/73] include/hw/core/cpu: Widen MMUIdxMap Richard Henderson
2025-10-08 21:55 ` [PATCH v7 16/73] target/arm: Split out mmuidx.h from cpu.h Richard Henderson
2025-10-08 21:55 ` [PATCH v7 17/73] target/arm: Convert arm_mmu_idx_to_el from switch to table Richard Henderson
2025-10-08 21:55 ` [PATCH v7 18/73] target/arm: Remove unused env argument from regime_el Richard Henderson
2025-10-08 21:55 ` [PATCH v7 19/73] target/arm: Convert regime_el from switch to table Richard Henderson
2025-10-08 21:55 ` [PATCH v7 20/73] target/arm: Convert regime_has_2_ranges " Richard Henderson
2025-10-08 21:55 ` [PATCH v7 21/73] target/arm: Remove unused env argument from regime_is_pan Richard Henderson
2025-10-08 21:55 ` [PATCH v7 22/73] target/arm: Convert regime_is_pan from switch to table Richard Henderson
2025-10-08 21:55 ` [PATCH v7 23/73] target/arm: Remove unused env argument from regime_is_user Richard Henderson
2025-10-08 21:55 ` [PATCH v7 24/73] target/arm: Convert regime_is_user from switch to table Richard Henderson
2025-10-08 21:55 ` [PATCH v7 25/73] target/arm: Convert arm_mmu_idx_is_stage1_of_2 " Richard Henderson
2025-10-08 21:55 ` [PATCH v7 26/73] target/arm: Convert regime_is_stage2 " Richard Henderson
2025-10-08 21:55 ` [PATCH v7 27/73] target/arm: Introduce mmu indexes for GCS Richard Henderson
2025-10-08 21:55 ` [PATCH v7 28/73] target/arm: Introduce regime_to_gcs Richard Henderson
2025-10-08 21:55 ` [PATCH v7 29/73] target/arm: Support page protections for GCS mmu indexes Richard Henderson
2025-10-08 21:55 ` [PATCH v7 30/73] target/arm: Implement gcs bit for data abort Richard Henderson
2025-10-08 21:55 ` [PATCH v7 31/73] target/arm: Add GCS cpregs Richard Henderson
2025-10-08 21:55 ` [PATCH v7 32/73] target/arm: Add GCS enable and trap levels to DisasContext Richard Henderson
2025-10-08 21:55 ` [PATCH v7 33/73] target/arm: Implement FEAT_CHK Richard Henderson
2025-10-08 21:55 ` [PATCH v7 34/73] target/arm: Make helper_exception_return system-only Richard Henderson
2025-10-09 14:38   ` Philippe Mathieu-Daudé
2025-10-08 21:55 ` [PATCH v7 35/73] target/arm: Export cpsr_{read_for, write_from}_spsr_elx Richard Henderson
2025-10-09 14:37   ` Philippe Mathieu-Daudé
2025-10-08 21:55 ` [PATCH v7 36/73] target/arm: Expand pstate to 64 bits Richard Henderson
2025-10-08 21:55 ` [PATCH v7 37/73] target/arm: Add syndrome data for EC_GCS Richard Henderson
2025-10-08 21:55 ` [PATCH v7 38/73] target/arm: Add arm_hcr_el2_nvx_eff Richard Henderson
2025-10-09 14:34   ` Philippe Mathieu-Daudé
2025-10-08 21:55 ` [PATCH v7 39/73] target/arm: Use arm_hcr_el2_nvx_eff in access_nv1 Richard Henderson
2025-10-09 14:34   ` Philippe Mathieu-Daudé
2025-10-08 21:55 ` [PATCH v7 40/73] target/arm: Split out access_nv1_with_nvx Richard Henderson
2025-10-09 14:04   ` Philippe Mathieu-Daudé
2025-10-08 21:55 ` [PATCH v7 41/73] target/arm: Implement EXLOCKException for ELR_ELx and SPSR_ELx Richard Henderson
2025-10-08 21:55 ` [PATCH v7 42/73] target/arm: Split {full,core}_a64_user_mem_index Richard Henderson
2025-10-09 14:05   ` [PATCH v7 42/73] target/arm: Split {full, core}_a64_user_mem_index Philippe Mathieu-Daudé
2025-10-08 21:55 ` [PATCH v7 43/73] target/arm: Introduce delay_exception{_el} Richard Henderson
2025-10-08 21:55 ` [PATCH v7 44/73] target/arm: Emit HSTR trap exception out of line Richard Henderson
2025-10-08 21:55 ` [PATCH v7 45/73] target/arm: Emit v7m LTPSIZE " Richard Henderson
2025-10-08 21:55 ` [PATCH v7 46/73] target/arm: Implement GCSSTR, GCSSTTR Richard Henderson
2025-10-08 21:55 ` [PATCH v7 47/73] target/arm: Implement GCSB Richard Henderson
2025-10-08 21:55 ` [PATCH v7 48/73] target/arm: Implement GCSPUSHM Richard Henderson
2025-10-08 21:55 ` [PATCH v7 49/73] target/arm: Implement GCSPOPM Richard Henderson
2025-10-08 21:55 ` [PATCH v7 50/73] target/arm: Implement GCSPUSHX Richard Henderson
2025-10-08 21:55 ` [PATCH v7 51/73] target/arm: Implement GCSPOPX Richard Henderson
2025-10-08 21:55 ` [PATCH v7 52/73] target/arm: Implement GCSPOPCX Richard Henderson
2025-10-08 21:55 ` [PATCH v7 53/73] target/arm: Implement GCSSS1 Richard Henderson
2025-10-08 21:55 ` [PATCH v7 54/73] target/arm: Implement GCSSS2 Richard Henderson
2025-10-08 21:55 ` [PATCH v7 55/73] target/arm: Add gcs record for BL Richard Henderson
2025-10-08 21:55 ` [PATCH v7 56/73] target/arm: Add gcs record for BLR Richard Henderson
2025-10-08 21:55 ` [PATCH v7 57/73] target/arm: Add gcs record for BLR with PAuth Richard Henderson
2025-10-08 21:55 ` [PATCH v7 58/73] target/arm: Load gcs record for RET Richard Henderson
2025-10-08 21:55 ` [PATCH v7 59/73] target/arm: Load gcs record for RET with PAuth Richard Henderson
2025-10-08 21:56 ` [PATCH v7 60/73] target/arm: Copy EXLOCKEn to EXLOCK on exception to the same EL Richard Henderson
2025-10-08 21:56 ` [PATCH v7 61/73] target/arm: Implement EXLOCK check during exception return Richard Henderson
2025-10-08 21:56 ` [PATCH v7 62/73] target/arm: Enable FEAT_GCS with -cpu max Richard Henderson
2025-10-09 14:33   ` Philippe Mathieu-Daudé
2025-10-08 21:56 ` [PATCH v7 63/73] linux-user/aarch64: Implement prctls for GCS Richard Henderson
2025-10-08 21:56 ` [PATCH v7 64/73] linux-user/aarch64: Allocate new gcs stack on clone Richard Henderson
2025-10-08 21:56 ` [PATCH v7 65/73] linux-user/aarch64: Release gcs stack on thread exit Richard Henderson
2025-10-08 21:56 ` [PATCH v7 66/73] linux-user/aarch64: Implement map_shadow_stack syscall Richard Henderson
2025-10-08 21:56 ` [PATCH v7 67/73] target/arm: Enable GCSPR_EL0 for read in user-mode Richard Henderson
2025-10-08 21:56 ` [PATCH v7 68/73] linux-user/aarch64: Inject SIGSEGV for GCS faults Richard Henderson
2025-10-08 21:56 ` [PATCH v7 69/73] linux-user/aarch64: Generate GCS signal records Richard Henderson
2025-10-08 21:56 ` [PATCH v7 70/73] linux-user/aarch64: Enable GCS in HWCAP Richard Henderson
2025-10-08 21:56 ` Richard Henderson [this message]
2025-10-08 21:56 ` [PATCH v7 72/73] tests/tcg/aarch64: Add gcspushm Richard Henderson
2025-10-08 21:56 ` [PATCH v7 73/73] tests/tcg/aarch64: Add gcsss Richard Henderson
2025-10-10 11:40 ` [PATCH v7 00/73] target/arm: Implement FEAT_GCS Peter Maydell

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