From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4F42ECAC5BB for ; Wed, 8 Oct 2025 22:07:04 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v6c9Y-0003zf-JU; Wed, 08 Oct 2025 17:56:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v6c9T-0003xe-3z for qemu-devel@nongnu.org; Wed, 08 Oct 2025 17:56:51 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v6c91-0006dh-IQ for qemu-devel@nongnu.org; Wed, 08 Oct 2025 17:56:49 -0400 Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-27d3540a43fso2936745ad.3 for ; Wed, 08 Oct 2025 14:56:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1759960580; x=1760565380; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vPXa4J7vTcsuHyJDfp39GjPEdE8Jk9DcDrsqJJqeM7s=; b=UI+h4Ayt23BJg7fxR0X1pJdWJyO81vC38cd9KgQ5KdAcLPHfnUUfopWUBJmV9qqYVa mVXR6D25rOcIYFb0ydQ0A3ZkuVk5Zzl6RwdvQJdnzGDoV+TyomTES//juYJ1xMGnPA/j svXPQwHD4b9XgpUMyuPaH9CBw2rWHCw4c6MwshDmjiHZ/dok4fYyRhgg80/qFoG6i9qf /Uc0F/ldLZFOXoC5ZaQtG4K5AFc3UErKDCHYckj0z2SLx8Q7Pjnu/dFZN+YNZ+TWMHvv Wg/32IX2Du11rqxGptciK62v1jdh0PgfK4iboY9azuE/sBPKOWbAaIGqZdUEXNxyUtwt nGQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1759960580; x=1760565380; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vPXa4J7vTcsuHyJDfp39GjPEdE8Jk9DcDrsqJJqeM7s=; b=SZst153CmbzTfY0ahilaVqlhL0Hq0bcALaK2A20W8lDggkekbe9DTBwo+XHaKLOYl4 ++50q3/1smH29+d4OOa4TCwQu/geVs7E95TA60cavAbwnL484UZgym+TiKWn5lBwNE9e 4PqsOPPF5ScsNtg0El8VztdAcw3h1bBdz9DsE5PjWwujL5dTJZsB9iaYZIKTwhvHeNfM DKPP3YPd+DPdMVUwkllEzLQ0r5l/6Hg0ssm6/a95MB61YI1uy02G3hZ+NUrV1sf5Q356 F5Uw4vcmAq7LPMxsjBrFGFEozgthgQqbNcyO49jkwxt9qft8Q3qYsxJ5Rr9gV8Ay89/b z/9w== X-Gm-Message-State: AOJu0YxCfKktVWenslBQum7nSgYwF6vasmWWcjp4/kVj0syCd8bXDXWf TIfAQ/FaPvgtKjE4XKWQAuWn3fZY7KLFoeJ1x02TiYg13SXwTc3BozK3UtOHwZwqrOQHb/2bOaP s0zqNq/A= X-Gm-Gg: ASbGncvqqxv5LxoZPvr0CBtKb9fj77/atNS8UsBWl8j5uH+9NmuOmLTky4D7WVtq/SR TkpGIk2BRq7oFJV41lnIoPXBghyM0/1+wTlEXflTJlFX01t9TTTcu6NFDD1SdsGbTf7b0y4NLYZ CYksDfKYzfiQApzZVicD+HI2rYprJ+W857+20U+pDSt4UbVKVfQB6NcXq29Q7BHwgQ+RDaP6zQm +JhRwc7BAlF0lmqCWmq6XrRCkt3CbDQn0THsqB2ktrOxD+Tzl6A3bqAyHiN2aiCI83yExTC3wjU JGA2hyGUKpZzdLCpH9DsKHFNkIGz7EluY+4AzkX8plZGUH0CzCqXMSbbTshwEnyM5r2xcsLyz2v qzCs5S/z5+mMrmOhvb4Zv3HN7t9JLRi+OwKrFU29uQRCtp8PbL7FsDvTe X-Google-Smtp-Source: AGHT+IEzM9zcctUqd2KRESzpG2YQQyAPhEFjCjGUnKq5+1NtVL1coXofFCBsj+23FdwA7iQJpCnlQA== X-Received: by 2002:a17:903:1aae:b0:273:7d52:e510 with SMTP id d9443c01a7336-290273038c3mr62294065ad.58.1759960580075; Wed, 08 Oct 2025 14:56:20 -0700 (PDT) Received: from stoup.. ([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29034e44ef9sm7354285ad.52.2025.10.08.14.56.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Oct 2025 14:56:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v7 08/73] target/arm: Implement get_S1prot_indirect Date: Wed, 8 Oct 2025 14:55:08 -0700 Message-ID: <20251008215613.300150-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251008215613.300150-1-richard.henderson@linaro.org> References: <20251008215613.300150-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This approximately corresponds to AArch64.S1IndirectBasePermissions and the tail of AArch64.S1ComputePermissions which applies WXN. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/ptw.c | 161 ++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 139 insertions(+), 22 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index e1515675eb..5913556077 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1484,6 +1484,106 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, return prot_rw | PAGE_EXEC; } +/* Extra page permission bits, during get_S1prot_indirect only. */ +#define PAGE_GCS (1 << 3) +#define PAGE_WXN (1 << 4) +#define PAGE_OVERLAY (1 << 5) +QEMU_BUILD_BUG_ON(PAGE_RWX & (PAGE_GCS | PAGE_WXN | PAGE_OVERLAY)); + +static int get_S1prot_indirect(CPUARMState *env, S1Translate *ptw, + ARMMMUIdx mmu_idx, int pi_index, int po_index, + ARMSecuritySpace in_pa, ARMSecuritySpace out_pa) +{ + static const uint8_t perm_table[16] = { + /* 0 */ PAGE_OVERLAY, /* no access */ + /* 1 */ PAGE_OVERLAY | PAGE_READ, + /* 2 */ PAGE_OVERLAY | PAGE_EXEC, + /* 3 */ PAGE_OVERLAY | PAGE_READ | PAGE_EXEC, + /* 4 */ PAGE_OVERLAY, /* reserved */ + /* 5 */ PAGE_OVERLAY | PAGE_READ | PAGE_WRITE, + /* 6 */ PAGE_OVERLAY | PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_WXN, + /* 7 */ PAGE_OVERLAY | PAGE_READ | PAGE_WRITE | PAGE_EXEC, + /* 8 */ PAGE_READ, + /* 9 */ PAGE_READ | PAGE_GCS, + /* A */ PAGE_READ | PAGE_EXEC, + /* B */ 0, /* reserved */ + /* C */ PAGE_READ | PAGE_WRITE, + /* D */ 0, /* reserved */ + /* E */ PAGE_READ | PAGE_WRITE | PAGE_EXEC, + /* F */ 0, /* reserved */ + }; + + uint32_t el = regime_el(env, mmu_idx); + uint64_t pir = env->cp15.pir_el[el]; + uint64_t pire0 = 0; + int perm; + + if (el < 3) { + if (arm_feature(env, ARM_FEATURE_EL3) + && !(env->cp15.scr_el3 & SCR_PIEN)) { + pir = 0; + } else if (el == 2) { + pire0 = env->cp15.pire0_el2; + } else if (!ptw->in_nv1) { + pire0 = env->cp15.pir_el[0]; + } + } + perm = perm_table[extract64(pir, pi_index * 4, 4)]; + + if (regime_has_2_ranges(mmu_idx)) { + int p_perm = perm; + int u_perm = perm_table[extract64(pire0, pi_index * 4, 4)]; + + if ((p_perm & (PAGE_EXEC | PAGE_GCS)) && + (u_perm & (PAGE_WRITE | PAGE_GCS))) { + p_perm &= ~(PAGE_RWX | PAGE_GCS); + u_perm &= ~(PAGE_RWX | PAGE_GCS); + } + if ((u_perm & (PAGE_RWX | PAGE_GCS)) && regime_is_pan(env, mmu_idx)) { + p_perm &= ~(PAGE_READ | PAGE_WRITE); + } + perm = regime_is_user(env, mmu_idx) ? u_perm : p_perm; + } + + if (in_pa != out_pa) { + switch (in_pa) { + case ARMSS_Root: + /* + * R_ZWRVD: permission fault for insn fetched from non-Root, + * I_WWBFB: SIF has no effect in EL3. + */ + perm &= ~(PAGE_EXEC | PAGE_GCS); + break; + case ARMSS_Realm: + /* + * R_PKTDS: permission fault for insn fetched from non-Realm, + * for Realm EL2 or EL2&0. The corresponding fault for EL1&0 + * happens during any stage2 translation. + */ + if (el == 2) { + perm &= ~(PAGE_EXEC | PAGE_GCS); + } + break; + case ARMSS_Secure: + if (env->cp15.scr_el3 & SCR_SIF) { + perm &= ~(PAGE_EXEC | PAGE_GCS); + } + break; + default: + /* Input NonSecure must have output NonSecure. */ + g_assert_not_reached(); + } + } + + if (perm & PAGE_WXN) { + perm &= ~PAGE_EXEC; + } + + /* TODO: FEAT_GCS */ + + return perm & PAGE_RWX; +} + static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, ARMMMUIdx mmu_idx) { @@ -1713,7 +1813,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, int32_t stride; int addrsize, inputsize, outputsize; uint64_t tcr = regime_tcr(env, mmu_idx); - int ap, xn, pxn; + int ap; uint32_t el = regime_el(env, mmu_idx); uint64_t descaddrmask; bool aarch64 = arm_el_is_aa64(env, el); @@ -2047,7 +2147,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, out_space = ARMSS_NonSecure; result->f.prot = get_S2prot_noexecute(ap); } else { - xn = extract64(attrs, 53, 2); + int xn = extract64(attrs, 53, 2); result->f.prot = get_S2prot(env, ap, xn, ptw->in_s1_is_el0); } @@ -2063,7 +2163,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, int nse, ns = extract32(attrs, 5, 1); uint8_t attrindx; uint64_t mair; - int user_rw, prot_rw; switch (out_space) { case ARMSS_Root: @@ -2112,29 +2211,47 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, default: g_assert_not_reached(); } - xn = extract64(attrs, 54, 1); - pxn = extract64(attrs, 53, 1); - if (el == 1 && ptw->in_nv1) { + if (param.pie) { + int pi = extract64(attrs, 6, 1) + | (extract64(attrs, 51, 1) << 1) + | (extract64(attrs, 53, 2) << 2); + int po = extract64(attrs, 60, 3); /* - * With FEAT_NV, when HCR_EL2.{NV,NV1} == {1,1}, the block/page - * descriptor bit 54 holds PXN, 53 is RES0, and the effective value - * of UXN is 0. Similarly for bits 59 and 60 in table descriptors - * (which we have already folded into bits 53 and 54 of attrs). - * AP[1] (descriptor bit 6, our ap bit 0) is treated as 0. - * Similarly, APTable[0] from the table descriptor is treated as 0; - * we already folded this into AP[1] and squashing that to 0 does - * the right thing. + * Note that we modified ptw->in_space earlier for NSTable, but + * result->f.attrs retains a copy of the original security space. */ - pxn = xn; - xn = 0; - ap &= ~1; - } + result->f.prot = get_S1prot_indirect(env, ptw, mmu_idx, pi, po, + result->f.attrs.space, + out_space); + } else { + int xn = extract64(attrs, 54, 1); + int pxn = extract64(attrs, 53, 1); + int user_rw, prot_rw; - user_rw = simple_ap_to_rw_prot_is_user(ap, true); - prot_rw = simple_ap_to_rw_prot_is_user(ap, false); - result->f.prot = get_S1prot(env, mmu_idx, aarch64, user_rw, prot_rw, - xn, pxn, ptw->in_space, out_space); + if (el == 1 && ptw->in_nv1) { + /* + * With FEAT_NV, when HCR_EL2.{NV,NV1} == {1,1}, + * the block/page descriptor bit 54 holds PXN, + * 53 is RES0, and the effective value of UXN is 0. + * Similarly for bits 59 and 60 in table descriptors + * (which we have already folded into bits 53 and 54 of attrs). + * AP[1] (descriptor bit 6, our ap bit 0) is treated as 0. + * Similarly, APTable[0] from the table descriptor is treated + * as 0; we already folded this into AP[1] and squashing + * that to 0 does the right thing. + */ + pxn = xn; + xn = 0; + ap &= ~1; + } + + user_rw = simple_ap_to_rw_prot_is_user(ap, true); + prot_rw = simple_ap_to_rw_prot_is_user(ap, false); + result->f.prot = get_S1prot(env, mmu_idx, aarch64, + user_rw, prot_rw, xn, pxn, + ptw->in_space, out_space); + } /* Index into MAIR registers for cache attributes */ attrindx = extract32(attrs, 2, 3); -- 2.43.0