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From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Anton Johansson" <anjo@rev.ng>,
	"Pierrick Bouvier" <pierrick.bouvier@linaro.org>,
	"Stafford Horne" <shorne@gmail.com>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PATCH v2 06/10] target/openrisc: Remove target_ulong use in raise_mmu_exception()
Date: Thu,  9 Oct 2025 10:18:58 +0200	[thread overview]
Message-ID: <20251009081903.13426-7-philmd@linaro.org> (raw)
In-Reply-To: <20251009081903.13426-1-philmd@linaro.org>

TCGCPUOps::tlb_fill() handler provides a vaddr type (since commit
7510454e3e7 "cpu: Turn cpu_handle_mmu_fault() into a CPUClass hook").

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
---
 target/openrisc/mmu.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c
index acea50c41eb..6fb3f6318a1 100644
--- a/target/openrisc/mmu.c
+++ b/target/openrisc/mmu.c
@@ -28,15 +28,14 @@
 #include "qemu/host-utils.h"
 #include "hw/loader.h"
 
-static inline void get_phys_nommu(hwaddr *phys_addr, int *prot,
-                                  target_ulong address)
+static inline void get_phys_nommu(hwaddr *phys_addr, int *prot, vaddr address)
 {
     *phys_addr = address;
     *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 }
 
 static int get_phys_mmu(OpenRISCCPU *cpu, hwaddr *phys_addr, int *prot,
-                        target_ulong addr, int need, bool super)
+                        vaddr addr, int need, bool super)
 {
     int idx = (addr >> TARGET_PAGE_BITS) & TLB_MASK;
     uint32_t imr = cpu->env.tlb.itlb[idx].mr;
@@ -95,7 +94,7 @@ static int get_phys_mmu(OpenRISCCPU *cpu, hwaddr *phys_addr, int *prot,
     }
 }
 
-static void raise_mmu_exception(OpenRISCCPU *cpu, target_ulong address,
+static void raise_mmu_exception(OpenRISCCPU *cpu, vaddr address,
                                 int exception)
 {
     CPUState *cs = CPU(cpu);
-- 
2.51.0



  parent reply	other threads:[~2025-10-09  8:23 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-09  8:18 [PATCH v2 00/10] target/openrisc: Remove all uses of target_[u]long types Philippe Mathieu-Daudé
2025-10-09  8:18 ` [PATCH v2 01/10] target/openrisc: Replace VMSTATE_UINTTL() -> VMSTATE_UINT32() Philippe Mathieu-Daudé
2025-10-09 16:41   ` Richard Henderson
2025-10-09  8:18 ` [PATCH v2 02/10] target/openrisc: Explode MO_TExx -> MO_TE | MO_xx Philippe Mathieu-Daudé
2025-10-09 16:43   ` Richard Henderson
2025-10-10  6:56     ` Philippe Mathieu-Daudé
2025-10-09  8:18 ` [PATCH v2 03/10] target/openrisc: Replace MO_TE -> MO_BE Philippe Mathieu-Daudé
2025-10-09  9:19   ` Philippe Mathieu-Daudé
2025-10-09  8:18 ` [PATCH v2 04/10] target/openrisc: Do not use target_ulong for @mr in MTSPR helper Philippe Mathieu-Daudé
2025-10-09 16:45   ` Richard Henderson
2025-10-09  8:18 ` [PATCH v2 05/10] target/openrisc: Remove unused cpu_openrisc_map_address_*() handlers Philippe Mathieu-Daudé
2025-10-09 16:47   ` Richard Henderson
2025-10-09  8:18 ` Philippe Mathieu-Daudé [this message]
2025-10-09 16:48   ` [PATCH v2 06/10] target/openrisc: Remove target_ulong use in raise_mmu_exception() Richard Henderson
2025-10-09  8:18 ` [PATCH v2 07/10] target/openrisc: Use vaddr type for $pc jumps Philippe Mathieu-Daudé
2025-10-09 16:49   ` Richard Henderson
2025-10-09  8:19 ` [PATCH v2 08/10] target/openrisc: Remove 'TARGET_LONG_BITS != 32' dead code Philippe Mathieu-Daudé
2025-10-09 16:50   ` Richard Henderson
2025-10-09  8:19 ` [PATCH v2 09/10] target/openrisc: Inline tcg_gen_trunc_i64_tl() Philippe Mathieu-Daudé
2025-10-09 16:50   ` Richard Henderson
2025-10-09  8:19 ` [PATCH v2 10/10] target/openrisc: Replace target_ulong -> uint32_t Philippe Mathieu-Daudé
2025-10-09 16:52   ` Richard Henderson

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