From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Alex Bennée" <alex.bennee@linaro.org>,
"Thomas Huth" <thuth@redhat.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Marc-André Lureau" <marcandre.lureau@redhat.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
devel@lists.libvirt.org, "Jiaxun Yang" <jiaxun.yang@flygoat.com>,
"Aleksandar Rikalo" <arikalo@gmail.com>,
"Riku Voipio" <riku.voipio@iki.fi>,
"Daniel P. Berrangé" <berrange@redhat.com>,
"Huacai Chen" <chenhuacai@kernel.org>,
"Aurelien Jarno" <aurelien@aurel32.net>
Subject: [PATCH v2 4/7] tcg/mips: Remove support for O32 and N32 ABIs
Date: Thu, 9 Oct 2025 21:52:07 +0200 [thread overview]
Message-ID: <20251009195210.33161-5-philmd@linaro.org> (raw)
In-Reply-To: <20251009195210.33161-1-philmd@linaro.org>
See previous commit for rationale.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
tcg/mips/tcg-target-reg-bits.h | 9 ++----
tcg/mips/tcg-target.c.inc | 15 ++--------
common-user/host/mips/safe-syscall.inc.S | 35 ------------------------
3 files changed, 6 insertions(+), 53 deletions(-)
diff --git a/tcg/mips/tcg-target-reg-bits.h b/tcg/mips/tcg-target-reg-bits.h
index a957d2312f3..ee346a3f256 100644
--- a/tcg/mips/tcg-target-reg-bits.h
+++ b/tcg/mips/tcg-target-reg-bits.h
@@ -7,13 +7,10 @@
#ifndef TCG_TARGET_REG_BITS_H
#define TCG_TARGET_REG_BITS_H
-#if defined(_ABIO32) && _MIPS_SIM == _ABIO32
-# define TCG_TARGET_REG_BITS 32
-#elif (defined(_ABIN32) && _MIPS_SIM == _ABIN32) \
- || (defined(_ABI64) && _MIPS_SIM == _ABI64)
-# define TCG_TARGET_REG_BITS 64
-#else
+#if !defined(_MIPS_SIM) || _MIPS_SIM != _ABI64
# error "Unknown ABI"
#endif
+#define TCG_TARGET_REG_BITS 64
+
#endif
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index 045565f4ca8..77af0d8658a 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -26,15 +26,9 @@
/* used for function call generation */
#define TCG_TARGET_STACK_ALIGN 16
-#if defined(_ABIO32) && _MIPS_SIM == _ABIO32
-# define TCG_TARGET_CALL_STACK_OFFSET 16
-# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN
-# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF
-#else
-# define TCG_TARGET_CALL_STACK_OFFSET 0
-# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL
-# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL
-#endif
+#define TCG_TARGET_CALL_STACK_OFFSET 0
+#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL
+#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL
#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL
#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN
@@ -135,13 +129,10 @@ static const TCGReg tcg_target_call_iarg_regs[] = {
TCG_REG_A1,
TCG_REG_A2,
TCG_REG_A3,
-#if (defined(_ABIN32) && _MIPS_SIM == _ABIN32) \
- || (defined(_ABI64) && _MIPS_SIM == _ABI64)
TCG_REG_T0,
TCG_REG_T1,
TCG_REG_T2,
TCG_REG_T3,
-#endif
};
static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
diff --git a/common-user/host/mips/safe-syscall.inc.S b/common-user/host/mips/safe-syscall.inc.S
index 8857d708dae..3b196cc634c 100644
--- a/common-user/host/mips/safe-syscall.inc.S
+++ b/common-user/host/mips/safe-syscall.inc.S
@@ -30,15 +30,9 @@
* arguments being syscall arguments (also 'long').
*/
-#if defined(_ABIO32) && _MIPS_SIM == _ABIO32
-/* 8 * 4 = 32 for outgoing parameters; 1 * 4 for s0 save; 1 * 4 for align. */
-#define FRAME 40
-#define OFS_S0 32
-#else
/* 1 * 8 for s0 save; 1 * 8 for align. */
#define FRAME 16
#define OFS_S0 0
-#endif
NESTED(safe_syscall_base, FRAME, ra)
@@ -47,34 +41,6 @@ NESTED(safe_syscall_base, FRAME, ra)
.cfi_adjust_cfa_offset FRAME
REG_S s0, OFS_S0(sp)
.cfi_rel_offset s0, OFS_S0
-#if defined(_ABIO32) && _MIPS_SIM == _ABIO32
- /*
- * The syscall calling convention is nearly the same as C:
- * we enter with a0 == &signal_pending
- * a1 == syscall number
- * a2, a3, stack == syscall arguments
- * and return the result in a0
- * and the syscall instruction needs
- * v0 == syscall number
- * a0 ... a3, stack == syscall arguments
- * and returns the result in v0
- * Shuffle everything around appropriately.
- */
- move s0, a0 /* signal_pending pointer */
- move v0, a1 /* syscall number */
- move a0, a2 /* syscall arguments */
- move a1, a3
- lw a2, FRAME+16(sp)
- lw a3, FRAME+20(sp)
- lw t4, FRAME+24(sp)
- lw t5, FRAME+28(sp)
- lw t6, FRAME+32(sp)
- lw t7, FRAME+40(sp)
- sw t4, 16(sp)
- sw t5, 20(sp)
- sw t6, 24(sp)
- sw t7, 28(sp)
-#else
/*
* The syscall calling convention is nearly the same as C:
* we enter with a0 == &signal_pending
@@ -95,7 +61,6 @@ NESTED(safe_syscall_base, FRAME, ra)
move a3, a5
move a4, a6
move a5, a7
-#endif
/*
* This next sequence of code works in conjunction with the
--
2.51.0
next prev parent reply other threads:[~2025-10-09 19:53 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-09 19:52 [PATCH v2 0/7] tcg/mips: Remove support for 32-bit hosts Philippe Mathieu-Daudé
2025-10-09 19:52 ` [PATCH v2 1/7] docker: Remove 32-bit MIPS toolchain from debian-all-test image Philippe Mathieu-Daudé
2025-10-09 19:52 ` [PATCH v2 2/7] gitlab: Stop cross-testing for 32-bit MIPS hosts Philippe Mathieu-Daudé
2025-10-09 19:52 ` [PATCH v2 3/7] docker: Stop building 32-bit MIPS images Philippe Mathieu-Daudé
2025-10-09 19:52 ` Philippe Mathieu-Daudé [this message]
2025-10-10 6:45 ` [PATCH v2 4/7] tcg/mips: Remove support for O32 and N32 ABIs Thomas Huth
2025-10-09 19:52 ` [PATCH v2 5/7] tcg/mips: Remove support for 32-bit hosts Philippe Mathieu-Daudé
2025-10-10 6:51 ` Thomas Huth
2025-10-09 19:52 ` [PATCH v2 6/7] kvm/mips: " Philippe Mathieu-Daudé
2025-10-10 6:52 ` Thomas Huth
2025-10-09 19:52 ` [PATCH v2 7/7] buildsys: Remove support for 32-bit MIPS hosts Philippe Mathieu-Daudé
2025-10-10 6:53 ` Thomas Huth
2025-10-10 8:46 ` Daniel P. Berrangé
2025-10-10 10:39 ` Philippe Mathieu-Daudé
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