* [PATCH 00/12] target/tricore: Remove all uses of target_ulong types
@ 2025-10-10 5:21 Philippe Mathieu-Daudé
2025-10-10 5:21 ` [PATCH 01/12] target/tricore: Remove target_ulong use in gen_goto_tb() Philippe Mathieu-Daudé
` (11 more replies)
0 siblings, 12 replies; 25+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-10 5:21 UTC (permalink / raw)
To: qemu-devel
Cc: Bastian Koppelmann, Pierrick Bouvier, Anton Johansson,
Philippe Mathieu-Daudé
Remove incorrect target_ulong uses, then for the rest
mechanically convert:
- target_ulong -> uint32_t
- TCGv -> TCGv_i32
- tcg_temp_new() -> tcg_temp_new_i32()
Based-on: <20251010031745.37528-1-philmd@linaro.org>
Philippe Mathieu-Daudé (12):
target/tricore: Remove target_ulong use in gen_goto_tb()
target/tricore: Replace target_ulong -> vaddr with tlb_fill() callees
target/tricore: Remove target_ulong use in translate_insn() handler
target/tricore: Remove target_ulong use in gen_addi_d()
target/tricore: Remove unnecessary cast to target_ulong
target/tricore: Replace target_ulong -> uint32_t in op_helper.c
target/tricore: Declare registers as TCGv_i32
target/tricore: Inline tcg_gen_ld32u_tl()
target/tricore: Expand TCG helpers for 32-bit target
target/tricore: Pass DisasContext as first argument
target/tricore: Un-inline various helpers
target/tricore: Expand TCGv type for 32-bit target
target/tricore/cpu.c | 2 +-
target/tricore/helper.c | 4 +-
target/tricore/op_helper.c | 219 +-
target/tricore/translate.c | 3969 ++++++++++++++++++------------------
4 files changed, 2107 insertions(+), 2087 deletions(-)
--
2.51.0
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH 01/12] target/tricore: Remove target_ulong use in gen_goto_tb()
2025-10-10 5:21 [PATCH 00/12] target/tricore: Remove all uses of target_ulong types Philippe Mathieu-Daudé
@ 2025-10-10 5:21 ` Philippe Mathieu-Daudé
2025-10-10 16:56 ` Richard Henderson
2025-10-10 5:21 ` [PATCH 02/12] target/tricore: Replace target_ulong -> vaddr with tlb_fill() callees Philippe Mathieu-Daudé
` (10 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-10 5:21 UTC (permalink / raw)
To: qemu-devel
Cc: Bastian Koppelmann, Pierrick Bouvier, Anton Johansson,
Philippe Mathieu-Daudé
translator_use_goto_tb() expects a vaddr type since commit
b1c09220b4c ("accel/tcg: Replace target_ulong with vaddr in
translator_*()").
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/tricore/translate.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 7c6e3095971..dd09f0651f5 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -72,7 +72,8 @@ static const char *regnames_d[] = {
typedef struct DisasContext {
DisasContextBase base;
- target_ulong pc_succ_insn;
+
+ vaddr pc_succ_insn;
uint32_t opcode;
/* Routine used to access memory */
int mem_idx;
@@ -2811,13 +2812,12 @@ static void gen_calc_usb_mulr_h(TCGv arg)
/* helpers for generating program flow micro-ops */
-static inline void gen_save_pc(target_ulong pc)
+static inline void gen_save_pc(vaddr pc)
{
tcg_gen_movi_tl(cpu_PC, pc);
}
-static void gen_goto_tb(DisasContext *ctx, unsigned tb_slot_index,
- target_ulong dest)
+static void gen_goto_tb(DisasContext *ctx, unsigned tb_slot_index, vaddr dest)
{
if (translator_use_goto_tb(&ctx->base, dest)) {
tcg_gen_goto_tb(tb_slot_index);
--
2.51.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 02/12] target/tricore: Replace target_ulong -> vaddr with tlb_fill() callees
2025-10-10 5:21 [PATCH 00/12] target/tricore: Remove all uses of target_ulong types Philippe Mathieu-Daudé
2025-10-10 5:21 ` [PATCH 01/12] target/tricore: Remove target_ulong use in gen_goto_tb() Philippe Mathieu-Daudé
@ 2025-10-10 5:21 ` Philippe Mathieu-Daudé
2025-10-10 16:56 ` Richard Henderson
2025-10-10 5:21 ` [PATCH 03/12] target/tricore: Remove target_ulong use in translate_insn() handler Philippe Mathieu-Daudé
` (9 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-10 5:21 UTC (permalink / raw)
To: qemu-devel
Cc: Bastian Koppelmann, Pierrick Bouvier, Anton Johansson,
Philippe Mathieu-Daudé
tlb_fill() provides a vaddr type since commit 68d6eee73c
("target/tricore: Convert to CPUClass::tlb_fill").
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/tricore/helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/tricore/helper.c b/target/tricore/helper.c
index e4c53d453dd..7574111c87d 100644
--- a/target/tricore/helper.c
+++ b/target/tricore/helper.c
@@ -35,7 +35,7 @@ enum {
};
static int get_physical_address(CPUTriCoreState *env, hwaddr *physical,
- int *prot, target_ulong address,
+ int *prot, vaddr address,
MMUAccessType access_type, int mmu_idx)
{
int ret = TLBRET_MATCH;
@@ -61,7 +61,7 @@ hwaddr tricore_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
}
/* TODO: Add exception support */
-static void raise_mmu_exception(CPUTriCoreState *env, target_ulong address,
+static void raise_mmu_exception(CPUTriCoreState *env, vaddr address,
int rw, int tlb_error)
{
}
--
2.51.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 03/12] target/tricore: Remove target_ulong use in translate_insn() handler
2025-10-10 5:21 [PATCH 00/12] target/tricore: Remove all uses of target_ulong types Philippe Mathieu-Daudé
2025-10-10 5:21 ` [PATCH 01/12] target/tricore: Remove target_ulong use in gen_goto_tb() Philippe Mathieu-Daudé
2025-10-10 5:21 ` [PATCH 02/12] target/tricore: Replace target_ulong -> vaddr with tlb_fill() callees Philippe Mathieu-Daudé
@ 2025-10-10 5:21 ` Philippe Mathieu-Daudé
2025-10-10 16:57 ` Richard Henderson
2025-10-10 5:21 ` [PATCH 04/12] target/tricore: Remove target_ulong use in gen_addi_d() Philippe Mathieu-Daudé
` (8 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-10 5:21 UTC (permalink / raw)
To: qemu-devel
Cc: Bastian Koppelmann, Pierrick Bouvier, Anton Johansson,
Philippe Mathieu-Daudé
Since commit 85c19af63e7 ("include/exec: Use vaddr in DisasContextBase
for virtual addresses") the DisasContextBase::pc_first field is a
vaddr type.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/tricore/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index dd09f0651f5..4b769b204ab 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -8414,7 +8414,7 @@ static void tricore_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
ctx->base.pc_next = ctx->pc_succ_insn;
if (ctx->base.is_jmp == DISAS_NEXT) {
- target_ulong page_start;
+ vaddr page_start;
page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE
--
2.51.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 04/12] target/tricore: Remove target_ulong use in gen_addi_d()
2025-10-10 5:21 [PATCH 00/12] target/tricore: Remove all uses of target_ulong types Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2025-10-10 5:21 ` [PATCH 03/12] target/tricore: Remove target_ulong use in translate_insn() handler Philippe Mathieu-Daudé
@ 2025-10-10 5:21 ` Philippe Mathieu-Daudé
2025-10-10 16:59 ` Richard Henderson
2025-10-10 5:21 ` [PATCH 05/12] target/tricore: Remove unnecessary cast to target_ulong Philippe Mathieu-Daudé
` (7 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-10 5:21 UTC (permalink / raw)
To: qemu-devel
Cc: Bastian Koppelmann, Pierrick Bouvier, Anton Johansson,
Philippe Mathieu-Daudé
Callers pass either int32_t or int16_t.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/tricore/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 4b769b204ab..116f45135bb 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -1308,7 +1308,7 @@ gen_msubui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
gen_msubu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
}
-static inline void gen_addi_d(TCGv ret, TCGv r1, target_ulong r2)
+static inline void gen_addi_d(TCGv ret, TCGv r1, int32_t r2)
{
TCGv temp = tcg_constant_i32(r2);
gen_add_d(ret, r1, temp);
--
2.51.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 05/12] target/tricore: Remove unnecessary cast to target_ulong
2025-10-10 5:21 [PATCH 00/12] target/tricore: Remove all uses of target_ulong types Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2025-10-10 5:21 ` [PATCH 04/12] target/tricore: Remove target_ulong use in gen_addi_d() Philippe Mathieu-Daudé
@ 2025-10-10 5:21 ` Philippe Mathieu-Daudé
2025-10-10 16:59 ` Richard Henderson
2025-10-10 5:21 ` [PATCH 06/12] target/tricore: Replace target_ulong -> uint32_t in op_helper.c Philippe Mathieu-Daudé
` (6 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-10 5:21 UTC (permalink / raw)
To: qemu-devel
Cc: Bastian Koppelmann, Pierrick Bouvier, Anton Johansson,
Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/tricore/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 4f035b6f768..04319e107ba 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -37,7 +37,7 @@ static const gchar *tricore_gdb_arch_name(CPUState *cs)
static void tricore_cpu_set_pc(CPUState *cs, vaddr value)
{
- cpu_env(cs)->PC = value & ~(target_ulong)1;
+ cpu_env(cs)->PC = value & ~1;
}
static vaddr tricore_cpu_get_pc(CPUState *cs)
--
2.51.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 06/12] target/tricore: Replace target_ulong -> uint32_t in op_helper.c
2025-10-10 5:21 [PATCH 00/12] target/tricore: Remove all uses of target_ulong types Philippe Mathieu-Daudé
` (4 preceding siblings ...)
2025-10-10 5:21 ` [PATCH 05/12] target/tricore: Remove unnecessary cast to target_ulong Philippe Mathieu-Daudé
@ 2025-10-10 5:21 ` Philippe Mathieu-Daudé
2025-10-10 17:01 ` Richard Henderson
2025-10-10 5:21 ` [PATCH 07/12] target/tricore: Declare registers as TCGv_i32 Philippe Mathieu-Daudé
` (5 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-10 5:21 UTC (permalink / raw)
To: qemu-devel
Cc: Bastian Koppelmann, Pierrick Bouvier, Anton Johansson,
Philippe Mathieu-Daudé
The TriCore target is only built as 32-bit:
$ git grep TARGET_LONG_BITS configs/targets/tricore-*
configs/targets/tricore-softmmu.mak:2:TARGET_LONG_BITS=32
Therefore target_ulong type always expands to uint32_t.
This is a mechanical replacement.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/tricore/op_helper.c | 219 +++++++++++++++++--------------------
1 file changed, 103 insertions(+), 116 deletions(-)
diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c
index 9910c13f4b5..610f148a237 100644
--- a/target/tricore/op_helper.c
+++ b/target/tricore/op_helper.c
@@ -149,15 +149,15 @@ static uint32_t ssov32(CPUTriCoreState *env, int64_t arg)
if (arg > max_pos) {
env->PSW_USB_V = (1 << 31);
env->PSW_USB_SV = (1 << 31);
- ret = (target_ulong)max_pos;
+ ret = (uint32_t)max_pos;
} else {
if (arg < max_neg) {
env->PSW_USB_V = (1 << 31);
env->PSW_USB_SV = (1 << 31);
- ret = (target_ulong)max_neg;
+ ret = (uint32_t)max_neg;
} else {
env->PSW_USB_V = 0;
- ret = (target_ulong)arg;
+ ret = (uint32_t)arg;
}
}
env->PSW_USB_AV = arg ^ arg * 2u;
@@ -172,10 +172,10 @@ static uint32_t suov32_pos(CPUTriCoreState *env, uint64_t arg)
if (arg > max_pos) {
env->PSW_USB_V = (1 << 31);
env->PSW_USB_SV = (1 << 31);
- ret = (target_ulong)max_pos;
+ ret = (uint32_t)max_pos;
} else {
env->PSW_USB_V = 0;
- ret = (target_ulong)arg;
+ ret = (uint32_t)arg;
}
env->PSW_USB_AV = arg ^ arg * 2u;
env->PSW_USB_SAV |= env->PSW_USB_AV;
@@ -192,7 +192,7 @@ static uint32_t suov32_neg(CPUTriCoreState *env, int64_t arg)
ret = 0;
} else {
env->PSW_USB_V = 0;
- ret = (target_ulong)arg;
+ ret = (uint32_t)arg;
}
env->PSW_USB_AV = arg ^ arg * 2u;
env->PSW_USB_SAV |= env->PSW_USB_AV;
@@ -260,8 +260,7 @@ static uint32_t suov16(CPUTriCoreState *env, int32_t hw0, int32_t hw1)
return (hw0 & 0xffff) | (hw1 << 16);
}
-target_ulong helper_add_ssov(CPUTriCoreState *env, target_ulong r1,
- target_ulong r2)
+uint32_t helper_add_ssov(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
{
int64_t t1 = sextract64(r1, 0, 32);
int64_t t2 = sextract64(r2, 0, 32);
@@ -294,8 +293,7 @@ uint64_t helper_add64_ssov(CPUTriCoreState *env, uint64_t r1, uint64_t r2)
return result;
}
-target_ulong helper_add_h_ssov(CPUTriCoreState *env, target_ulong r1,
- target_ulong r2)
+uint32_t helper_add_h_ssov(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
{
int32_t ret_hw0, ret_hw1;
@@ -397,8 +395,7 @@ uint32_t helper_addsur_h_ssov(CPUTriCoreState *env, uint64_t r1, uint32_t r2_l,
}
-target_ulong helper_add_suov(CPUTriCoreState *env, target_ulong r1,
- target_ulong r2)
+uint32_t helper_add_suov(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
{
int64_t t1 = extract64(r1, 0, 32);
int64_t t2 = extract64(r2, 0, 32);
@@ -406,8 +403,7 @@ target_ulong helper_add_suov(CPUTriCoreState *env, target_ulong r1,
return suov32_pos(env, result);
}
-target_ulong helper_add_h_suov(CPUTriCoreState *env, target_ulong r1,
- target_ulong r2)
+uint32_t helper_add_h_suov(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
{
int32_t ret_hw0, ret_hw1;
@@ -416,8 +412,7 @@ target_ulong helper_add_h_suov(CPUTriCoreState *env, target_ulong r1,
return suov16(env, ret_hw0, ret_hw1);
}
-target_ulong helper_sub_ssov(CPUTriCoreState *env, target_ulong r1,
- target_ulong r2)
+uint32_t helper_sub_ssov(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
{
int64_t t1 = sextract64(r1, 0, 32);
int64_t t2 = sextract64(r2, 0, 32);
@@ -450,8 +445,7 @@ uint64_t helper_sub64_ssov(CPUTriCoreState *env, uint64_t r1, uint64_t r2)
return result;
}
-target_ulong helper_sub_h_ssov(CPUTriCoreState *env, target_ulong r1,
- target_ulong r2)
+uint32_t helper_sub_h_ssov(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
{
int32_t ret_hw0, ret_hw1;
@@ -552,8 +546,7 @@ uint32_t helper_subadr_h_ssov(CPUTriCoreState *env, uint64_t r1, uint32_t r2_l,
return (result1 & 0xffff0000ULL) | ((result0 >> 16) & 0xffffULL);
}
-target_ulong helper_sub_suov(CPUTriCoreState *env, target_ulong r1,
- target_ulong r2)
+uint32_t helper_sub_suov(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
{
int64_t t1 = extract64(r1, 0, 32);
int64_t t2 = extract64(r2, 0, 32);
@@ -561,8 +554,7 @@ target_ulong helper_sub_suov(CPUTriCoreState *env, target_ulong r1,
return suov32_neg(env, result);
}
-target_ulong helper_sub_h_suov(CPUTriCoreState *env, target_ulong r1,
- target_ulong r2)
+uint32_t helper_sub_h_suov(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
{
int32_t ret_hw0, ret_hw1;
@@ -571,8 +563,7 @@ target_ulong helper_sub_h_suov(CPUTriCoreState *env, target_ulong r1,
return suov16(env, ret_hw0, ret_hw1);
}
-target_ulong helper_mul_ssov(CPUTriCoreState *env, target_ulong r1,
- target_ulong r2)
+uint32_t helper_mul_ssov(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
{
int64_t t1 = sextract64(r1, 0, 32);
int64_t t2 = sextract64(r2, 0, 32);
@@ -580,8 +571,7 @@ target_ulong helper_mul_ssov(CPUTriCoreState *env, target_ulong r1,
return ssov32(env, result);
}
-target_ulong helper_mul_suov(CPUTriCoreState *env, target_ulong r1,
- target_ulong r2)
+uint32_t helper_mul_suov(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
{
int64_t t1 = extract64(r1, 0, 32);
int64_t t2 = extract64(r2, 0, 32);
@@ -590,8 +580,7 @@ target_ulong helper_mul_suov(CPUTriCoreState *env, target_ulong r1,
return suov32_pos(env, result);
}
-target_ulong helper_sha_ssov(CPUTriCoreState *env, target_ulong r1,
- target_ulong r2)
+uint32_t helper_sha_ssov(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
{
int64_t t1 = sextract64(r1, 0, 32);
int32_t t2 = sextract64(r2, 0, 6);
@@ -606,14 +595,14 @@ target_ulong helper_sha_ssov(CPUTriCoreState *env, target_ulong r1,
return ssov32(env, result);
}
-uint32_t helper_abs_ssov(CPUTriCoreState *env, target_ulong r1)
+uint32_t helper_abs_ssov(CPUTriCoreState *env, uint32_t r1)
{
- target_ulong result;
+ uint32_t result;
result = ((int32_t)r1 >= 0) ? r1 : (0 - r1);
return ssov32(env, result);
}
-uint32_t helper_abs_h_ssov(CPUTriCoreState *env, target_ulong r1)
+uint32_t helper_abs_h_ssov(CPUTriCoreState *env, uint32_t r1)
{
int32_t ret_h0, ret_h1;
@@ -626,8 +615,7 @@ uint32_t helper_abs_h_ssov(CPUTriCoreState *env, target_ulong r1)
return ssov16(env, ret_h0, ret_h1);
}
-target_ulong helper_absdif_ssov(CPUTriCoreState *env, target_ulong r1,
- target_ulong r2)
+uint32_t helper_absdif_ssov(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
{
int64_t t1 = sextract64(r1, 0, 32);
int64_t t2 = sextract64(r2, 0, 32);
@@ -641,8 +629,7 @@ target_ulong helper_absdif_ssov(CPUTriCoreState *env, target_ulong r1,
return ssov32(env, result);
}
-uint32_t helper_absdif_h_ssov(CPUTriCoreState *env, target_ulong r1,
- target_ulong r2)
+uint32_t helper_absdif_h_ssov(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
{
int32_t t1, t2;
int32_t ret_h0, ret_h1;
@@ -666,8 +653,8 @@ uint32_t helper_absdif_h_ssov(CPUTriCoreState *env, target_ulong r1,
return ssov16(env, ret_h0, ret_h1);
}
-target_ulong helper_madd32_ssov(CPUTriCoreState *env, target_ulong r1,
- target_ulong r2, target_ulong r3)
+uint32_t helper_madd32_ssov(CPUTriCoreState *env, uint32_t r1,
+ uint32_t r2, uint32_t r3)
{
int64_t t1 = sextract64(r1, 0, 32);
int64_t t2 = sextract64(r2, 0, 32);
@@ -678,8 +665,8 @@ target_ulong helper_madd32_ssov(CPUTriCoreState *env, target_ulong r1,
return ssov32(env, result);
}
-target_ulong helper_madd32_suov(CPUTriCoreState *env, target_ulong r1,
- target_ulong r2, target_ulong r3)
+uint32_t helper_madd32_suov(CPUTriCoreState *env, uint32_t r1,
+ uint32_t r2, uint32_t r3)
{
uint64_t t1 = extract64(r1, 0, 32);
uint64_t t2 = extract64(r2, 0, 32);
@@ -690,8 +677,8 @@ target_ulong helper_madd32_suov(CPUTriCoreState *env, target_ulong r1,
return suov32_pos(env, result);
}
-uint64_t helper_madd64_ssov(CPUTriCoreState *env, target_ulong r1,
- uint64_t r2, target_ulong r3)
+uint64_t helper_madd64_ssov(CPUTriCoreState *env, uint32_t r1,
+ uint64_t r2, uint32_t r3)
{
uint64_t ret, ovf;
int64_t t1 = sextract64(r1, 0, 32);
@@ -848,8 +835,8 @@ uint32_t helper_maddr_q_ssov(CPUTriCoreState *env, uint32_t r1, uint32_t r2,
return ret & 0xffff0000ll;
}
-uint64_t helper_madd64_suov(CPUTriCoreState *env, target_ulong r1,
- uint64_t r2, target_ulong r3)
+uint64_t helper_madd64_suov(CPUTriCoreState *env, uint32_t r1,
+ uint64_t r2, uint32_t r3)
{
uint64_t ret, mul;
uint64_t t1 = extract64(r1, 0, 32);
@@ -873,8 +860,8 @@ uint64_t helper_madd64_suov(CPUTriCoreState *env, target_ulong r1,
return ret;
}
-target_ulong helper_msub32_ssov(CPUTriCoreState *env, target_ulong r1,
- target_ulong r2, target_ulong r3)
+uint32_t helper_msub32_ssov(CPUTriCoreState *env, uint32_t r1,
+ uint32_t r2, uint32_t r3)
{
int64_t t1 = sextract64(r1, 0, 32);
int64_t t2 = sextract64(r2, 0, 32);
@@ -885,8 +872,8 @@ target_ulong helper_msub32_ssov(CPUTriCoreState *env, target_ulong r1,
return ssov32(env, result);
}
-target_ulong helper_msub32_suov(CPUTriCoreState *env, target_ulong r1,
- target_ulong r2, target_ulong r3)
+uint32_t helper_msub32_suov(CPUTriCoreState *env, uint32_t r1,
+ uint32_t r2, uint32_t r3)
{
uint64_t t1 = extract64(r1, 0, 32);
uint64_t t2 = extract64(r2, 0, 32);
@@ -912,8 +899,8 @@ target_ulong helper_msub32_suov(CPUTriCoreState *env, target_ulong r1,
return result;
}
-uint64_t helper_msub64_ssov(CPUTriCoreState *env, target_ulong r1,
- uint64_t r2, target_ulong r3)
+uint64_t helper_msub64_ssov(CPUTriCoreState *env, uint32_t r1,
+ uint64_t r2, uint32_t r3)
{
uint64_t ret, ovf;
int64_t t1 = sextract64(r1, 0, 32);
@@ -944,8 +931,8 @@ uint64_t helper_msub64_ssov(CPUTriCoreState *env, target_ulong r1,
return ret;
}
-uint64_t helper_msub64_suov(CPUTriCoreState *env, target_ulong r1,
- uint64_t r2, target_ulong r3)
+uint64_t helper_msub64_suov(CPUTriCoreState *env, uint32_t r1,
+ uint64_t r2, uint32_t r3)
{
uint64_t ret, mul;
uint64_t t1 = extract64(r1, 0, 32);
@@ -1097,7 +1084,7 @@ uint32_t helper_msubr_q_ssov(CPUTriCoreState *env, uint32_t r1, uint32_t r2,
return ret & 0xffff0000ll;
}
-uint32_t helper_abs_b(CPUTriCoreState *env, target_ulong arg)
+uint32_t helper_abs_b(CPUTriCoreState *env, uint32_t arg)
{
int32_t b, i;
int32_t ovf = 0;
@@ -1120,7 +1107,7 @@ uint32_t helper_abs_b(CPUTriCoreState *env, target_ulong arg)
return ret;
}
-uint32_t helper_abs_h(CPUTriCoreState *env, target_ulong arg)
+uint32_t helper_abs_h(CPUTriCoreState *env, uint32_t arg)
{
int32_t h, i;
int32_t ovf = 0;
@@ -1143,7 +1130,7 @@ uint32_t helper_abs_h(CPUTriCoreState *env, target_ulong arg)
return ret;
}
-uint32_t helper_absdif_b(CPUTriCoreState *env, target_ulong r1, target_ulong r2)
+uint32_t helper_absdif_b(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
{
int32_t b, i;
int32_t extr_r2;
@@ -1167,7 +1154,7 @@ uint32_t helper_absdif_b(CPUTriCoreState *env, target_ulong r1, target_ulong r2)
return ret;
}
-uint32_t helper_absdif_h(CPUTriCoreState *env, target_ulong r1, target_ulong r2)
+uint32_t helper_absdif_h(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
{
int32_t h, i;
int32_t extr_r2;
@@ -1296,7 +1283,7 @@ uint32_t helper_maddr_q(CPUTriCoreState *env, uint32_t r1, uint32_t r2,
return ret & 0xffff0000ll;
}
-uint32_t helper_add_b(CPUTriCoreState *env, target_ulong r1, target_ulong r2)
+uint32_t helper_add_b(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
{
int32_t b, i;
int32_t extr_r1, extr_r2;
@@ -1322,7 +1309,7 @@ uint32_t helper_add_b(CPUTriCoreState *env, target_ulong r1, target_ulong r2)
return ret;
}
-uint32_t helper_add_h(CPUTriCoreState *env, target_ulong r1, target_ulong r2)
+uint32_t helper_add_h(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
{
int32_t h, i;
int32_t extr_r1, extr_r2;
@@ -1451,7 +1438,7 @@ uint32_t helper_msubr_q(CPUTriCoreState *env, uint32_t r1, uint32_t r2,
return ret & 0xffff0000ll;
}
-uint32_t helper_sub_b(CPUTriCoreState *env, target_ulong r1, target_ulong r2)
+uint32_t helper_sub_b(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
{
int32_t b, i;
int32_t extr_r1, extr_r2;
@@ -1477,7 +1464,7 @@ uint32_t helper_sub_b(CPUTriCoreState *env, target_ulong r1, target_ulong r2)
return ret;
}
-uint32_t helper_sub_h(CPUTriCoreState *env, target_ulong r1, target_ulong r2)
+uint32_t helper_sub_h(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
{
int32_t h, i;
int32_t extr_r1, extr_r2;
@@ -1502,7 +1489,7 @@ uint32_t helper_sub_h(CPUTriCoreState *env, target_ulong r1, target_ulong r2)
return ret;
}
-uint32_t helper_eq_b(target_ulong r1, target_ulong r2)
+uint32_t helper_eq_b(uint32_t r1, uint32_t r2)
{
uint32_t ret, msk;
int32_t i;
@@ -1519,7 +1506,7 @@ uint32_t helper_eq_b(target_ulong r1, target_ulong r2)
return ret;
}
-uint32_t helper_eq_h(target_ulong r1, target_ulong r2)
+uint32_t helper_eq_h(uint32_t r1, uint32_t r2)
{
int32_t ret = 0;
@@ -1534,7 +1521,7 @@ uint32_t helper_eq_h(target_ulong r1, target_ulong r2)
return ret;
}
-uint32_t helper_eqany_b(target_ulong r1, target_ulong r2)
+uint32_t helper_eqany_b(uint32_t r1, uint32_t r2)
{
int32_t i;
uint32_t ret = 0;
@@ -1546,7 +1533,7 @@ uint32_t helper_eqany_b(target_ulong r1, target_ulong r2)
return ret;
}
-uint32_t helper_eqany_h(target_ulong r1, target_ulong r2)
+uint32_t helper_eqany_h(uint32_t r1, uint32_t r2)
{
uint32_t ret;
@@ -1556,7 +1543,7 @@ uint32_t helper_eqany_h(target_ulong r1, target_ulong r2)
return ret;
}
-uint32_t helper_lt_b(target_ulong r1, target_ulong r2)
+uint32_t helper_lt_b(uint32_t r1, uint32_t r2)
{
int32_t i;
uint32_t ret = 0;
@@ -1570,7 +1557,7 @@ uint32_t helper_lt_b(target_ulong r1, target_ulong r2)
return ret;
}
-uint32_t helper_lt_bu(target_ulong r1, target_ulong r2)
+uint32_t helper_lt_bu(uint32_t r1, uint32_t r2)
{
int32_t i;
uint32_t ret = 0;
@@ -1584,7 +1571,7 @@ uint32_t helper_lt_bu(target_ulong r1, target_ulong r2)
return ret;
}
-uint32_t helper_lt_h(target_ulong r1, target_ulong r2)
+uint32_t helper_lt_h(uint32_t r1, uint32_t r2)
{
uint32_t ret = 0;
@@ -1599,7 +1586,7 @@ uint32_t helper_lt_h(target_ulong r1, target_ulong r2)
return ret;
}
-uint32_t helper_lt_hu(target_ulong r1, target_ulong r2)
+uint32_t helper_lt_hu(uint32_t r1, uint32_t r2)
{
uint32_t ret = 0;
@@ -1615,7 +1602,7 @@ uint32_t helper_lt_hu(target_ulong r1, target_ulong r2)
}
#define EXTREMA_H_B(name, op) \
-uint32_t helper_##name ##_b(target_ulong r1, target_ulong r2) \
+uint32_t helper_##name ##_b(uint32_t r1, uint32_t r2) \
{ \
int32_t i, extr_r1, extr_r2; \
uint32_t ret = 0; \
@@ -1629,7 +1616,7 @@ uint32_t helper_##name ##_b(target_ulong r1, target_ulong r2) \
return ret; \
} \
\
-uint32_t helper_##name ##_bu(target_ulong r1, target_ulong r2)\
+uint32_t helper_##name ##_bu(uint32_t r1, uint32_t r2) \
{ \
int32_t i; \
uint32_t extr_r1, extr_r2; \
@@ -1644,7 +1631,7 @@ uint32_t helper_##name ##_bu(target_ulong r1, target_ulong r2)\
return ret; \
} \
\
-uint32_t helper_##name ##_h(target_ulong r1, target_ulong r2) \
+uint32_t helper_##name ##_h(uint32_t r1, uint32_t r2) \
{ \
int32_t extr_r1, extr_r2; \
uint32_t ret = 0; \
@@ -1662,7 +1649,7 @@ uint32_t helper_##name ##_h(target_ulong r1, target_ulong r2) \
return ret; \
} \
\
-uint32_t helper_##name ##_hu(target_ulong r1, target_ulong r2)\
+uint32_t helper_##name ##_hu(uint32_t r1, uint32_t r2) \
{ \
uint32_t extr_r1, extr_r2; \
uint32_t ret = 0; \
@@ -1729,7 +1716,7 @@ EXTREMA_H_B(min, <)
#undef EXTREMA_H_B
-uint32_t helper_clo_h(target_ulong r1)
+uint32_t helper_clo_h(uint32_t r1)
{
uint32_t ret_hw0 = extract32(r1, 0, 16);
uint32_t ret_hw1 = extract32(r1, 16, 16);
@@ -1747,7 +1734,7 @@ uint32_t helper_clo_h(target_ulong r1)
return ret_hw0 | (ret_hw1 << 16);
}
-uint32_t helper_clz_h(target_ulong r1)
+uint32_t helper_clz_h(uint32_t r1)
{
uint32_t ret_hw0 = extract32(r1, 0, 16);
uint32_t ret_hw1 = extract32(r1, 16, 16);
@@ -1765,7 +1752,7 @@ uint32_t helper_clz_h(target_ulong r1)
return ret_hw0 | (ret_hw1 << 16);
}
-uint32_t helper_cls_h(target_ulong r1)
+uint32_t helper_cls_h(uint32_t r1)
{
uint32_t ret_hw0 = extract32(r1, 0, 16);
uint32_t ret_hw1 = extract32(r1, 16, 16);
@@ -1783,7 +1770,7 @@ uint32_t helper_cls_h(target_ulong r1)
return ret_hw0 | (ret_hw1 << 16);
}
-uint32_t helper_sh(target_ulong r1, target_ulong r2)
+uint32_t helper_sh(uint32_t r1, uint32_t r2)
{
int32_t shift_count = sextract32(r2, 0, 6);
@@ -1796,7 +1783,7 @@ uint32_t helper_sh(target_ulong r1, target_ulong r2)
}
}
-uint32_t helper_sh_h(target_ulong r1, target_ulong r2)
+uint32_t helper_sh_h(uint32_t r1, uint32_t r2)
{
int32_t ret_hw0, ret_hw1;
int32_t shift_count;
@@ -1816,7 +1803,7 @@ uint32_t helper_sh_h(target_ulong r1, target_ulong r2)
}
}
-uint32_t helper_sha(CPUTriCoreState *env, target_ulong r1, target_ulong r2)
+uint32_t helper_sha(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
{
int32_t shift_count;
int64_t result, t1;
@@ -1854,7 +1841,7 @@ uint32_t helper_sha(CPUTriCoreState *env, target_ulong r1, target_ulong r2)
return ret;
}
-uint32_t helper_sha_h(target_ulong r1, target_ulong r2)
+uint32_t helper_sha_h(uint32_t r1, uint32_t r2)
{
int32_t shift_count;
int32_t ret_hw0, ret_hw1;
@@ -1874,7 +1861,7 @@ uint32_t helper_sha_h(target_ulong r1, target_ulong r2)
}
}
-uint32_t helper_bmerge(target_ulong r1, target_ulong r2)
+uint32_t helper_bmerge(uint32_t r1, uint32_t r2)
{
uint32_t i, ret;
@@ -1905,7 +1892,7 @@ uint64_t helper_bsplit(uint32_t r1)
return ret;
}
-uint32_t helper_parity(target_ulong r1)
+uint32_t helper_parity(uint32_t r1)
{
uint32_t ret;
uint32_t nOnes, i;
@@ -1942,7 +1929,7 @@ uint32_t helper_parity(target_ulong r1)
}
uint32_t helper_pack(uint32_t carry, uint32_t r1_low, uint32_t r1_high,
- target_ulong r2)
+ uint32_t r2)
{
uint32_t ret;
int32_t fp_exp, fp_frac, temp_exp, fp_exp_frac;
@@ -1983,7 +1970,7 @@ uint32_t helper_pack(uint32_t carry, uint32_t r1_low, uint32_t r1_high,
return ret;
}
-uint64_t helper_unpack(target_ulong arg1)
+uint64_t helper_unpack(uint32_t arg1)
{
int32_t fp_exp = extract32(arg1, 23, 8);
int32_t fp_frac = extract32(arg1, 0, 23);
@@ -2408,7 +2395,7 @@ uint32_t helper_shuffle(uint32_t arg0, uint32_t arg1)
/* context save area (CSA) related helpers */
-static int cdc_increment(target_ulong *psw)
+static int cdc_increment(uint32_t *psw)
{
if ((*psw & MASK_PSW_CDC) == 0x7f) {
return 0;
@@ -2426,7 +2413,7 @@ static int cdc_increment(target_ulong *psw)
return 0;
}
-static int cdc_decrement(target_ulong *psw)
+static int cdc_decrement(uint32_t *psw)
{
if ((*psw & MASK_PSW_CDC) == 0x7f) {
return 0;
@@ -2442,7 +2429,7 @@ static int cdc_decrement(target_ulong *psw)
return 0;
}
-static bool cdc_zero(target_ulong *psw)
+static bool cdc_zero(uint32_t *psw)
{
int cdc = *psw & MASK_PSW_CDC;
/* Returns TRUE if PSW.CDC.COUNT == 0 or if PSW.CDC ==
@@ -2457,7 +2444,7 @@ static bool cdc_zero(target_ulong *psw)
return count == 0;
}
-static void save_context_upper(CPUTriCoreState *env, target_ulong ea)
+static void save_context_upper(CPUTriCoreState *env, uint32_t ea)
{
cpu_stl_data(env, ea, env->PCXI);
cpu_stl_data(env, ea+4, psw_read(env));
@@ -2477,7 +2464,7 @@ static void save_context_upper(CPUTriCoreState *env, target_ulong ea)
cpu_stl_data(env, ea+60, env->gpr_d[15]);
}
-static void save_context_lower(CPUTriCoreState *env, target_ulong ea)
+static void save_context_lower(CPUTriCoreState *env, uint32_t ea)
{
cpu_stl_data(env, ea, env->PCXI);
cpu_stl_data(env, ea+4, env->gpr_a[11]);
@@ -2497,8 +2484,8 @@ static void save_context_lower(CPUTriCoreState *env, target_ulong ea)
cpu_stl_data(env, ea+60, env->gpr_d[7]);
}
-static void restore_context_upper(CPUTriCoreState *env, target_ulong ea,
- target_ulong *new_PCXI, target_ulong *new_PSW)
+static void restore_context_upper(CPUTriCoreState *env, uint32_t ea,
+ uint32_t *new_PCXI, uint32_t *new_PSW)
{
*new_PCXI = cpu_ldl_data(env, ea);
*new_PSW = cpu_ldl_data(env, ea+4);
@@ -2518,8 +2505,8 @@ static void restore_context_upper(CPUTriCoreState *env, target_ulong ea,
env->gpr_d[15] = cpu_ldl_data(env, ea+60);
}
-static void restore_context_lower(CPUTriCoreState *env, target_ulong ea,
- target_ulong *ra, target_ulong *pcxi)
+static void restore_context_lower(CPUTriCoreState *env, uint32_t ea,
+ uint32_t *ra, uint32_t *pcxi)
{
*pcxi = cpu_ldl_data(env, ea);
*ra = cpu_ldl_data(env, ea+4);
@@ -2541,10 +2528,10 @@ static void restore_context_lower(CPUTriCoreState *env, target_ulong ea,
void helper_call(CPUTriCoreState *env, uint32_t next_pc)
{
- target_ulong tmp_FCX;
- target_ulong ea;
- target_ulong new_FCX;
- target_ulong psw;
+ uint32_t tmp_FCX;
+ uint32_t ea;
+ uint32_t new_FCX;
+ uint32_t psw;
psw = psw_read(env);
/* if (FCX == 0) trap(FCU); */
@@ -2604,9 +2591,9 @@ void helper_call(CPUTriCoreState *env, uint32_t next_pc)
void helper_ret(CPUTriCoreState *env)
{
- target_ulong ea;
- target_ulong new_PCXI;
- target_ulong new_PSW, psw;
+ uint32_t ea;
+ uint32_t new_PCXI;
+ uint32_t new_PSW, psw;
psw = psw_read(env);
/* if (PSW.CDE) then if (cdc_decrement()) then trap(CDU);*/
@@ -2657,9 +2644,9 @@ void helper_ret(CPUTriCoreState *env)
void helper_bisr(CPUTriCoreState *env, uint32_t const9)
{
- target_ulong tmp_FCX;
- target_ulong ea;
- target_ulong new_FCX;
+ uint32_t tmp_FCX;
+ uint32_t ea;
+ uint32_t new_FCX;
if (env->FCX == 0) {
/* FCU trap */
@@ -2701,9 +2688,9 @@ void helper_bisr(CPUTriCoreState *env, uint32_t const9)
void helper_rfe(CPUTriCoreState *env)
{
- target_ulong ea;
- target_ulong new_PCXI;
- target_ulong new_PSW;
+ uint32_t ea;
+ uint32_t new_PCXI;
+ uint32_t new_PSW;
/* if (PCXI[19: 0] == 0) then trap(CSU); */
if ((env->PCXI & 0xfffff) == 0) {
/* raise csu trap */
@@ -2762,35 +2749,35 @@ void helper_rfm(CPUTriCoreState *env)
}
}
-void helper_ldlcx(CPUTriCoreState *env, target_ulong ea)
+void helper_ldlcx(CPUTriCoreState *env, uint32_t ea)
{
uint32_t dummy;
/* insn doesn't load PCXI and RA */
restore_context_lower(env, ea, &dummy, &dummy);
}
-void helper_lducx(CPUTriCoreState *env, target_ulong ea)
+void helper_lducx(CPUTriCoreState *env, uint32_t ea)
{
uint32_t dummy;
/* insn doesn't load PCXI and PSW */
restore_context_upper(env, ea, &dummy, &dummy);
}
-void helper_stlcx(CPUTriCoreState *env, target_ulong ea)
+void helper_stlcx(CPUTriCoreState *env, uint32_t ea)
{
save_context_lower(env, ea);
}
-void helper_stucx(CPUTriCoreState *env, target_ulong ea)
+void helper_stucx(CPUTriCoreState *env, uint32_t ea)
{
save_context_upper(env, ea);
}
void helper_svlcx(CPUTriCoreState *env)
{
- target_ulong tmp_FCX;
- target_ulong ea;
- target_ulong new_FCX;
+ uint32_t tmp_FCX;
+ uint32_t ea;
+ uint32_t new_FCX;
if (env->FCX == 0) {
/* FCU trap */
@@ -2831,9 +2818,9 @@ void helper_svlcx(CPUTriCoreState *env)
void helper_svucx(CPUTriCoreState *env)
{
- target_ulong tmp_FCX;
- target_ulong ea;
- target_ulong new_FCX;
+ uint32_t tmp_FCX;
+ uint32_t ea;
+ uint32_t new_FCX;
if (env->FCX == 0) {
/* FCU trap */
@@ -2874,8 +2861,8 @@ void helper_svucx(CPUTriCoreState *env)
void helper_rslcx(CPUTriCoreState *env)
{
- target_ulong ea;
- target_ulong new_PCXI;
+ uint32_t ea;
+ uint32_t new_PCXI;
/* if (PCXI[19: 0] == 0) then trap(CSU); */
if ((env->PCXI & 0xfffff) == 0) {
/* CSU trap */
--
2.51.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 07/12] target/tricore: Declare registers as TCGv_i32
2025-10-10 5:21 [PATCH 00/12] target/tricore: Remove all uses of target_ulong types Philippe Mathieu-Daudé
` (5 preceding siblings ...)
2025-10-10 5:21 ` [PATCH 06/12] target/tricore: Replace target_ulong -> uint32_t in op_helper.c Philippe Mathieu-Daudé
@ 2025-10-10 5:21 ` Philippe Mathieu-Daudé
2025-10-10 17:04 ` Richard Henderson
2025-10-10 5:21 ` [PATCH 08/12] target/tricore: Inline tcg_gen_ld32u_tl() Philippe Mathieu-Daudé
` (4 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-10 5:21 UTC (permalink / raw)
To: qemu-devel
Cc: Bastian Koppelmann, Pierrick Bouvier, Anton Johansson,
Philippe Mathieu-Daudé
CPUTriCoreState register are declared as uint32_t since the
target introduction in commit 48e06fe0ed8 ("target-tricore:
Add target stubs and qom-cpu").
Mechanical replacement of:
TCGv -> TCGv_i32
tcg_temp_new -> tcg_temp_new_i32
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/tricore/translate.c | 80 +++++++++++++++++++-------------------
1 file changed, 40 insertions(+), 40 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 116f45135bb..194c4db8d0f 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -44,19 +44,19 @@
/*
* TCG registers
*/
-static TCGv cpu_PC;
-static TCGv cpu_PCXI;
-static TCGv cpu_PSW;
-static TCGv cpu_ICR;
+static TCGv_i32 cpu_PC;
+static TCGv_i32 cpu_PCXI;
+static TCGv_i32 cpu_PSW;
+static TCGv_i32 cpu_ICR;
/* GPR registers */
-static TCGv cpu_gpr_a[16];
-static TCGv cpu_gpr_d[16];
+static TCGv_i32 cpu_gpr_a[16];
+static TCGv_i32 cpu_gpr_d[16];
/* PSW Flag cache */
-static TCGv cpu_PSW_C;
-static TCGv cpu_PSW_V;
-static TCGv cpu_PSW_SV;
-static TCGv cpu_PSW_AV;
-static TCGv cpu_PSW_SAV;
+static TCGv_i32 cpu_PSW_C;
+static TCGv_i32 cpu_PSW_V;
+static TCGv_i32 cpu_PSW_SV;
+static TCGv_i32 cpu_PSW_AV;
+static TCGv_i32 cpu_PSW_SAV;
static const char *regnames_a[] = {
"a0" , "a1" , "a2" , "a3" , "a4" , "a5" ,
@@ -8480,14 +8480,14 @@ void cpu_state_reset(CPUTriCoreState *env)
static void tricore_tcg_init_csfr(void)
{
- cpu_PCXI = tcg_global_mem_new(tcg_env,
- offsetof(CPUTriCoreState, PCXI), "PCXI");
- cpu_PSW = tcg_global_mem_new(tcg_env,
- offsetof(CPUTriCoreState, PSW), "PSW");
- cpu_PC = tcg_global_mem_new(tcg_env,
- offsetof(CPUTriCoreState, PC), "PC");
- cpu_ICR = tcg_global_mem_new(tcg_env,
- offsetof(CPUTriCoreState, ICR), "ICR");
+ cpu_PCXI = tcg_global_mem_new_i32(tcg_env,
+ offsetof(CPUTriCoreState, PCXI), "PCXI");
+ cpu_PSW = tcg_global_mem_new_i32(tcg_env,
+ offsetof(CPUTriCoreState, PSW), "PSW");
+ cpu_PC = tcg_global_mem_new_i32(tcg_env,
+ offsetof(CPUTriCoreState, PC), "PC");
+ cpu_ICR = tcg_global_mem_new_i32(tcg_env,
+ offsetof(CPUTriCoreState, ICR), "ICR");
}
void tricore_tcg_init(void)
@@ -8496,30 +8496,30 @@ void tricore_tcg_init(void)
/* reg init */
for (i = 0 ; i < 16 ; i++) {
- cpu_gpr_a[i] = tcg_global_mem_new(tcg_env,
- offsetof(CPUTriCoreState, gpr_a[i]),
- regnames_a[i]);
+ cpu_gpr_a[i] = tcg_global_mem_new_i32(tcg_env,
+ offsetof(CPUTriCoreState, gpr_a[i]),
+ regnames_a[i]);
}
for (i = 0 ; i < 16 ; i++) {
- cpu_gpr_d[i] = tcg_global_mem_new(tcg_env,
- offsetof(CPUTriCoreState, gpr_d[i]),
- regnames_d[i]);
+ cpu_gpr_d[i] = tcg_global_mem_new_i32(tcg_env,
+ offsetof(CPUTriCoreState, gpr_d[i]),
+ regnames_d[i]);
}
tricore_tcg_init_csfr();
/* init PSW flag cache */
- cpu_PSW_C = tcg_global_mem_new(tcg_env,
- offsetof(CPUTriCoreState, PSW_USB_C),
- "PSW_C");
- cpu_PSW_V = tcg_global_mem_new(tcg_env,
- offsetof(CPUTriCoreState, PSW_USB_V),
- "PSW_V");
- cpu_PSW_SV = tcg_global_mem_new(tcg_env,
- offsetof(CPUTriCoreState, PSW_USB_SV),
- "PSW_SV");
- cpu_PSW_AV = tcg_global_mem_new(tcg_env,
- offsetof(CPUTriCoreState, PSW_USB_AV),
- "PSW_AV");
- cpu_PSW_SAV = tcg_global_mem_new(tcg_env,
- offsetof(CPUTriCoreState, PSW_USB_SAV),
- "PSW_SAV");
+ cpu_PSW_C = tcg_global_mem_new_i32(tcg_env,
+ offsetof(CPUTriCoreState, PSW_USB_C),
+ "PSW_C");
+ cpu_PSW_V = tcg_global_mem_new_i32(tcg_env,
+ offsetof(CPUTriCoreState, PSW_USB_V),
+ "PSW_V");
+ cpu_PSW_SV = tcg_global_mem_new_i32(tcg_env,
+ offsetof(CPUTriCoreState, PSW_USB_SV),
+ "PSW_SV");
+ cpu_PSW_AV = tcg_global_mem_new_i32(tcg_env,
+ offsetof(CPUTriCoreState, PSW_USB_AV),
+ "PSW_AV");
+ cpu_PSW_SAV = tcg_global_mem_new_i32(tcg_env,
+ offsetof(CPUTriCoreState, PSW_USB_SAV),
+ "PSW_SAV");
}
--
2.51.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 08/12] target/tricore: Inline tcg_gen_ld32u_tl()
2025-10-10 5:21 [PATCH 00/12] target/tricore: Remove all uses of target_ulong types Philippe Mathieu-Daudé
` (6 preceding siblings ...)
2025-10-10 5:21 ` [PATCH 07/12] target/tricore: Declare registers as TCGv_i32 Philippe Mathieu-Daudé
@ 2025-10-10 5:21 ` Philippe Mathieu-Daudé
2025-10-10 17:05 ` Richard Henderson
2025-10-10 5:21 ` [PATCH 09/12] target/tricore: Expand TCG helpers for 32-bit target Philippe Mathieu-Daudé
` (3 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-10 5:21 UTC (permalink / raw)
To: qemu-devel
Cc: Bastian Koppelmann, Pierrick Bouvier, Anton Johansson,
Philippe Mathieu-Daudé
The TriCore target is only built as 32-bit, so tcg_gen_ld32u_tl()
expands to tcg_gen_ld_i32(). Use the latter to simplify the next
commit mechanical change.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/tricore/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 194c4db8d0f..da08f7bd60a 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -7959,7 +7959,7 @@ static void decode_sys_interrupts(DisasContext *ctx)
tmp = tcg_temp_new();
l1 = gen_new_label();
- tcg_gen_ld32u_tl(tmp, tcg_env, offsetof(CPUTriCoreState, DBGSR));
+ tcg_gen_ld_i32(tmp, tcg_env, offsetof(CPUTriCoreState, DBGSR));
tcg_gen_andi_tl(tmp, tmp, MASK_DBGSR_DE);
tcg_gen_brcondi_tl(TCG_COND_NE, tmp, 1, l1);
gen_helper_rfm(tcg_env);
--
2.51.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 09/12] target/tricore: Expand TCG helpers for 32-bit target
2025-10-10 5:21 [PATCH 00/12] target/tricore: Remove all uses of target_ulong types Philippe Mathieu-Daudé
` (7 preceding siblings ...)
2025-10-10 5:21 ` [PATCH 08/12] target/tricore: Inline tcg_gen_ld32u_tl() Philippe Mathieu-Daudé
@ 2025-10-10 5:21 ` Philippe Mathieu-Daudé
2025-10-10 17:06 ` Richard Henderson
2025-10-10 5:21 ` [PATCH 10/12] target/tricore: Pass DisasContext as first argument Philippe Mathieu-Daudé
` (2 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-10 5:21 UTC (permalink / raw)
To: qemu-devel
Cc: Bastian Koppelmann, Pierrick Bouvier, Anton Johansson,
Philippe Mathieu-Daudé
The TriCore target is only built as 32-bit:
$ git grep TARGET_LONG_BITS configs/targets/tricore-*
configs/targets/tricore-softmmu.mak:2:TARGET_LONG_BITS=32
Therefore tcg_FOO_tl() always expands to tcg_FOO_i32().
This is a mechanical replacement.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/tricore/translate.c | 2595 ++++++++++++++++++------------------
1 file changed, 1298 insertions(+), 1297 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index da08f7bd60a..ce4e3f6202e 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -139,9 +139,9 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f, int flags)
TCGv arg00 = tcg_temp_new(); \
TCGv arg01 = tcg_temp_new(); \
TCGv arg11 = tcg_temp_new(); \
- tcg_gen_sari_tl(arg00, arg0, 16); \
- tcg_gen_ext16s_tl(arg01, arg0); \
- tcg_gen_ext16s_tl(arg11, arg1); \
+ tcg_gen_sari_i32(arg00, arg0, 16); \
+ tcg_gen_ext16s_i32(arg01, arg0); \
+ tcg_gen_ext16s_i32(arg11, arg1); \
gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \
} while (0)
@@ -150,10 +150,10 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f, int flags)
TCGv arg01 = tcg_temp_new(); \
TCGv arg10 = tcg_temp_new(); \
TCGv arg11 = tcg_temp_new(); \
- tcg_gen_sari_tl(arg00, arg0, 16); \
- tcg_gen_ext16s_tl(arg01, arg0); \
- tcg_gen_sari_tl(arg11, arg1, 16); \
- tcg_gen_ext16s_tl(arg10, arg1); \
+ tcg_gen_sari_i32(arg00, arg0, 16); \
+ tcg_gen_ext16s_i32(arg01, arg0); \
+ tcg_gen_sari_i32(arg11, arg1, 16); \
+ tcg_gen_ext16s_i32(arg10, arg1); \
gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \
} while (0)
@@ -162,10 +162,10 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f, int flags)
TCGv arg01 = tcg_temp_new(); \
TCGv arg10 = tcg_temp_new(); \
TCGv arg11 = tcg_temp_new(); \
- tcg_gen_sari_tl(arg00, arg0, 16); \
- tcg_gen_ext16s_tl(arg01, arg0); \
- tcg_gen_sari_tl(arg10, arg1, 16); \
- tcg_gen_ext16s_tl(arg11, arg1); \
+ tcg_gen_sari_i32(arg00, arg0, 16); \
+ tcg_gen_ext16s_i32(arg01, arg0); \
+ tcg_gen_sari_i32(arg10, arg1, 16); \
+ tcg_gen_ext16s_i32(arg11, arg1); \
gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \
} while (0)
@@ -173,9 +173,9 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f, int flags)
TCGv arg00 = tcg_temp_new(); \
TCGv arg01 = tcg_temp_new(); \
TCGv arg11 = tcg_temp_new(); \
- tcg_gen_sari_tl(arg01, arg0, 16); \
- tcg_gen_ext16s_tl(arg00, arg0); \
- tcg_gen_sari_tl(arg11, arg1, 16); \
+ tcg_gen_sari_i32(arg01, arg0, 16); \
+ tcg_gen_ext16s_i32(arg00, arg0); \
+ tcg_gen_sari_i32(arg11, arg1, 16); \
gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \
} while (0)
@@ -214,16 +214,16 @@ static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2,
int16_t con, MemOp mop)
{
TCGv temp = tcg_temp_new();
- tcg_gen_addi_tl(temp, r2, con);
- tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop);
+ tcg_gen_addi_i32(temp, r2, con);
+ tcg_gen_qemu_ld_i32(r1, temp, ctx->mem_idx, mop);
}
static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2,
int16_t con, MemOp mop)
{
TCGv temp = tcg_temp_new();
- tcg_gen_addi_tl(temp, r2, con);
- tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop);
+ tcg_gen_addi_i32(temp, r2, con);
+ tcg_gen_qemu_st_i32(r1, temp, ctx->mem_idx, mop);
}
static void gen_st_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx)
@@ -238,7 +238,7 @@ static void gen_offset_st_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con,
DisasContext *ctx)
{
TCGv temp = tcg_temp_new();
- tcg_gen_addi_tl(temp, base, con);
+ tcg_gen_addi_i32(temp, base, con);
gen_st_2regs_64(rh, rl, temp, ctx);
}
@@ -255,7 +255,7 @@ static void gen_offset_ld_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con,
DisasContext *ctx)
{
TCGv temp = tcg_temp_new();
- tcg_gen_addi_tl(temp, base, con);
+ tcg_gen_addi_i32(temp, base, con);
gen_ld_2regs_64(rh, rl, temp, ctx);
}
@@ -263,18 +263,18 @@ static void gen_st_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,
MemOp mop)
{
TCGv temp = tcg_temp_new();
- tcg_gen_addi_tl(temp, r2, off);
- tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop);
- tcg_gen_mov_tl(r2, temp);
+ tcg_gen_addi_i32(temp, r2, off);
+ tcg_gen_qemu_st_i32(r1, temp, ctx->mem_idx, mop);
+ tcg_gen_mov_i32(r2, temp);
}
static void gen_ld_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,
MemOp mop)
{
TCGv temp = tcg_temp_new();
- tcg_gen_addi_tl(temp, r2, off);
- tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop);
- tcg_gen_mov_tl(r2, temp);
+ tcg_gen_addi_i32(temp, r2, off);
+ tcg_gen_qemu_ld_i32(r1, temp, ctx->mem_idx, mop);
+ tcg_gen_mov_i32(r2, temp);
}
/* M(EA, word) = (M(EA, word) & ~E[a][63:32]) | (E[a][31:0] & E[a][63:32]); */
@@ -285,15 +285,15 @@ static void gen_ldmst(DisasContext *ctx, int ereg, TCGv ea)
CHECK_REG_PAIR(ereg);
/* temp = (M(EA, word) */
- tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
+ tcg_gen_qemu_ld_i32(temp, ea, ctx->mem_idx, MO_LEUL);
/* temp = temp & ~E[a][63:32]) */
- tcg_gen_andc_tl(temp, temp, cpu_gpr_d[ereg+1]);
+ tcg_gen_andc_i32(temp, temp, cpu_gpr_d[ereg + 1]);
/* temp2 = (E[a][31:0] & E[a][63:32]); */
- tcg_gen_and_tl(temp2, cpu_gpr_d[ereg], cpu_gpr_d[ereg+1]);
+ tcg_gen_and_i32(temp2, cpu_gpr_d[ereg], cpu_gpr_d[ereg + 1]);
/* temp = temp | temp2; */
- tcg_gen_or_tl(temp, temp, temp2);
+ tcg_gen_or_i32(temp, temp, temp2);
/* M(EA, word) = temp; */
- tcg_gen_qemu_st_tl(temp, ea, ctx->mem_idx, MO_LEUL);
+ tcg_gen_qemu_st_i32(temp, ea, ctx->mem_idx, MO_LEUL);
}
/* tmp = M(EA, word);
@@ -303,9 +303,9 @@ static void gen_swap(DisasContext *ctx, int reg, TCGv ea)
{
TCGv temp = tcg_temp_new();
- tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
- tcg_gen_qemu_st_tl(cpu_gpr_d[reg], ea, ctx->mem_idx, MO_LEUL);
- tcg_gen_mov_tl(cpu_gpr_d[reg], temp);
+ tcg_gen_qemu_ld_i32(temp, ea, ctx->mem_idx, MO_LEUL);
+ tcg_gen_qemu_st_i32(cpu_gpr_d[reg], ea, ctx->mem_idx, MO_LEUL);
+ tcg_gen_mov_i32(cpu_gpr_d[reg], temp);
}
static void gen_cmpswap(DisasContext *ctx, int reg, TCGv ea)
@@ -313,11 +313,11 @@ static void gen_cmpswap(DisasContext *ctx, int reg, TCGv ea)
TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
CHECK_REG_PAIR(reg);
- tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
- tcg_gen_movcond_tl(TCG_COND_EQ, temp2, cpu_gpr_d[reg+1], temp,
+ tcg_gen_qemu_ld_i32(temp, ea, ctx->mem_idx, MO_LEUL);
+ tcg_gen_movcond_i32(TCG_COND_EQ, temp2, cpu_gpr_d[reg + 1], temp,
cpu_gpr_d[reg], temp);
- tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL);
- tcg_gen_mov_tl(cpu_gpr_d[reg], temp);
+ tcg_gen_qemu_st_i32(temp2, ea, ctx->mem_idx, MO_LEUL);
+ tcg_gen_mov_i32(cpu_gpr_d[reg], temp);
}
static void gen_swapmsk(DisasContext *ctx, int reg, TCGv ea)
@@ -326,12 +326,12 @@ static void gen_swapmsk(DisasContext *ctx, int reg, TCGv ea)
TCGv temp2 = tcg_temp_new();
TCGv temp3 = tcg_temp_new();
CHECK_REG_PAIR(reg);
- tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
- tcg_gen_and_tl(temp2, cpu_gpr_d[reg], cpu_gpr_d[reg+1]);
- tcg_gen_andc_tl(temp3, temp, cpu_gpr_d[reg+1]);
- tcg_gen_or_tl(temp2, temp2, temp3);
- tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL);
- tcg_gen_mov_tl(cpu_gpr_d[reg], temp);
+ tcg_gen_qemu_ld_i32(temp, ea, ctx->mem_idx, MO_LEUL);
+ tcg_gen_and_i32(temp2, cpu_gpr_d[reg], cpu_gpr_d[reg + 1]);
+ tcg_gen_andc_i32(temp3, temp, cpu_gpr_d[reg + 1]);
+ tcg_gen_or_i32(temp2, temp2, temp3);
+ tcg_gen_qemu_st_i32(temp2, ea, ctx->mem_idx, MO_LEUL);
+ tcg_gen_mov_i32(cpu_gpr_d[reg], temp);
}
/* We generate loads and store to core special function register (csfr) through
@@ -341,7 +341,7 @@ static void gen_swapmsk(DisasContext *ctx, int reg, TCGv ea)
#define R(ADDRESS, REG, FEATURE) \
case ADDRESS: \
if (has_feature(ctx, FEATURE)) { \
- tcg_gen_ld_tl(ret, tcg_env, offsetof(CPUTriCoreState, REG)); \
+ tcg_gen_ld_i32(ret, tcg_env, offsetof(CPUTriCoreState, REG)); \
} \
break;
#define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE)
@@ -366,7 +366,7 @@ static inline void gen_mfcr(DisasContext *ctx, TCGv ret, int32_t offset)
#define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) \
case ADDRESS: \
if (has_feature(ctx, FEATURE)) { \
- tcg_gen_st_tl(r1, tcg_env, offsetof(CPUTriCoreState, REG)); \
+ tcg_gen_st_i32(r1, tcg_env, offsetof(CPUTriCoreState, REG)); \
} \
break;
/* Endinit protected registers
@@ -399,20 +399,20 @@ static inline void gen_add_d(TCGv ret, TCGv r1, TCGv r2)
TCGv t0 = tcg_temp_new_i32();
TCGv result = tcg_temp_new_i32();
/* Addition and set V/SV bits */
- tcg_gen_add_tl(result, r1, r2);
+ tcg_gen_add_i32(result, r1, r2);
/* calc V bit */
- tcg_gen_xor_tl(cpu_PSW_V, result, r1);
- tcg_gen_xor_tl(t0, r1, r2);
- tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
+ tcg_gen_xor_i32(cpu_PSW_V, result, r1);
+ tcg_gen_xor_i32(t0, r1, r2);
+ tcg_gen_andc_i32(cpu_PSW_V, cpu_PSW_V, t0);
/* Calc SV bit */
- tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
+ tcg_gen_or_i32(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* Calc AV/SAV bits */
- tcg_gen_add_tl(cpu_PSW_AV, result, result);
- tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
+ tcg_gen_add_i32(cpu_PSW_AV, result, result);
+ tcg_gen_xor_i32(cpu_PSW_AV, result, cpu_PSW_AV);
/* calc SAV */
- tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
+ tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
/* write back result */
- tcg_gen_mov_tl(ret, result);
+ tcg_gen_mov_i32(ret, result);
}
static inline void
@@ -430,13 +430,13 @@ gen_add64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2)
tcg_gen_andc_i64(t1, t1, t0);
tcg_gen_extrh_i64_i32(cpu_PSW_V, t1);
/* calc SV bit */
- tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
+ tcg_gen_or_i32(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* calc AV/SAV bits */
tcg_gen_extrh_i64_i32(temp, result);
- tcg_gen_add_tl(cpu_PSW_AV, temp, temp);
- tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV);
+ tcg_gen_add_i32(cpu_PSW_AV, temp, temp);
+ tcg_gen_xor_i32(cpu_PSW_AV, temp, cpu_PSW_AV);
/* calc SAV */
- tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
+ tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
/* write back result */
tcg_gen_mov_i64(ret, result);
}
@@ -453,38 +453,38 @@ gen_addsub64_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
(*op1)(temp, r1_low, r2);
/* calc V0 bit */
- tcg_gen_xor_tl(temp2, temp, r1_low);
- tcg_gen_xor_tl(temp3, r1_low, r2);
+ tcg_gen_xor_i32(temp2, temp, r1_low);
+ tcg_gen_xor_i32(temp3, r1_low, r2);
if (op1 == tcg_gen_add_tl) {
- tcg_gen_andc_tl(temp2, temp2, temp3);
+ tcg_gen_andc_i32(temp2, temp2, temp3);
} else {
- tcg_gen_and_tl(temp2, temp2, temp3);
+ tcg_gen_and_i32(temp2, temp2, temp3);
}
(*op2)(temp3, r1_high, r3);
/* calc V1 bit */
- tcg_gen_xor_tl(cpu_PSW_V, temp3, r1_high);
- tcg_gen_xor_tl(temp4, r1_high, r3);
+ tcg_gen_xor_i32(cpu_PSW_V, temp3, r1_high);
+ tcg_gen_xor_i32(temp4, r1_high, r3);
if (op2 == tcg_gen_add_tl) {
- tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, temp4);
+ tcg_gen_andc_i32(cpu_PSW_V, cpu_PSW_V, temp4);
} else {
- tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp4);
+ tcg_gen_and_i32(cpu_PSW_V, cpu_PSW_V, temp4);
}
/* combine V0/V1 bits */
- tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp2);
+ tcg_gen_or_i32(cpu_PSW_V, cpu_PSW_V, temp2);
/* calc sv bit */
- tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
+ tcg_gen_or_i32(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* write result */
- tcg_gen_mov_tl(ret_low, temp);
- tcg_gen_mov_tl(ret_high, temp3);
+ tcg_gen_mov_i32(ret_low, temp);
+ tcg_gen_mov_i32(ret_high, temp3);
/* calc AV bit */
- tcg_gen_add_tl(temp, ret_low, ret_low);
- tcg_gen_xor_tl(temp, temp, ret_low);
- tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
- tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, ret_high);
- tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp);
+ tcg_gen_add_i32(temp, ret_low, ret_low);
+ tcg_gen_xor_i32(temp, temp, ret_low);
+ tcg_gen_add_i32(cpu_PSW_AV, ret_high, ret_high);
+ tcg_gen_xor_i32(cpu_PSW_AV, cpu_PSW_AV, ret_high);
+ tcg_gen_or_i32(cpu_PSW_AV, cpu_PSW_AV, temp);
/* calc SAV bit */
- tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
+ tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
}
/* ret = r2 + (r1 * r3); */
@@ -509,14 +509,14 @@ static inline void gen_madd32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3)
tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL);
tcg_gen_or_i64(t2, t2, t3);
tcg_gen_extrl_i64_i32(cpu_PSW_V, t2);
- tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
+ tcg_gen_shli_i32(cpu_PSW_V, cpu_PSW_V, 31);
/* Calc SV bit */
- tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
+ tcg_gen_or_i32(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* Calc AV/SAV bits */
- tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
- tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
+ tcg_gen_add_i32(cpu_PSW_AV, ret, ret);
+ tcg_gen_xor_i32(cpu_PSW_AV, ret, cpu_PSW_AV);
/* calc SAV */
- tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
+ tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
}
static inline void gen_maddi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con)
@@ -534,23 +534,23 @@ gen_madd64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
TCGv t3 = tcg_temp_new();
TCGv t4 = tcg_temp_new();
- tcg_gen_muls2_tl(t1, t2, r1, r3);
+ tcg_gen_muls2_i32(t1, t2, r1, r3);
/* only the add can overflow */
- tcg_gen_add2_tl(t3, t4, r2_low, r2_high, t1, t2);
+ tcg_gen_add2_i32(t3, t4, r2_low, r2_high, t1, t2);
/* calc V bit */
- tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high);
- tcg_gen_xor_tl(t1, r2_high, t2);
- tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t1);
+ tcg_gen_xor_i32(cpu_PSW_V, t4, r2_high);
+ tcg_gen_xor_i32(t1, r2_high, t2);
+ tcg_gen_andc_i32(cpu_PSW_V, cpu_PSW_V, t1);
/* Calc SV bit */
- tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
+ tcg_gen_or_i32(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* Calc AV/SAV bits */
- tcg_gen_add_tl(cpu_PSW_AV, t4, t4);
- tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV);
+ tcg_gen_add_i32(cpu_PSW_AV, t4, t4);
+ tcg_gen_xor_i32(cpu_PSW_AV, t4, cpu_PSW_AV);
/* calc SAV */
- tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
+ tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
/* write back the result */
- tcg_gen_mov_tl(ret_low, t3);
- tcg_gen_mov_tl(ret_high, t4);
+ tcg_gen_mov_i32(ret_low, t3);
+ tcg_gen_mov_i32(ret_high, t4);
}
static inline void
@@ -573,14 +573,14 @@ gen_maddu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
calc V bit */
tcg_gen_setcond_i64(TCG_COND_LTU, t2, t2, t1);
tcg_gen_extrl_i64_i32(cpu_PSW_V, t2);
- tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
+ tcg_gen_shli_i32(cpu_PSW_V, cpu_PSW_V, 31);
/* Calc SV bit */
- tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
+ tcg_gen_or_i32(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* Calc AV/SAV bits */
- tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
- tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
+ tcg_gen_add_i32(cpu_PSW_AV, ret_high, ret_high);
+ tcg_gen_xor_i32(cpu_PSW_AV, ret_high, cpu_PSW_AV);
/* calc SAV */
- tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
+ tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
}
static inline void
@@ -714,13 +714,13 @@ gen_madds_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
}
tcg_gen_extr_i64_i32(temp, temp2, temp64);
gen_adds(ret_low, r1_low, temp);
- tcg_gen_mov_tl(temp, cpu_PSW_V);
- tcg_gen_mov_tl(temp3, cpu_PSW_AV);
+ tcg_gen_mov_i32(temp, cpu_PSW_V);
+ tcg_gen_mov_i32(temp3, cpu_PSW_AV);
gen_adds(ret_high, r1_high, temp2);
/* combine v bits */
- tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
+ tcg_gen_or_i32(cpu_PSW_V, cpu_PSW_V, temp);
/* combine av bits */
- tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
+ tcg_gen_or_i32(cpu_PSW_AV, cpu_PSW_AV, temp3);
}
static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2);
@@ -751,13 +751,13 @@ gen_maddsus_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
}
tcg_gen_extr_i64_i32(temp, temp2, temp64);
gen_subs(ret_low, r1_low, temp);
- tcg_gen_mov_tl(temp, cpu_PSW_V);
- tcg_gen_mov_tl(temp3, cpu_PSW_AV);
+ tcg_gen_mov_i32(temp, cpu_PSW_V);
+ tcg_gen_mov_i32(temp3, cpu_PSW_AV);
gen_adds(ret_high, r1_high, temp2);
/* combine v bits */
- tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
+ tcg_gen_or_i32(cpu_PSW_V, cpu_PSW_V, temp);
/* combine av bits */
- tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
+ tcg_gen_or_i32(cpu_PSW_AV, cpu_PSW_AV, temp3);
}
static inline void
@@ -876,8 +876,8 @@ gen_maddr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
- tcg_gen_andi_tl(temp2, r1, 0xffff0000);
- tcg_gen_shli_tl(temp, r1, 16);
+ tcg_gen_andi_i32(temp2, r1, 0xffff0000);
+ tcg_gen_shli_i32(temp, r1, 16);
gen_maddr64_h(ret, temp, temp2, r2, r3, n, mode);
}
@@ -902,8 +902,8 @@ gen_maddsur32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
break;
}
- tcg_gen_andi_tl(temp2, r1, 0xffff0000);
- tcg_gen_shli_tl(temp, r1, 16);
+ tcg_gen_andi_i32(temp2, r1, 0xffff0000);
+ tcg_gen_shli_i32(temp, r1, 16);
gen_helper_addsur_h(ret, tcg_env, temp64, temp, temp2);
}
@@ -937,8 +937,8 @@ gen_maddr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
- tcg_gen_andi_tl(temp2, r1, 0xffff0000);
- tcg_gen_shli_tl(temp, r1, 16);
+ tcg_gen_andi_i32(temp2, r1, 0xffff0000);
+ tcg_gen_shli_i32(temp, r1, 16);
gen_maddr64s_h(ret, temp, temp2, r2, r3, n, mode);
}
@@ -963,8 +963,8 @@ gen_maddsur32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
break;
}
- tcg_gen_andi_tl(temp2, r1, 0xffff0000);
- tcg_gen_shli_tl(temp, r1, 16);
+ tcg_gen_andi_i32(temp2, r1, 0xffff0000);
+ tcg_gen_shli_i32(temp, r1, 16);
gen_helper_addsur_h_ssov(ret, tcg_env, temp64, temp, temp2);
}
@@ -1009,27 +1009,27 @@ gen_madd32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL);
tcg_gen_or_i64(t1, t1, t2);
tcg_gen_extrl_i64_i32(cpu_PSW_V, t1);
- tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
+ tcg_gen_shli_i32(cpu_PSW_V, cpu_PSW_V, 31);
/* We produce an overflow on the host if the mul before was
(0x80000000 * 0x80000000) << 1). If this is the
case, we negate the ovf. */
if (n == 1) {
- tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000);
- tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3);
- tcg_gen_and_tl(temp, temp, temp2);
- tcg_gen_shli_tl(temp, temp, 31);
+ tcg_gen_setcondi_i32(TCG_COND_EQ, temp, arg2, 0x80000000);
+ tcg_gen_setcond_i32(TCG_COND_EQ, temp2, arg2, arg3);
+ tcg_gen_and_i32(temp, temp, temp2);
+ tcg_gen_shli_i32(temp, temp, 31);
/* negate v bit, if special condition */
- tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp);
+ tcg_gen_xor_i32(cpu_PSW_V, cpu_PSW_V, temp);
}
/* Calc SV bit */
- tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
+ tcg_gen_or_i32(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* Calc AV/SAV bits */
- tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3);
- tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV);
+ tcg_gen_add_i32(cpu_PSW_AV, temp3, temp3);
+ tcg_gen_xor_i32(cpu_PSW_AV, temp3, cpu_PSW_AV);
/* calc SAV */
- tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
+ tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
/* write back result */
- tcg_gen_mov_tl(ret, temp3);
+ tcg_gen_mov_i32(ret, temp3);
}
static inline void
@@ -1038,13 +1038,13 @@ gen_m16add32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
if (n == 0) {
- tcg_gen_mul_tl(temp, arg2, arg3);
+ tcg_gen_mul_i32(temp, arg2, arg3);
} else { /* n is expected to be 1 */
- tcg_gen_mul_tl(temp, arg2, arg3);
- tcg_gen_shli_tl(temp, temp, 1);
+ tcg_gen_mul_i32(temp, arg2, arg3);
+ tcg_gen_shli_i32(temp, temp, 1);
/* catch special case r1 = r2 = 0x8000 */
- tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
- tcg_gen_sub_tl(temp, temp, temp2);
+ tcg_gen_setcondi_i32(TCG_COND_EQ, temp2, temp, 0x80000000);
+ tcg_gen_sub_i32(temp, temp, temp2);
}
gen_add_d(ret, arg1, temp);
}
@@ -1055,13 +1055,13 @@ gen_m16adds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
if (n == 0) {
- tcg_gen_mul_tl(temp, arg2, arg3);
+ tcg_gen_mul_i32(temp, arg2, arg3);
} else { /* n is expected to be 1 */
- tcg_gen_mul_tl(temp, arg2, arg3);
- tcg_gen_shli_tl(temp, temp, 1);
+ tcg_gen_mul_i32(temp, arg2, arg3);
+ tcg_gen_shli_i32(temp, temp, 1);
/* catch special case r1 = r2 = 0x8000 */
- tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
- tcg_gen_sub_tl(temp, temp, temp2);
+ tcg_gen_setcondi_i32(TCG_COND_EQ, temp2, temp, 0x80000000);
+ tcg_gen_sub_i32(temp, temp, temp2);
}
gen_adds(ret, arg1, temp);
}
@@ -1077,13 +1077,13 @@ gen_m16add64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
TCGv_i64 t3 = tcg_temp_new_i64();
if (n == 0) {
- tcg_gen_mul_tl(temp, arg2, arg3);
+ tcg_gen_mul_i32(temp, arg2, arg3);
} else { /* n is expected to be 1 */
- tcg_gen_mul_tl(temp, arg2, arg3);
- tcg_gen_shli_tl(temp, temp, 1);
+ tcg_gen_mul_i32(temp, arg2, arg3);
+ tcg_gen_shli_i32(temp, temp, 1);
/* catch special case r1 = r2 = 0x8000 */
- tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
- tcg_gen_sub_tl(temp, temp, temp2);
+ tcg_gen_setcondi_i32(TCG_COND_EQ, temp2, temp, 0x80000000);
+ tcg_gen_sub_i32(temp, temp, temp2);
}
tcg_gen_ext_i32_i64(t2, temp);
tcg_gen_shli_i64(t2, t2, 16);
@@ -1103,13 +1103,13 @@ gen_m16adds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
TCGv_i64 t2 = tcg_temp_new_i64();
if (n == 0) {
- tcg_gen_mul_tl(temp, arg2, arg3);
+ tcg_gen_mul_i32(temp, arg2, arg3);
} else { /* n is expected to be 1 */
- tcg_gen_mul_tl(temp, arg2, arg3);
- tcg_gen_shli_tl(temp, temp, 1);
+ tcg_gen_mul_i32(temp, arg2, arg3);
+ tcg_gen_shli_i32(temp, temp, 1);
/* catch special case r1 = r2 = 0x8000 */
- tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
- tcg_gen_sub_tl(temp, temp, temp2);
+ tcg_gen_setcondi_i32(TCG_COND_EQ, temp2, temp, 0x80000000);
+ tcg_gen_sub_i32(temp, temp, temp2);
}
tcg_gen_ext_i32_i64(t2, temp);
tcg_gen_shli_i64(t2, t2, 16);
@@ -1149,22 +1149,22 @@ gen_madd64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
if (n == 1) {
temp = tcg_temp_new();
temp2 = tcg_temp_new();
- tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000);
- tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3);
- tcg_gen_and_tl(temp, temp, temp2);
- tcg_gen_shli_tl(temp, temp, 31);
+ tcg_gen_setcondi_i32(TCG_COND_EQ, temp, arg2, 0x80000000);
+ tcg_gen_setcond_i32(TCG_COND_EQ, temp2, arg2, arg3);
+ tcg_gen_and_i32(temp, temp, temp2);
+ tcg_gen_shli_i32(temp, temp, 31);
/* negate v bit, if special condition */
- tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp);
+ tcg_gen_xor_i32(cpu_PSW_V, cpu_PSW_V, temp);
}
/* write back result */
tcg_gen_extr_i64_i32(rl, rh, t4);
/* Calc SV bit */
- tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
+ tcg_gen_or_i32(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* Calc AV/SAV bits */
- tcg_gen_add_tl(cpu_PSW_AV, rh, rh);
- tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV);
+ tcg_gen_add_i32(cpu_PSW_AV, rh, rh);
+ tcg_gen_xor_i32(cpu_PSW_AV, rh, cpu_PSW_AV);
/* calc SAV */
- tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
+ tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
}
static inline void
@@ -1219,15 +1219,15 @@ static inline void gen_msub32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3)
tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL);
tcg_gen_or_i64(t2, t2, t3);
tcg_gen_extrl_i64_i32(cpu_PSW_V, t2);
- tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
+ tcg_gen_shli_i32(cpu_PSW_V, cpu_PSW_V, 31);
/* Calc SV bit */
- tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
+ tcg_gen_or_i32(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* Calc AV/SAV bits */
- tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
- tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
+ tcg_gen_add_i32(cpu_PSW_AV, ret, ret);
+ tcg_gen_xor_i32(cpu_PSW_AV, ret, cpu_PSW_AV);
/* calc SAV */
- tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
+ tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
}
static inline void gen_msubi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con)
@@ -1245,23 +1245,23 @@ gen_msub64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
TCGv t3 = tcg_temp_new();
TCGv t4 = tcg_temp_new();
- tcg_gen_muls2_tl(t1, t2, r1, r3);
+ tcg_gen_muls2_i32(t1, t2, r1, r3);
/* only the sub can overflow */
- tcg_gen_sub2_tl(t3, t4, r2_low, r2_high, t1, t2);
+ tcg_gen_sub2_i32(t3, t4, r2_low, r2_high, t1, t2);
/* calc V bit */
- tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high);
- tcg_gen_xor_tl(t1, r2_high, t2);
- tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, t1);
+ tcg_gen_xor_i32(cpu_PSW_V, t4, r2_high);
+ tcg_gen_xor_i32(t1, r2_high, t2);
+ tcg_gen_and_i32(cpu_PSW_V, cpu_PSW_V, t1);
/* Calc SV bit */
- tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
+ tcg_gen_or_i32(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* Calc AV/SAV bits */
- tcg_gen_add_tl(cpu_PSW_AV, t4, t4);
- tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV);
+ tcg_gen_add_i32(cpu_PSW_AV, t4, t4);
+ tcg_gen_xor_i32(cpu_PSW_AV, t4, cpu_PSW_AV);
/* calc SAV */
- tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
+ tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
/* write back the result */
- tcg_gen_mov_tl(ret_low, t3);
- tcg_gen_mov_tl(ret_high, t4);
+ tcg_gen_mov_i32(ret_low, t3);
+ tcg_gen_mov_i32(ret_high, t4);
}
static inline void
@@ -1290,14 +1290,14 @@ gen_msubu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
/* calc V bit, only the sub can overflow, if t1 > t2 */
tcg_gen_setcond_i64(TCG_COND_GTU, t1, t1, t2);
tcg_gen_extrl_i64_i32(cpu_PSW_V, t1);
- tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
+ tcg_gen_shli_i32(cpu_PSW_V, cpu_PSW_V, 31);
/* Calc SV bit */
- tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
+ tcg_gen_or_i32(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* Calc AV/SAV bits */
- tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
- tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
+ tcg_gen_add_i32(cpu_PSW_AV, ret_high, ret_high);
+ tcg_gen_xor_i32(cpu_PSW_AV, ret_high, cpu_PSW_AV);
/* calc SAV */
- tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
+ tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
}
static inline void
@@ -1320,22 +1320,22 @@ static inline void gen_add_CC(TCGv ret, TCGv r1, TCGv r2)
TCGv t0 = tcg_temp_new_i32();
TCGv result = tcg_temp_new_i32();
- tcg_gen_movi_tl(t0, 0);
+ tcg_gen_movi_i32(t0, 0);
/* Addition and set C/V/SV bits */
tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, r2, t0);
/* calc V bit */
- tcg_gen_xor_tl(cpu_PSW_V, result, r1);
- tcg_gen_xor_tl(t0, r1, r2);
- tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
+ tcg_gen_xor_i32(cpu_PSW_V, result, r1);
+ tcg_gen_xor_i32(t0, r1, r2);
+ tcg_gen_andc_i32(cpu_PSW_V, cpu_PSW_V, t0);
/* Calc SV bit */
- tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
+ tcg_gen_or_i32(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* Calc AV/SAV bits */
- tcg_gen_add_tl(cpu_PSW_AV, result, result);
- tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
+ tcg_gen_add_i32(cpu_PSW_AV, result, result);
+ tcg_gen_xor_i32(cpu_PSW_AV, result, cpu_PSW_AV);
/* calc SAV */
- tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
+ tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
/* write back result */
- tcg_gen_mov_tl(ret, result);
+ tcg_gen_mov_i32(ret, result);
}
static inline void gen_addi_CC(TCGv ret, TCGv r1, int32_t con)
@@ -1352,18 +1352,18 @@ static inline void gen_addc_CC(TCGv ret, TCGv r1, TCGv r2)
/* Addition, carry and set C/V/SV bits */
tcg_gen_addcio_i32(result, cpu_PSW_C, r1, r2, cpu_PSW_C);
/* calc V bit */
- tcg_gen_xor_tl(cpu_PSW_V, result, r1);
- tcg_gen_xor_tl(t0, r1, r2);
- tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
+ tcg_gen_xor_i32(cpu_PSW_V, result, r1);
+ tcg_gen_xor_i32(t0, r1, r2);
+ tcg_gen_andc_i32(cpu_PSW_V, cpu_PSW_V, t0);
/* Calc SV bit */
- tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
+ tcg_gen_or_i32(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* Calc AV/SAV bits */
- tcg_gen_add_tl(cpu_PSW_AV, result, result);
- tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
+ tcg_gen_add_i32(cpu_PSW_AV, result, result);
+ tcg_gen_xor_i32(cpu_PSW_AV, result, cpu_PSW_AV);
/* calc SAV */
- tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
+ tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
/* write back result */
- tcg_gen_mov_tl(ret, result);
+ tcg_gen_mov_i32(ret, result);
}
static inline void gen_addci_CC(TCGv ret, TCGv r1, int32_t con)
@@ -1382,27 +1382,27 @@ static inline void gen_cond_add(TCGCond cond, TCGv r1, TCGv r2, TCGv r3,
TCGv t0 = tcg_constant_i32(0);
/* create mask for sticky bits */
- tcg_gen_setcond_tl(cond, mask, r4, t0);
- tcg_gen_shli_tl(mask, mask, 31);
+ tcg_gen_setcond_i32(cond, mask, r4, t0);
+ tcg_gen_shli_i32(mask, mask, 31);
- tcg_gen_add_tl(result, r1, r2);
+ tcg_gen_add_i32(result, r1, r2);
/* Calc PSW_V */
- tcg_gen_xor_tl(temp, result, r1);
- tcg_gen_xor_tl(temp2, r1, r2);
- tcg_gen_andc_tl(temp, temp, temp2);
- tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V);
+ tcg_gen_xor_i32(temp, result, r1);
+ tcg_gen_xor_i32(temp2, r1, r2);
+ tcg_gen_andc_i32(temp, temp, temp2);
+ tcg_gen_movcond_i32(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V);
/* Set PSW_SV */
- tcg_gen_and_tl(temp, temp, mask);
- tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV);
+ tcg_gen_and_i32(temp, temp, mask);
+ tcg_gen_or_i32(cpu_PSW_SV, temp, cpu_PSW_SV);
/* calc AV bit */
- tcg_gen_add_tl(temp, result, result);
- tcg_gen_xor_tl(temp, temp, result);
- tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV);
+ tcg_gen_add_i32(temp, result, result);
+ tcg_gen_xor_i32(temp, temp, result);
+ tcg_gen_movcond_i32(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV);
/* calc SAV bit */
- tcg_gen_and_tl(temp, temp, mask);
- tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV);
+ tcg_gen_and_i32(temp, temp, mask);
+ tcg_gen_or_i32(cpu_PSW_SAV, temp, cpu_PSW_SAV);
/* write back result */
- tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1);
+ tcg_gen_movcond_i32(cond, r3, r4, t0, result, r1);
}
static inline void gen_condi_add(TCGCond cond, TCGv r1, int32_t r2,
@@ -1417,20 +1417,20 @@ static inline void gen_sub_d(TCGv ret, TCGv r1, TCGv r2)
TCGv temp = tcg_temp_new_i32();
TCGv result = tcg_temp_new_i32();
- tcg_gen_sub_tl(result, r1, r2);
+ tcg_gen_sub_i32(result, r1, r2);
/* calc V bit */
- tcg_gen_xor_tl(cpu_PSW_V, result, r1);
- tcg_gen_xor_tl(temp, r1, r2);
- tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
+ tcg_gen_xor_i32(cpu_PSW_V, result, r1);
+ tcg_gen_xor_i32(temp, r1, r2);
+ tcg_gen_and_i32(cpu_PSW_V, cpu_PSW_V, temp);
/* calc SV bit */
- tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
+ tcg_gen_or_i32(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* Calc AV bit */
- tcg_gen_add_tl(cpu_PSW_AV, result, result);
- tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
+ tcg_gen_add_i32(cpu_PSW_AV, result, result);
+ tcg_gen_xor_i32(cpu_PSW_AV, result, cpu_PSW_AV);
/* calc SAV bit */
- tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
+ tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
/* write back result */
- tcg_gen_mov_tl(ret, result);
+ tcg_gen_mov_i32(ret, result);
}
static inline void
@@ -1448,13 +1448,13 @@ gen_sub64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2)
tcg_gen_and_i64(t1, t1, t0);
tcg_gen_extrh_i64_i32(cpu_PSW_V, t1);
/* calc SV bit */
- tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
+ tcg_gen_or_i32(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* calc AV/SAV bits */
tcg_gen_extrh_i64_i32(temp, result);
- tcg_gen_add_tl(cpu_PSW_AV, temp, temp);
- tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV);
+ tcg_gen_add_i32(cpu_PSW_AV, temp, temp);
+ tcg_gen_xor_i32(cpu_PSW_AV, temp, cpu_PSW_AV);
/* calc SAV */
- tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
+ tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
/* write back result */
tcg_gen_mov_i64(ret, result);
}
@@ -1464,28 +1464,28 @@ static inline void gen_sub_CC(TCGv ret, TCGv r1, TCGv r2)
TCGv result = tcg_temp_new();
TCGv temp = tcg_temp_new();
- tcg_gen_sub_tl(result, r1, r2);
+ tcg_gen_sub_i32(result, r1, r2);
/* calc C bit */
- tcg_gen_setcond_tl(TCG_COND_GEU, cpu_PSW_C, r1, r2);
+ tcg_gen_setcond_i32(TCG_COND_GEU, cpu_PSW_C, r1, r2);
/* calc V bit */
- tcg_gen_xor_tl(cpu_PSW_V, result, r1);
- tcg_gen_xor_tl(temp, r1, r2);
- tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
+ tcg_gen_xor_i32(cpu_PSW_V, result, r1);
+ tcg_gen_xor_i32(temp, r1, r2);
+ tcg_gen_and_i32(cpu_PSW_V, cpu_PSW_V, temp);
/* calc SV bit */
- tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
+ tcg_gen_or_i32(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* Calc AV bit */
- tcg_gen_add_tl(cpu_PSW_AV, result, result);
- tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
+ tcg_gen_add_i32(cpu_PSW_AV, result, result);
+ tcg_gen_xor_i32(cpu_PSW_AV, result, cpu_PSW_AV);
/* calc SAV bit */
- tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
+ tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
/* write back result */
- tcg_gen_mov_tl(ret, result);
+ tcg_gen_mov_i32(ret, result);
}
static inline void gen_subc_CC(TCGv ret, TCGv r1, TCGv r2)
{
TCGv temp = tcg_temp_new();
- tcg_gen_not_tl(temp, r2);
+ tcg_gen_not_i32(temp, r2);
gen_addc_CC(ret, r1, temp);
}
@@ -1499,27 +1499,27 @@ static inline void gen_cond_sub(TCGCond cond, TCGv r1, TCGv r2, TCGv r3,
TCGv t0 = tcg_constant_i32(0);
/* create mask for sticky bits */
- tcg_gen_setcond_tl(cond, mask, r4, t0);
- tcg_gen_shli_tl(mask, mask, 31);
+ tcg_gen_setcond_i32(cond, mask, r4, t0);
+ tcg_gen_shli_i32(mask, mask, 31);
- tcg_gen_sub_tl(result, r1, r2);
+ tcg_gen_sub_i32(result, r1, r2);
/* Calc PSW_V */
- tcg_gen_xor_tl(temp, result, r1);
- tcg_gen_xor_tl(temp2, r1, r2);
- tcg_gen_and_tl(temp, temp, temp2);
- tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V);
+ tcg_gen_xor_i32(temp, result, r1);
+ tcg_gen_xor_i32(temp2, r1, r2);
+ tcg_gen_and_i32(temp, temp, temp2);
+ tcg_gen_movcond_i32(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V);
/* Set PSW_SV */
- tcg_gen_and_tl(temp, temp, mask);
- tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV);
+ tcg_gen_and_i32(temp, temp, mask);
+ tcg_gen_or_i32(cpu_PSW_SV, temp, cpu_PSW_SV);
/* calc AV bit */
- tcg_gen_add_tl(temp, result, result);
- tcg_gen_xor_tl(temp, temp, result);
- tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV);
+ tcg_gen_add_i32(temp, result, result);
+ tcg_gen_xor_i32(temp, temp, result);
+ tcg_gen_movcond_i32(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV);
/* calc SAV bit */
- tcg_gen_and_tl(temp, temp, mask);
- tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV);
+ tcg_gen_and_i32(temp, temp, mask);
+ tcg_gen_or_i32(cpu_PSW_SAV, temp, cpu_PSW_SAV);
/* write back result */
- tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1);
+ tcg_gen_movcond_i32(cond, r3, r4, t0, result, r1);
}
static inline void
@@ -1575,13 +1575,13 @@ gen_msubs_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
}
tcg_gen_extr_i64_i32(temp, temp2, temp64);
gen_subs(ret_low, r1_low, temp);
- tcg_gen_mov_tl(temp, cpu_PSW_V);
- tcg_gen_mov_tl(temp3, cpu_PSW_AV);
+ tcg_gen_mov_i32(temp, cpu_PSW_V);
+ tcg_gen_mov_i32(temp3, cpu_PSW_AV);
gen_subs(ret_high, r1_high, temp2);
/* combine v bits */
- tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
+ tcg_gen_or_i32(cpu_PSW_V, cpu_PSW_V, temp);
/* combine av bits */
- tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
+ tcg_gen_or_i32(cpu_PSW_AV, cpu_PSW_AV, temp3);
}
static inline void
@@ -1667,8 +1667,8 @@ gen_msubr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
- tcg_gen_andi_tl(temp2, r1, 0xffff0000);
- tcg_gen_shli_tl(temp, r1, 16);
+ tcg_gen_andi_i32(temp2, r1, 0xffff0000);
+ tcg_gen_shli_i32(temp, r1, 16);
gen_msubr64_h(ret, temp, temp2, r2, r3, n, mode);
}
@@ -1701,8 +1701,8 @@ gen_msubr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
- tcg_gen_andi_tl(temp2, r1, 0xffff0000);
- tcg_gen_shli_tl(temp, r1, 16);
+ tcg_gen_andi_i32(temp2, r1, 0xffff0000);
+ tcg_gen_shli_i32(temp, r1, 16);
gen_msubr64s_h(ret, temp, temp2, r2, r3, n, mode);
}
@@ -1749,16 +1749,16 @@ gen_msub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL);
tcg_gen_or_i64(t1, t1, t2);
tcg_gen_extrl_i64_i32(cpu_PSW_V, t1);
- tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
+ tcg_gen_shli_i32(cpu_PSW_V, cpu_PSW_V, 31);
/* Calc SV bit */
- tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
+ tcg_gen_or_i32(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* Calc AV/SAV bits */
- tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3);
- tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV);
+ tcg_gen_add_i32(cpu_PSW_AV, temp3, temp3);
+ tcg_gen_xor_i32(cpu_PSW_AV, temp3, cpu_PSW_AV);
/* calc SAV */
- tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
+ tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
/* write back result */
- tcg_gen_mov_tl(ret, temp3);
+ tcg_gen_mov_i32(ret, temp3);
}
static inline void
@@ -1767,13 +1767,13 @@ gen_m16sub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
if (n == 0) {
- tcg_gen_mul_tl(temp, arg2, arg3);
+ tcg_gen_mul_i32(temp, arg2, arg3);
} else { /* n is expected to be 1 */
- tcg_gen_mul_tl(temp, arg2, arg3);
- tcg_gen_shli_tl(temp, temp, 1);
+ tcg_gen_mul_i32(temp, arg2, arg3);
+ tcg_gen_shli_i32(temp, temp, 1);
/* catch special case r1 = r2 = 0x8000 */
- tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
- tcg_gen_sub_tl(temp, temp, temp2);
+ tcg_gen_setcondi_i32(TCG_COND_EQ, temp2, temp, 0x80000000);
+ tcg_gen_sub_i32(temp, temp, temp2);
}
gen_sub_d(ret, arg1, temp);
}
@@ -1784,13 +1784,13 @@ gen_m16subs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
if (n == 0) {
- tcg_gen_mul_tl(temp, arg2, arg3);
+ tcg_gen_mul_i32(temp, arg2, arg3);
} else { /* n is expected to be 1 */
- tcg_gen_mul_tl(temp, arg2, arg3);
- tcg_gen_shli_tl(temp, temp, 1);
+ tcg_gen_mul_i32(temp, arg2, arg3);
+ tcg_gen_shli_i32(temp, temp, 1);
/* catch special case r1 = r2 = 0x8000 */
- tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
- tcg_gen_sub_tl(temp, temp, temp2);
+ tcg_gen_setcondi_i32(TCG_COND_EQ, temp2, temp, 0x80000000);
+ tcg_gen_sub_i32(temp, temp, temp2);
}
gen_subs(ret, arg1, temp);
}
@@ -1806,13 +1806,13 @@ gen_m16sub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
TCGv_i64 t3 = tcg_temp_new_i64();
if (n == 0) {
- tcg_gen_mul_tl(temp, arg2, arg3);
+ tcg_gen_mul_i32(temp, arg2, arg3);
} else { /* n is expected to be 1 */
- tcg_gen_mul_tl(temp, arg2, arg3);
- tcg_gen_shli_tl(temp, temp, 1);
+ tcg_gen_mul_i32(temp, arg2, arg3);
+ tcg_gen_shli_i32(temp, temp, 1);
/* catch special case r1 = r2 = 0x8000 */
- tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
- tcg_gen_sub_tl(temp, temp, temp2);
+ tcg_gen_setcondi_i32(TCG_COND_EQ, temp2, temp, 0x80000000);
+ tcg_gen_sub_i32(temp, temp, temp2);
}
tcg_gen_ext_i32_i64(t2, temp);
tcg_gen_shli_i64(t2, t2, 16);
@@ -1832,13 +1832,13 @@ gen_m16subs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
TCGv_i64 t2 = tcg_temp_new_i64();
if (n == 0) {
- tcg_gen_mul_tl(temp, arg2, arg3);
+ tcg_gen_mul_i32(temp, arg2, arg3);
} else { /* n is expected to be 1 */
- tcg_gen_mul_tl(temp, arg2, arg3);
- tcg_gen_shli_tl(temp, temp, 1);
+ tcg_gen_mul_i32(temp, arg2, arg3);
+ tcg_gen_shli_i32(temp, temp, 1);
/* catch special case r1 = r2 = 0x8000 */
- tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
- tcg_gen_sub_tl(temp, temp, temp2);
+ tcg_gen_setcondi_i32(TCG_COND_EQ, temp2, temp, 0x80000000);
+ tcg_gen_sub_i32(temp, temp, temp2);
}
tcg_gen_ext_i32_i64(t2, temp);
tcg_gen_shli_i64(t2, t2, 16);
@@ -1878,22 +1878,22 @@ gen_msub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
if (n == 1) {
temp = tcg_temp_new();
temp2 = tcg_temp_new();
- tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000);
- tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3);
- tcg_gen_and_tl(temp, temp, temp2);
- tcg_gen_shli_tl(temp, temp, 31);
+ tcg_gen_setcondi_i32(TCG_COND_EQ, temp, arg2, 0x80000000);
+ tcg_gen_setcond_i32(TCG_COND_EQ, temp2, arg2, arg3);
+ tcg_gen_and_i32(temp, temp, temp2);
+ tcg_gen_shli_i32(temp, temp, 31);
/* negate v bit, if special condition */
- tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp);
+ tcg_gen_xor_i32(cpu_PSW_V, cpu_PSW_V, temp);
}
/* write back result */
tcg_gen_extr_i64_i32(rl, rh, t4);
/* Calc SV bit */
- tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
+ tcg_gen_or_i32(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* Calc AV/SAV bits */
- tcg_gen_add_tl(cpu_PSW_AV, rh, rh);
- tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV);
+ tcg_gen_add_i32(cpu_PSW_AV, rh, rh);
+ tcg_gen_xor_i32(cpu_PSW_AV, rh, cpu_PSW_AV);
/* calc SAV */
- tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
+ tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
}
static inline void
@@ -2012,8 +2012,8 @@ gen_msubadr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
break;
}
- tcg_gen_andi_tl(temp2, r1, 0xffff0000);
- tcg_gen_shli_tl(temp, r1, 16);
+ tcg_gen_andi_i32(temp2, r1, 0xffff0000);
+ tcg_gen_shli_i32(temp, r1, 16);
gen_helper_subadr_h(ret, tcg_env, temp64, temp, temp2);
}
@@ -2043,13 +2043,13 @@ gen_msubads_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
}
tcg_gen_extr_i64_i32(temp, temp2, temp64);
gen_adds(ret_low, r1_low, temp);
- tcg_gen_mov_tl(temp, cpu_PSW_V);
- tcg_gen_mov_tl(temp3, cpu_PSW_AV);
+ tcg_gen_mov_i32(temp, cpu_PSW_V);
+ tcg_gen_mov_i32(temp3, cpu_PSW_AV);
gen_subs(ret_high, r1_high, temp2);
/* combine v bits */
- tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
+ tcg_gen_or_i32(cpu_PSW_V, cpu_PSW_V, temp);
/* combine av bits */
- tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
+ tcg_gen_or_i32(cpu_PSW_AV, cpu_PSW_AV, temp3);
}
static inline void
@@ -2105,24 +2105,24 @@ gen_msubadr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
break;
}
- tcg_gen_andi_tl(temp2, r1, 0xffff0000);
- tcg_gen_shli_tl(temp, r1, 16);
+ tcg_gen_andi_i32(temp2, r1, 0xffff0000);
+ tcg_gen_shli_i32(temp, r1, 16);
gen_helper_subadr_h_ssov(ret, tcg_env, temp64, temp, temp2);
}
static inline void gen_abs(TCGv ret, TCGv r1)
{
- tcg_gen_abs_tl(ret, r1);
+ tcg_gen_abs_i32(ret, r1);
/* overflow can only happen, if r1 = 0x80000000 */
- tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, r1, 0x80000000);
- tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
+ tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_PSW_V, r1, 0x80000000);
+ tcg_gen_shli_i32(cpu_PSW_V, cpu_PSW_V, 31);
/* calc SV bit */
- tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
+ tcg_gen_or_i32(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* Calc AV bit */
- tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
- tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
+ tcg_gen_add_i32(cpu_PSW_AV, ret, ret);
+ tcg_gen_xor_i32(cpu_PSW_AV, ret, cpu_PSW_AV);
/* calc SAV bit */
- tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
+ tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
}
static inline void gen_absdif(TCGv ret, TCGv r1, TCGv r2)
@@ -2130,25 +2130,25 @@ static inline void gen_absdif(TCGv ret, TCGv r1, TCGv r2)
TCGv temp = tcg_temp_new_i32();
TCGv result = tcg_temp_new_i32();
- tcg_gen_sub_tl(result, r1, r2);
- tcg_gen_sub_tl(temp, r2, r1);
- tcg_gen_movcond_tl(TCG_COND_GT, result, r1, r2, result, temp);
+ tcg_gen_sub_i32(result, r1, r2);
+ tcg_gen_sub_i32(temp, r2, r1);
+ tcg_gen_movcond_i32(TCG_COND_GT, result, r1, r2, result, temp);
/* calc V bit */
- tcg_gen_xor_tl(cpu_PSW_V, result, r1);
- tcg_gen_xor_tl(temp, result, r2);
- tcg_gen_movcond_tl(TCG_COND_GT, cpu_PSW_V, r1, r2, cpu_PSW_V, temp);
- tcg_gen_xor_tl(temp, r1, r2);
- tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
+ tcg_gen_xor_i32(cpu_PSW_V, result, r1);
+ tcg_gen_xor_i32(temp, result, r2);
+ tcg_gen_movcond_i32(TCG_COND_GT, cpu_PSW_V, r1, r2, cpu_PSW_V, temp);
+ tcg_gen_xor_i32(temp, r1, r2);
+ tcg_gen_and_i32(cpu_PSW_V, cpu_PSW_V, temp);
/* calc SV bit */
- tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
+ tcg_gen_or_i32(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* Calc AV bit */
- tcg_gen_add_tl(cpu_PSW_AV, result, result);
- tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
+ tcg_gen_add_i32(cpu_PSW_AV, result, result);
+ tcg_gen_xor_i32(cpu_PSW_AV, result, cpu_PSW_AV);
/* calc SAV bit */
- tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
+ tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
/* write back result */
- tcg_gen_mov_tl(ret, result);
+ tcg_gen_mov_i32(ret, result);
}
static inline void gen_absdifi(TCGv ret, TCGv r1, int32_t con)
@@ -2168,19 +2168,19 @@ static inline void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2)
TCGv high = tcg_temp_new();
TCGv low = tcg_temp_new();
- tcg_gen_muls2_tl(low, high, r1, r2);
- tcg_gen_mov_tl(ret, low);
+ tcg_gen_muls2_i32(low, high, r1, r2);
+ tcg_gen_mov_i32(ret, low);
/* calc V bit */
- tcg_gen_sari_tl(low, low, 31);
- tcg_gen_setcond_tl(TCG_COND_NE, cpu_PSW_V, high, low);
- tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
+ tcg_gen_sari_i32(low, low, 31);
+ tcg_gen_setcond_i32(TCG_COND_NE, cpu_PSW_V, high, low);
+ tcg_gen_shli_i32(cpu_PSW_V, cpu_PSW_V, 31);
/* calc SV bit */
- tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
+ tcg_gen_or_i32(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* Calc AV bit */
- tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
- tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
+ tcg_gen_add_i32(cpu_PSW_AV, ret, ret);
+ tcg_gen_xor_i32(cpu_PSW_AV, ret, cpu_PSW_AV);
/* calc SAV bit */
- tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
+ tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
}
static inline void gen_muli_i32s(TCGv ret, TCGv r1, int32_t con)
@@ -2191,16 +2191,16 @@ static inline void gen_muli_i32s(TCGv ret, TCGv r1, int32_t con)
static inline void gen_mul_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2)
{
- tcg_gen_muls2_tl(ret_low, ret_high, r1, r2);
+ tcg_gen_muls2_i32(ret_low, ret_high, r1, r2);
/* clear V bit */
- tcg_gen_movi_tl(cpu_PSW_V, 0);
+ tcg_gen_movi_i32(cpu_PSW_V, 0);
/* calc SV bit */
- tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
+ tcg_gen_or_i32(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* Calc AV bit */
- tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
- tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
+ tcg_gen_add_i32(cpu_PSW_AV, ret_high, ret_high);
+ tcg_gen_xor_i32(cpu_PSW_AV, ret_high, cpu_PSW_AV);
/* calc SAV bit */
- tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
+ tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
}
static inline void gen_muli_i64s(TCGv ret_low, TCGv ret_high, TCGv r1,
@@ -2212,16 +2212,16 @@ static inline void gen_muli_i64s(TCGv ret_low, TCGv ret_high, TCGv r1,
static inline void gen_mul_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2)
{
- tcg_gen_mulu2_tl(ret_low, ret_high, r1, r2);
+ tcg_gen_mulu2_i32(ret_low, ret_high, r1, r2);
/* clear V bit */
- tcg_gen_movi_tl(cpu_PSW_V, 0);
+ tcg_gen_movi_i32(cpu_PSW_V, 0);
/* calc SV bit */
- tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
+ tcg_gen_or_i32(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* Calc AV bit */
- tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
- tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
+ tcg_gen_add_i32(cpu_PSW_AV, ret_high, ret_high);
+ tcg_gen_xor_i32(cpu_PSW_AV, ret_high, cpu_PSW_AV);
/* calc SAV bit */
- tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
+ tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
}
static inline void gen_muli_i64u(TCGv ret_low, TCGv ret_high, TCGv r1,
@@ -2264,7 +2264,7 @@ gen_mul_q(TCGv rl, TCGv rh, TCGv arg1, TCGv arg2, uint32_t n, uint32_t up_shift)
if (n == 0) {
if (up_shift == 32) {
- tcg_gen_muls2_tl(rh, rl, arg1, arg2);
+ tcg_gen_muls2_i32(rh, rl, arg1, arg2);
} else if (up_shift == 16) {
tcg_gen_ext_i32_i64(temp_64, arg1);
tcg_gen_ext_i32_i64(temp2_64, arg2);
@@ -2273,10 +2273,10 @@ gen_mul_q(TCGv rl, TCGv rh, TCGv arg1, TCGv arg2, uint32_t n, uint32_t up_shift)
tcg_gen_shri_i64(temp_64, temp_64, up_shift);
tcg_gen_extr_i64_i32(rl, rh, temp_64);
} else {
- tcg_gen_muls2_tl(rl, rh, arg1, arg2);
+ tcg_gen_muls2_i32(rl, rh, arg1, arg2);
}
/* reset v bit */
- tcg_gen_movi_tl(cpu_PSW_V, 0);
+ tcg_gen_movi_i32(cpu_PSW_V, 0);
} else { /* n is expected to be 1 */
tcg_gen_ext_i32_i64(temp_64, arg1);
tcg_gen_ext_i32_i64(temp2_64, arg2);
@@ -2291,26 +2291,26 @@ gen_mul_q(TCGv rl, TCGv rh, TCGv arg1, TCGv arg2, uint32_t n, uint32_t up_shift)
tcg_gen_extr_i64_i32(rl, rh, temp_64);
/* overflow only occurs if r1 = r2 = 0x8000 */
if (up_shift == 0) {/* result is 64 bit */
- tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rh,
+ tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_PSW_V, rh,
0x80000000);
} else { /* result is 32 bit */
- tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rl,
+ tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_PSW_V, rl,
0x80000000);
}
- tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
+ tcg_gen_shli_i32(cpu_PSW_V, cpu_PSW_V, 31);
/* calc sv overflow bit */
- tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
+ tcg_gen_or_i32(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
}
/* calc av overflow bit */
if (up_shift == 0) {
- tcg_gen_add_tl(cpu_PSW_AV, rh, rh);
- tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV);
+ tcg_gen_add_i32(cpu_PSW_AV, rh, rh);
+ tcg_gen_xor_i32(cpu_PSW_AV, rh, cpu_PSW_AV);
} else {
- tcg_gen_add_tl(cpu_PSW_AV, rl, rl);
- tcg_gen_xor_tl(cpu_PSW_AV, rl, cpu_PSW_AV);
+ tcg_gen_add_i32(cpu_PSW_AV, rl, rl);
+ tcg_gen_xor_i32(cpu_PSW_AV, rl, cpu_PSW_AV);
}
/* calc sav overflow bit */
- tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
+ tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
}
static void
@@ -2318,47 +2318,47 @@ gen_mul_q_16(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n)
{
TCGv temp = tcg_temp_new();
if (n == 0) {
- tcg_gen_mul_tl(ret, arg1, arg2);
+ tcg_gen_mul_i32(ret, arg1, arg2);
} else { /* n is expected to be 1 */
- tcg_gen_mul_tl(ret, arg1, arg2);
- tcg_gen_shli_tl(ret, ret, 1);
+ tcg_gen_mul_i32(ret, arg1, arg2);
+ tcg_gen_shli_i32(ret, ret, 1);
/* catch special case r1 = r2 = 0x8000 */
- tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80000000);
- tcg_gen_sub_tl(ret, ret, temp);
+ tcg_gen_setcondi_i32(TCG_COND_EQ, temp, ret, 0x80000000);
+ tcg_gen_sub_i32(ret, ret, temp);
}
/* reset v bit */
- tcg_gen_movi_tl(cpu_PSW_V, 0);
+ tcg_gen_movi_i32(cpu_PSW_V, 0);
/* calc av overflow bit */
- tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
- tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
+ tcg_gen_add_i32(cpu_PSW_AV, ret, ret);
+ tcg_gen_xor_i32(cpu_PSW_AV, ret, cpu_PSW_AV);
/* calc sav overflow bit */
- tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
+ tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
}
static void gen_mulr_q(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n)
{
TCGv temp = tcg_temp_new();
if (n == 0) {
- tcg_gen_mul_tl(ret, arg1, arg2);
- tcg_gen_addi_tl(ret, ret, 0x8000);
+ tcg_gen_mul_i32(ret, arg1, arg2);
+ tcg_gen_addi_i32(ret, ret, 0x8000);
} else {
- tcg_gen_mul_tl(ret, arg1, arg2);
- tcg_gen_shli_tl(ret, ret, 1);
- tcg_gen_addi_tl(ret, ret, 0x8000);
+ tcg_gen_mul_i32(ret, arg1, arg2);
+ tcg_gen_shli_i32(ret, ret, 1);
+ tcg_gen_addi_i32(ret, ret, 0x8000);
/* catch special case r1 = r2 = 0x8000 */
- tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80008000);
- tcg_gen_muli_tl(temp, temp, 0x8001);
- tcg_gen_sub_tl(ret, ret, temp);
+ tcg_gen_setcondi_i32(TCG_COND_EQ, temp, ret, 0x80008000);
+ tcg_gen_muli_i32(temp, temp, 0x8001);
+ tcg_gen_sub_i32(ret, ret, temp);
}
/* reset v bit */
- tcg_gen_movi_tl(cpu_PSW_V, 0);
+ tcg_gen_movi_i32(cpu_PSW_V, 0);
/* calc av overflow bit */
- tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
- tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
+ tcg_gen_add_i32(cpu_PSW_AV, ret, ret);
+ tcg_gen_xor_i32(cpu_PSW_AV, ret, cpu_PSW_AV);
/* calc sav overflow bit */
- tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
+ tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
/* cut halfword off */
- tcg_gen_andi_tl(ret, ret, 0xffff0000);
+ tcg_gen_andi_i32(ret, ret, 0xffff0000);
}
static inline void
@@ -2447,23 +2447,23 @@ gen_msubsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
static void gen_saturate(TCGv ret, TCGv arg, int32_t up, int32_t low)
{
- tcg_gen_smax_tl(ret, arg, tcg_constant_i32(low));
- tcg_gen_smin_tl(ret, ret, tcg_constant_i32(up));
+ tcg_gen_smax_i32(ret, arg, tcg_constant_i32(low));
+ tcg_gen_smin_i32(ret, ret, tcg_constant_i32(up));
}
static void gen_saturate_u(TCGv ret, TCGv arg, int32_t up)
{
- tcg_gen_umin_tl(ret, arg, tcg_constant_i32(up));
+ tcg_gen_umin_i32(ret, arg, tcg_constant_i32(up));
}
static void gen_shi(TCGv ret, TCGv r1, int32_t shift_count)
{
if (shift_count == -32) {
- tcg_gen_movi_tl(ret, 0);
+ tcg_gen_movi_i32(ret, 0);
} else if (shift_count >= 0) {
- tcg_gen_shli_tl(ret, r1, shift_count);
+ tcg_gen_shli_i32(ret, r1, shift_count);
} else {
- tcg_gen_shri_tl(ret, r1, -shift_count);
+ tcg_gen_shri_i32(ret, r1, -shift_count);
}
}
@@ -2472,16 +2472,16 @@ static void gen_sh_hi(TCGv ret, TCGv r1, int32_t shiftcount)
TCGv temp_low, temp_high;
if (shiftcount == -16) {
- tcg_gen_movi_tl(ret, 0);
+ tcg_gen_movi_i32(ret, 0);
} else {
temp_high = tcg_temp_new();
temp_low = tcg_temp_new();
- tcg_gen_andi_tl(temp_low, r1, 0xffff);
- tcg_gen_andi_tl(temp_high, r1, 0xffff0000);
+ tcg_gen_andi_i32(temp_low, r1, 0xffff);
+ tcg_gen_andi_i32(temp_high, r1, 0xffff0000);
gen_shi(temp_low, temp_low, shiftcount);
gen_shi(ret, temp_high, shiftcount);
- tcg_gen_deposit_tl(ret, ret, temp_low, 0, 16);
+ tcg_gen_deposit_i32(ret, ret, temp_low, 0, 16);
}
}
@@ -2493,16 +2493,16 @@ static void gen_shaci(TCGv ret, TCGv r1, int32_t shift_count)
if (shift_count == 0) {
/* Clear PSW.C and PSW.V */
- tcg_gen_movi_tl(cpu_PSW_C, 0);
- tcg_gen_mov_tl(cpu_PSW_V, cpu_PSW_C);
- tcg_gen_mov_tl(ret, r1);
+ tcg_gen_movi_i32(cpu_PSW_C, 0);
+ tcg_gen_mov_i32(cpu_PSW_V, cpu_PSW_C);
+ tcg_gen_mov_i32(ret, r1);
} else if (shift_count == -32) {
/* set PSW.C */
- tcg_gen_mov_tl(cpu_PSW_C, r1);
+ tcg_gen_mov_i32(cpu_PSW_C, r1);
/* fill ret completely with sign bit */
- tcg_gen_sari_tl(ret, r1, 31);
+ tcg_gen_sari_i32(ret, r1, 31);
/* clear PSW.V */
- tcg_gen_movi_tl(cpu_PSW_V, 0);
+ tcg_gen_movi_i32(cpu_PSW_V, 0);
} else if (shift_count > 0) {
TCGv t_max = tcg_constant_i32(0x7FFFFFFF >> shift_count);
TCGv t_min = tcg_constant_i32(((int32_t) -0x80000000) >> shift_count);
@@ -2510,30 +2510,30 @@ static void gen_shaci(TCGv ret, TCGv r1, int32_t shift_count)
/* calc carry */
msk_start = 32 - shift_count;
msk = ((1 << shift_count) - 1) << msk_start;
- tcg_gen_andi_tl(cpu_PSW_C, r1, msk);
+ tcg_gen_andi_i32(cpu_PSW_C, r1, msk);
/* calc v/sv bits */
- tcg_gen_setcond_tl(TCG_COND_GT, temp, r1, t_max);
- tcg_gen_setcond_tl(TCG_COND_LT, temp2, r1, t_min);
- tcg_gen_or_tl(cpu_PSW_V, temp, temp2);
- tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
+ tcg_gen_setcond_i32(TCG_COND_GT, temp, r1, t_max);
+ tcg_gen_setcond_i32(TCG_COND_LT, temp2, r1, t_min);
+ tcg_gen_or_i32(cpu_PSW_V, temp, temp2);
+ tcg_gen_shli_i32(cpu_PSW_V, cpu_PSW_V, 31);
/* calc sv */
- tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_V, cpu_PSW_SV);
+ tcg_gen_or_i32(cpu_PSW_SV, cpu_PSW_V, cpu_PSW_SV);
/* do shift */
- tcg_gen_shli_tl(ret, r1, shift_count);
+ tcg_gen_shli_i32(ret, r1, shift_count);
} else {
/* clear PSW.V */
- tcg_gen_movi_tl(cpu_PSW_V, 0);
+ tcg_gen_movi_i32(cpu_PSW_V, 0);
/* calc carry */
msk = (1 << -shift_count) - 1;
- tcg_gen_andi_tl(cpu_PSW_C, r1, msk);
+ tcg_gen_andi_i32(cpu_PSW_C, r1, msk);
/* do shift */
- tcg_gen_sari_tl(ret, r1, -shift_count);
+ tcg_gen_sari_i32(ret, r1, -shift_count);
}
/* calc av overflow bit */
- tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
- tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
+ tcg_gen_add_i32(cpu_PSW_AV, ret, ret);
+ tcg_gen_xor_i32(cpu_PSW_AV, ret, cpu_PSW_AV);
/* calc sav overflow bit */
- tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
+ tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
}
static void gen_shas(TCGv ret, TCGv r1, TCGv r2)
@@ -2552,23 +2552,23 @@ static void gen_sha_hi(TCGv ret, TCGv r1, int32_t shift_count)
TCGv low, high;
if (shift_count == 0) {
- tcg_gen_mov_tl(ret, r1);
+ tcg_gen_mov_i32(ret, r1);
} else if (shift_count > 0) {
low = tcg_temp_new();
high = tcg_temp_new();
- tcg_gen_andi_tl(high, r1, 0xffff0000);
- tcg_gen_shli_tl(low, r1, shift_count);
- tcg_gen_shli_tl(ret, high, shift_count);
- tcg_gen_deposit_tl(ret, ret, low, 0, 16);
+ tcg_gen_andi_i32(high, r1, 0xffff0000);
+ tcg_gen_shli_i32(low, r1, shift_count);
+ tcg_gen_shli_i32(ret, high, shift_count);
+ tcg_gen_deposit_i32(ret, ret, low, 0, 16);
} else {
low = tcg_temp_new();
high = tcg_temp_new();
- tcg_gen_ext16s_tl(low, r1);
- tcg_gen_sari_tl(low, low, -shift_count);
- tcg_gen_sari_tl(ret, r1, -shift_count);
- tcg_gen_deposit_tl(ret, ret, low, 0, 16);
+ tcg_gen_ext16s_i32(low, r1);
+ tcg_gen_sari_i32(low, low, -shift_count);
+ tcg_gen_sari_i32(ret, r1, -shift_count);
+ tcg_gen_deposit_i32(ret, ret, low, 0, 16);
}
}
@@ -2578,9 +2578,9 @@ static void gen_sh_cond(int cond, TCGv ret, TCGv r1, TCGv r2)
TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
- tcg_gen_shli_tl(temp, ret, 1);
- tcg_gen_setcond_tl(cond, temp2, r1, r2);
- tcg_gen_or_tl(ret, temp, temp2);
+ tcg_gen_shli_i32(temp, ret, 1);
+ tcg_gen_setcond_i32(cond, temp2, r1, r2);
+ tcg_gen_or_i32(ret, temp, temp2);
}
static void gen_sh_condi(int cond, TCGv ret, TCGv r1, int32_t con)
@@ -2626,13 +2626,13 @@ static inline void gen_bit_2op(TCGv ret, TCGv r1, TCGv r2,
temp1 = tcg_temp_new();
temp2 = tcg_temp_new();
- tcg_gen_shri_tl(temp2, r2, pos2);
- tcg_gen_shri_tl(temp1, r1, pos1);
+ tcg_gen_shri_i32(temp2, r2, pos2);
+ tcg_gen_shri_i32(temp1, r1, pos1);
(*op1)(temp1, temp1, temp2);
(*op2)(temp1 , ret, temp1);
- tcg_gen_deposit_tl(ret, ret, temp1, 0, 1);
+ tcg_gen_deposit_i32(ret, ret, temp1, 0, 1);
}
/* ret = r1[pos1] op1 r2[pos2]; */
@@ -2645,12 +2645,12 @@ static inline void gen_bit_1op(TCGv ret, TCGv r1, TCGv r2,
temp1 = tcg_temp_new();
temp2 = tcg_temp_new();
- tcg_gen_shri_tl(temp2, r2, pos2);
- tcg_gen_shri_tl(temp1, r1, pos1);
+ tcg_gen_shri_i32(temp2, r2, pos2);
+ tcg_gen_shri_i32(temp1, r1, pos1);
(*op1)(ret, temp1, temp2);
- tcg_gen_andi_tl(ret, ret, 0x1);
+ tcg_gen_andi_i32(ret, ret, 0x1);
}
static inline void gen_accumulating_cond(int cond, TCGv ret, TCGv r1, TCGv r2,
@@ -2659,13 +2659,13 @@ static inline void gen_accumulating_cond(int cond, TCGv ret, TCGv r1, TCGv r2,
TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
/* temp = (arg1 cond arg2 )*/
- tcg_gen_setcond_tl(cond, temp, r1, r2);
+ tcg_gen_setcond_i32(cond, temp, r1, r2);
/* temp2 = ret[0]*/
- tcg_gen_andi_tl(temp2, ret, 0x1);
+ tcg_gen_andi_i32(temp2, ret, 0x1);
/* temp = temp insn temp2 */
(*op)(temp, temp, temp2);
/* ret = {ret[31:1], temp} */
- tcg_gen_deposit_tl(ret, ret, temp, 0, 1);
+ tcg_gen_deposit_i32(ret, ret, temp, 0, 1);
}
static inline void
@@ -2684,25 +2684,25 @@ static inline void gen_eqany_bi(TCGv ret, TCGv r1, int32_t con)
TCGv b3 = tcg_temp_new();
/* byte 0 */
- tcg_gen_andi_tl(b0, r1, 0xff);
- tcg_gen_setcondi_tl(TCG_COND_EQ, b0, b0, con & 0xff);
+ tcg_gen_andi_i32(b0, r1, 0xff);
+ tcg_gen_setcondi_i32(TCG_COND_EQ, b0, b0, con & 0xff);
/* byte 1 */
- tcg_gen_andi_tl(b1, r1, 0xff00);
- tcg_gen_setcondi_tl(TCG_COND_EQ, b1, b1, con & 0xff00);
+ tcg_gen_andi_i32(b1, r1, 0xff00);
+ tcg_gen_setcondi_i32(TCG_COND_EQ, b1, b1, con & 0xff00);
/* byte 2 */
- tcg_gen_andi_tl(b2, r1, 0xff0000);
- tcg_gen_setcondi_tl(TCG_COND_EQ, b2, b2, con & 0xff0000);
+ tcg_gen_andi_i32(b2, r1, 0xff0000);
+ tcg_gen_setcondi_i32(TCG_COND_EQ, b2, b2, con & 0xff0000);
/* byte 3 */
- tcg_gen_andi_tl(b3, r1, 0xff000000);
- tcg_gen_setcondi_tl(TCG_COND_EQ, b3, b3, con & 0xff000000);
+ tcg_gen_andi_i32(b3, r1, 0xff000000);
+ tcg_gen_setcondi_i32(TCG_COND_EQ, b3, b3, con & 0xff000000);
/* combine them */
- tcg_gen_or_tl(ret, b0, b1);
- tcg_gen_or_tl(ret, ret, b2);
- tcg_gen_or_tl(ret, ret, b3);
+ tcg_gen_or_i32(ret, b0, b1);
+ tcg_gen_or_i32(ret, ret, b2);
+ tcg_gen_or_i32(ret, ret, b3);
}
static inline void gen_eqany_hi(TCGv ret, TCGv r1, int32_t con)
@@ -2711,15 +2711,15 @@ static inline void gen_eqany_hi(TCGv ret, TCGv r1, int32_t con)
TCGv h1 = tcg_temp_new();
/* halfword 0 */
- tcg_gen_andi_tl(h0, r1, 0xffff);
- tcg_gen_setcondi_tl(TCG_COND_EQ, h0, h0, con & 0xffff);
+ tcg_gen_andi_i32(h0, r1, 0xffff);
+ tcg_gen_setcondi_i32(TCG_COND_EQ, h0, h0, con & 0xffff);
/* halfword 1 */
- tcg_gen_andi_tl(h1, r1, 0xffff0000);
- tcg_gen_setcondi_tl(TCG_COND_EQ, h1, h1, con & 0xffff0000);
+ tcg_gen_andi_i32(h1, r1, 0xffff0000);
+ tcg_gen_setcondi_i32(TCG_COND_EQ, h1, h1, con & 0xffff0000);
/* combine them */
- tcg_gen_or_tl(ret, h0, h1);
+ tcg_gen_or_i32(ret, h0, h1);
}
/* mask = ((1 << width) -1) << pos;
@@ -2730,14 +2730,14 @@ static inline void gen_insert(TCGv ret, TCGv r1, TCGv r2, TCGv width, TCGv pos)
TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
- tcg_gen_shl_tl(mask, tcg_constant_tl(1), width);
- tcg_gen_subi_tl(mask, mask, 1);
- tcg_gen_shl_tl(mask, mask, pos);
+ tcg_gen_shl_i32(mask, tcg_constant_i32(1), width);
+ tcg_gen_subi_i32(mask, mask, 1);
+ tcg_gen_shl_i32(mask, mask, pos);
- tcg_gen_shl_tl(temp, r2, pos);
- tcg_gen_and_tl(temp, temp, mask);
- tcg_gen_andc_tl(temp2, r1, mask);
- tcg_gen_or_tl(ret, temp, temp2);
+ tcg_gen_shl_i32(temp, r2, pos);
+ tcg_gen_and_i32(temp, temp, mask);
+ tcg_gen_andc_i32(temp2, r1, mask);
+ tcg_gen_or_i32(ret, temp, temp2);
}
static inline void gen_bsplit(TCGv rl, TCGv rh, TCGv r1)
@@ -2786,35 +2786,35 @@ static void gen_calc_usb_mul_h(TCGv arg_low, TCGv arg_high)
{
TCGv temp = tcg_temp_new();
/* calc AV bit */
- tcg_gen_add_tl(temp, arg_low, arg_low);
- tcg_gen_xor_tl(temp, temp, arg_low);
- tcg_gen_add_tl(cpu_PSW_AV, arg_high, arg_high);
- tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, arg_high);
- tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp);
+ tcg_gen_add_i32(temp, arg_low, arg_low);
+ tcg_gen_xor_i32(temp, temp, arg_low);
+ tcg_gen_add_i32(cpu_PSW_AV, arg_high, arg_high);
+ tcg_gen_xor_i32(cpu_PSW_AV, cpu_PSW_AV, arg_high);
+ tcg_gen_or_i32(cpu_PSW_AV, cpu_PSW_AV, temp);
/* calc SAV bit */
- tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
- tcg_gen_movi_tl(cpu_PSW_V, 0);
+ tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
+ tcg_gen_movi_i32(cpu_PSW_V, 0);
}
static void gen_calc_usb_mulr_h(TCGv arg)
{
TCGv temp = tcg_temp_new();
/* calc AV bit */
- tcg_gen_add_tl(temp, arg, arg);
- tcg_gen_xor_tl(temp, temp, arg);
- tcg_gen_shli_tl(cpu_PSW_AV, temp, 16);
- tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp);
+ tcg_gen_add_i32(temp, arg, arg);
+ tcg_gen_xor_i32(temp, temp, arg);
+ tcg_gen_shli_i32(cpu_PSW_AV, temp, 16);
+ tcg_gen_or_i32(cpu_PSW_AV, cpu_PSW_AV, temp);
/* calc SAV bit */
- tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
+ tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
/* clear V bit */
- tcg_gen_movi_tl(cpu_PSW_V, 0);
+ tcg_gen_movi_i32(cpu_PSW_V, 0);
}
/* helpers for generating program flow micro-ops */
static inline void gen_save_pc(vaddr pc)
{
- tcg_gen_movi_tl(cpu_PC, pc);
+ tcg_gen_movi_i32(cpu_PC, pc);
}
static void gen_goto_tb(DisasContext *ctx, unsigned tb_slot_index, vaddr dest)
@@ -2844,7 +2844,7 @@ static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1,
TCGv r2, int16_t address)
{
TCGLabel *jumpLabel = gen_new_label();
- tcg_gen_brcond_tl(cond, r1, r2, jumpLabel);
+ tcg_gen_brcond_i32(cond, r1, r2, jumpLabel);
gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
@@ -2863,8 +2863,8 @@ static void gen_loop(DisasContext *ctx, int r1, int32_t offset)
{
TCGLabel *l1 = gen_new_label();
- tcg_gen_subi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], 1);
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr_a[r1], -1, l1);
+ tcg_gen_subi_i32(cpu_gpr_a[r1], cpu_gpr_a[r1], 1);
+ tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_gpr_a[r1], -1, l1);
gen_goto_tb(ctx, 1, ctx->base.pc_next + offset);
gen_set_label(l1);
gen_goto_tb(ctx, 0, ctx->pc_succ_insn);
@@ -2874,20 +2874,20 @@ static void gen_fcall_save_ctx(DisasContext *ctx)
{
TCGv temp = tcg_temp_new();
- tcg_gen_addi_tl(temp, cpu_gpr_a[10], -4);
- tcg_gen_qemu_st_tl(cpu_gpr_a[11], temp, ctx->mem_idx, MO_LESL);
- tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn);
- tcg_gen_mov_tl(cpu_gpr_a[10], temp);
+ tcg_gen_addi_i32(temp, cpu_gpr_a[10], -4);
+ tcg_gen_qemu_st_i32(cpu_gpr_a[11], temp, ctx->mem_idx, MO_LESL);
+ tcg_gen_movi_i32(cpu_gpr_a[11], ctx->pc_succ_insn);
+ tcg_gen_mov_i32(cpu_gpr_a[10], temp);
}
static void gen_fret(DisasContext *ctx)
{
TCGv temp = tcg_temp_new();
- tcg_gen_andi_tl(temp, cpu_gpr_a[11], ~0x1);
- tcg_gen_qemu_ld_tl(cpu_gpr_a[11], cpu_gpr_a[10], ctx->mem_idx, MO_LESL);
- tcg_gen_addi_tl(cpu_gpr_a[10], cpu_gpr_a[10], 4);
- tcg_gen_mov_tl(cpu_PC, temp);
+ tcg_gen_andi_i32(temp, cpu_gpr_a[11], ~0x1);
+ tcg_gen_qemu_ld_i32(cpu_gpr_a[11], cpu_gpr_a[10], ctx->mem_idx, MO_LESL);
+ tcg_gen_addi_i32(cpu_gpr_a[10], cpu_gpr_a[10], 4);
+ tcg_gen_mov_i32(cpu_PC, temp);
ctx->base.is_jmp = DISAS_EXIT;
}
@@ -2932,12 +2932,12 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
/* SBRN-format jumps */
case OPC1_16_SBRN_JZ_T:
temp = tcg_temp_new();
- tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
+ tcg_gen_andi_i32(temp, cpu_gpr_d[15], 0x1u << constant);
gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset);
break;
case OPC1_16_SBRN_JNZ_T:
temp = tcg_temp_new();
- tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
+ tcg_gen_andi_i32(temp, cpu_gpr_d[15], 0x1u << constant);
gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset);
break;
/* SBR-format jumps */
@@ -2986,7 +2986,7 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
break;
/* SR-format jumps */
case OPC1_16_SR_JI:
- tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], 0xfffffffe);
+ tcg_gen_andi_i32(cpu_PC, cpu_gpr_a[r1], 0xfffffffe);
ctx->base.is_jmp = DISAS_EXIT;
break;
case OPC2_32_SYS_RET:
@@ -3008,13 +3008,13 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
break;
case OPC1_32_B_JLA:
- tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn);
+ tcg_gen_movi_i32(cpu_gpr_a[11], ctx->pc_succ_insn);
/* fall through */
case OPC1_32_B_JA:
gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
break;
case OPC1_32_B_JL:
- tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn);
+ tcg_gen_movi_i32(cpu_gpr_a[11], ctx->pc_succ_insn);
gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2);
break;
/* BOL format */
@@ -3046,14 +3046,14 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
case OPCM_32_BRC_JNE:
temp = tcg_temp_new();
if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JNED) {
- tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
+ tcg_gen_mov_i32(temp, cpu_gpr_d[r1]);
/* subi is unconditional */
- tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
+ tcg_gen_subi_i32(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset);
} else {
- tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
+ tcg_gen_mov_i32(temp, cpu_gpr_d[r1]);
/* addi is unconditional */
- tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
+ tcg_gen_addi_i32(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset);
}
break;
@@ -3062,7 +3062,7 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
n = MASK_OP_BRN_N(ctx->opcode);
temp = tcg_temp_new();
- tcg_gen_andi_tl(temp, cpu_gpr_d[r1], (1 << n));
+ tcg_gen_andi_i32(temp, cpu_gpr_d[r1], (1 << n));
if (MASK_OP_BRN_OP2(ctx->opcode) == OPC2_32_BRN_JNZ_T) {
gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset);
@@ -3119,18 +3119,18 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
temp = tcg_temp_new();
temp2 = tcg_temp_new();
if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRR_JNED) {
- tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
+ tcg_gen_mov_i32(temp, cpu_gpr_d[r1]);
/* also save r2, in case of r1 == r2, so r2 is not decremented */
- tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]);
+ tcg_gen_mov_i32(temp2, cpu_gpr_d[r2]);
/* subi is unconditional */
- tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
+ tcg_gen_subi_i32(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset);
} else {
- tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
+ tcg_gen_mov_i32(temp, cpu_gpr_d[r1]);
/* also save r2, in case of r1 == r2, so r2 is not decremented */
- tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]);
+ tcg_gen_mov_i32(temp2, cpu_gpr_d[r2]);
/* addi is unconditional */
- tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
+ tcg_gen_addi_i32(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset);
}
break;
@@ -3171,7 +3171,7 @@ static void decode_src_opc(DisasContext *ctx, int op1)
gen_addi_d(cpu_gpr_d[15], cpu_gpr_d[r1], const4);
break;
case OPC1_16_SRC_ADD_A:
- tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], const4);
+ tcg_gen_addi_i32(cpu_gpr_a[r1], cpu_gpr_a[r1], const4);
break;
case OPC1_16_SRC_CADD:
gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const4, cpu_gpr_d[r1],
@@ -3182,37 +3182,37 @@ static void decode_src_opc(DisasContext *ctx, int op1)
cpu_gpr_d[15]);
break;
case OPC1_16_SRC_CMOV:
- temp = tcg_constant_tl(0);
- temp2 = tcg_constant_tl(const4);
- tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
+ temp = tcg_constant_i32(0);
+ temp2 = tcg_constant_i32(const4);
+ tcg_gen_movcond_i32(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
temp2, cpu_gpr_d[r1]);
break;
case OPC1_16_SRC_CMOVN:
- temp = tcg_constant_tl(0);
- temp2 = tcg_constant_tl(const4);
- tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
+ temp = tcg_constant_i32(0);
+ temp2 = tcg_constant_i32(const4);
+ tcg_gen_movcond_i32(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
temp2, cpu_gpr_d[r1]);
break;
case OPC1_16_SRC_EQ:
- tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
+ tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
const4);
break;
case OPC1_16_SRC_LT:
- tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
+ tcg_gen_setcondi_i32(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
const4);
break;
case OPC1_16_SRC_MOV:
- tcg_gen_movi_tl(cpu_gpr_d[r1], const4);
+ tcg_gen_movi_i32(cpu_gpr_d[r1], const4);
break;
case OPC1_16_SRC_MOV_A:
const4 = MASK_OP_SRC_CONST4(ctx->opcode);
- tcg_gen_movi_tl(cpu_gpr_a[r1], const4);
+ tcg_gen_movi_i32(cpu_gpr_a[r1], const4);
break;
case OPC1_16_SRC_MOV_E:
if (has_feature(ctx, TRICORE_FEATURE_16)) {
CHECK_REG_PAIR(r1);
- tcg_gen_movi_tl(cpu_gpr_d[r1], const4);
- tcg_gen_sari_tl(cpu_gpr_d[r1+1], cpu_gpr_d[r1], 31);
+ tcg_gen_movi_i32(cpu_gpr_d[r1], const4);
+ tcg_gen_sari_i32(cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], 31);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
@@ -3247,49 +3247,49 @@ static void decode_srr_opc(DisasContext *ctx, int op1)
gen_add_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC1_16_SRR_ADD_A:
- tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], cpu_gpr_a[r2]);
+ tcg_gen_add_i32(cpu_gpr_a[r1], cpu_gpr_a[r1], cpu_gpr_a[r2]);
break;
case OPC1_16_SRR_ADDS:
gen_adds(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC1_16_SRR_AND:
- tcg_gen_and_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ tcg_gen_and_i32(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC1_16_SRR_CMOV:
- temp = tcg_constant_tl(0);
- tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
+ temp = tcg_constant_i32(0);
+ tcg_gen_movcond_i32(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
cpu_gpr_d[r2], cpu_gpr_d[r1]);
break;
case OPC1_16_SRR_CMOVN:
- temp = tcg_constant_tl(0);
- tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
+ temp = tcg_constant_i32(0);
+ tcg_gen_movcond_i32(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
cpu_gpr_d[r2], cpu_gpr_d[r1]);
break;
case OPC1_16_SRR_EQ:
- tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
+ tcg_gen_setcond_i32(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC1_16_SRR_LT:
- tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
+ tcg_gen_setcond_i32(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC1_16_SRR_MOV:
- tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ tcg_gen_mov_i32(cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC1_16_SRR_MOV_A:
- tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_d[r2]);
+ tcg_gen_mov_i32(cpu_gpr_a[r1], cpu_gpr_d[r2]);
break;
case OPC1_16_SRR_MOV_AA:
- tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_a[r2]);
+ tcg_gen_mov_i32(cpu_gpr_a[r1], cpu_gpr_a[r2]);
break;
case OPC1_16_SRR_MOV_D:
- tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_a[r2]);
+ tcg_gen_mov_i32(cpu_gpr_d[r1], cpu_gpr_a[r2]);
break;
case OPC1_16_SRR_MUL:
gen_mul_i32s(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC1_16_SRR_OR:
- tcg_gen_or_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ tcg_gen_or_i32(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC1_16_SRR_SUB:
gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
@@ -3304,7 +3304,7 @@ static void decode_srr_opc(DisasContext *ctx, int op1)
gen_subs(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC1_16_SRR_XOR:
- tcg_gen_xor_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ tcg_gen_xor_i32(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
@@ -3320,32 +3320,32 @@ static void decode_ssr_opc(DisasContext *ctx, int op1)
switch (op1) {
case OPC1_16_SSR_ST_A:
- tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
+ tcg_gen_qemu_st_i32(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
break;
case OPC1_16_SSR_ST_A_POSTINC:
- tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
- tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
+ tcg_gen_qemu_st_i32(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
+ tcg_gen_addi_i32(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
break;
case OPC1_16_SSR_ST_B:
- tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
+ tcg_gen_qemu_st_i32(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
break;
case OPC1_16_SSR_ST_B_POSTINC:
- tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
- tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
+ tcg_gen_qemu_st_i32(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
+ tcg_gen_addi_i32(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
break;
case OPC1_16_SSR_ST_H:
- tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW);
+ tcg_gen_qemu_st_i32(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW);
break;
case OPC1_16_SSR_ST_H_POSTINC:
- tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW);
- tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
+ tcg_gen_qemu_st_i32(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW);
+ tcg_gen_addi_i32(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
break;
case OPC1_16_SSR_ST_W:
- tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
+ tcg_gen_qemu_st_i32(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
break;
case OPC1_16_SSR_ST_W_POSTINC:
- tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
- tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
+ tcg_gen_qemu_st_i32(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
+ tcg_gen_addi_i32(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
@@ -3360,7 +3360,7 @@ static void decode_sc_opc(DisasContext *ctx, int op1)
switch (op1) {
case OPC1_16_SC_AND:
- tcg_gen_andi_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);
+ tcg_gen_andi_i32(cpu_gpr_d[15], cpu_gpr_d[15], const16);
break;
case OPC1_16_SC_BISR:
if (ctx->priv == TRICORE_PRIV_SM) {
@@ -3376,10 +3376,10 @@ static void decode_sc_opc(DisasContext *ctx, int op1)
gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
break;
case OPC1_16_SC_MOV:
- tcg_gen_movi_tl(cpu_gpr_d[15], const16);
+ tcg_gen_movi_i32(cpu_gpr_d[15], const16);
break;
case OPC1_16_SC_OR:
- tcg_gen_ori_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);
+ tcg_gen_ori_i32(cpu_gpr_d[15], cpu_gpr_d[15], const16);
break;
case OPC1_16_SC_ST_A:
gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
@@ -3388,7 +3388,7 @@ static void decode_sc_opc(DisasContext *ctx, int op1)
gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
break;
case OPC1_16_SC_SUB_A:
- tcg_gen_subi_tl(cpu_gpr_a[10], cpu_gpr_a[10], const16);
+ tcg_gen_subi_i32(cpu_gpr_a[10], cpu_gpr_a[10], const16);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
@@ -3405,32 +3405,32 @@ static void decode_slr_opc(DisasContext *ctx, int op1)
switch (op1) {
/* SLR-format */
case OPC1_16_SLR_LD_A:
- tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
+ tcg_gen_qemu_ld_i32(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
break;
case OPC1_16_SLR_LD_A_POSTINC:
- tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
- tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
+ tcg_gen_qemu_ld_i32(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
+ tcg_gen_addi_i32(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
break;
case OPC1_16_SLR_LD_BU:
- tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
+ tcg_gen_qemu_ld_i32(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
break;
case OPC1_16_SLR_LD_BU_POSTINC:
- tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
- tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
+ tcg_gen_qemu_ld_i32(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
+ tcg_gen_addi_i32(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
break;
case OPC1_16_SLR_LD_H:
- tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
+ tcg_gen_qemu_ld_i32(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
break;
case OPC1_16_SLR_LD_H_POSTINC:
- tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
- tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
+ tcg_gen_qemu_ld_i32(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
+ tcg_gen_addi_i32(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
break;
case OPC1_16_SLR_LD_W:
- tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
+ tcg_gen_qemu_ld_i32(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
break;
case OPC1_16_SLR_LD_W_POSTINC:
- tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
- tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
+ tcg_gen_qemu_ld_i32(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
+ tcg_gen_addi_i32(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
@@ -3513,17 +3513,18 @@ static void decode_sr_accu(DisasContext *ctx)
switch (op2) {
case OPC2_16_SR_RSUB:
/* calc V bit -- overflow only if r1 = -0x80000000 */
- tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r1], -0x80000000);
- tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
+ tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_PSW_V,
+ cpu_gpr_d[r1], -0x80000000);
+ tcg_gen_shli_i32(cpu_PSW_V, cpu_PSW_V, 31);
/* calc SV bit */
- tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
+ tcg_gen_or_i32(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* sub */
- tcg_gen_neg_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]);
+ tcg_gen_neg_i32(cpu_gpr_d[r1], cpu_gpr_d[r1]);
/* calc av */
- tcg_gen_add_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_gpr_d[r1]);
- tcg_gen_xor_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_PSW_AV);
+ tcg_gen_add_i32(cpu_PSW_AV, cpu_gpr_d[r1], cpu_gpr_d[r1]);
+ tcg_gen_xor_i32(cpu_PSW_AV, cpu_gpr_d[r1], cpu_PSW_AV);
/* calc sav */
- tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
+ tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
break;
case OPC2_16_SR_SAT_B:
gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7f, -0x80);
@@ -3616,8 +3617,8 @@ static void decode_16Bit_opc(DisasContext *ctx)
r1 = MASK_OP_SRRS_S1D(ctx->opcode);
const16 = MASK_OP_SRRS_N(ctx->opcode);
temp = tcg_temp_new();
- tcg_gen_shli_tl(temp, cpu_gpr_d[15], const16);
- tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], temp);
+ tcg_gen_shli_i32(temp, cpu_gpr_d[15], const16);
+ tcg_gen_add_i32(cpu_gpr_a[r1], cpu_gpr_a[r2], temp);
break;
/* SLRO-format */
case OPC1_16_SLRO_LD_A:
@@ -3766,7 +3767,7 @@ static void decode_16Bit_opc(DisasContext *ctx)
break;
case OPC1_16_SR_NOT:
r1 = MASK_OP_SR_S1D(ctx->opcode);
- tcg_gen_not_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]);
+ tcg_gen_not_i32(cpu_gpr_d[r1], cpu_gpr_d[r1]);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
@@ -3793,18 +3794,18 @@ static void decode_abs_ldw(DisasContext *ctx)
switch (op2) {
case OPC2_32_ABS_LD_A:
- tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL);
+ tcg_gen_qemu_ld_i32(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL);
break;
case OPC2_32_ABS_LD_D:
CHECK_REG_PAIR(r1);
- gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
+ gen_ld_2regs_64(cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], temp, ctx);
break;
case OPC2_32_ABS_LD_DA:
CHECK_REG_PAIR(r1);
- gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
+ gen_ld_2regs_64(cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], temp, ctx);
break;
case OPC2_32_ABS_LD_W:
- tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL);
+ tcg_gen_qemu_ld_i32(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
@@ -3826,16 +3827,16 @@ static void decode_abs_ldb(DisasContext *ctx)
switch (op2) {
case OPC2_32_ABS_LD_B:
- tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_SB);
+ tcg_gen_qemu_ld_i32(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_SB);
break;
case OPC2_32_ABS_LD_BU:
- tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB);
+ tcg_gen_qemu_ld_i32(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB);
break;
case OPC2_32_ABS_LD_H:
- tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESW);
+ tcg_gen_qemu_ld_i32(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESW);
break;
case OPC2_32_ABS_LD_HU:
- tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
+ tcg_gen_qemu_ld_i32(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
@@ -3908,18 +3909,18 @@ static void decode_abs_store(DisasContext *ctx)
switch (op2) {
case OPC2_32_ABS_ST_A:
- tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL);
+ tcg_gen_qemu_st_i32(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL);
break;
case OPC2_32_ABS_ST_D:
CHECK_REG_PAIR(r1);
- gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
+ gen_st_2regs_64(cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], temp, ctx);
break;
case OPC2_32_ABS_ST_DA:
CHECK_REG_PAIR(r1);
- gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
+ gen_st_2regs_64(cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], temp, ctx);
break;
case OPC2_32_ABS_ST_W:
- tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL);
+ tcg_gen_qemu_st_i32(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
@@ -3941,10 +3942,10 @@ static void decode_abs_storeb_h(DisasContext *ctx)
switch (op2) {
case OPC2_32_ABS_ST_B:
- tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB);
+ tcg_gen_qemu_st_i32(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB);
break;
case OPC2_32_ABS_ST_H:
- tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
+ tcg_gen_qemu_st_i32(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
@@ -4043,11 +4044,11 @@ static void decode_bit_insert(DisasContext *ctx)
temp = tcg_temp_new();
- tcg_gen_shri_tl(temp, cpu_gpr_d[r2], pos2);
+ tcg_gen_shri_i32(temp, cpu_gpr_d[r2], pos2);
if (op2 == OPC2_32_BIT_INSN_T) {
- tcg_gen_not_tl(temp, temp);
+ tcg_gen_not_i32(temp, temp);
}
- tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, pos1, 1);
+ tcg_gen_deposit_i32(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, pos1, 1);
}
static void decode_bit_logical_t2(DisasContext *ctx)
@@ -4163,8 +4164,8 @@ static void decode_bit_sh_logic1(DisasContext *ctx)
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
- tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1);
- tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
+ tcg_gen_shli_i32(cpu_gpr_d[r3], cpu_gpr_d[r3], 1);
+ tcg_gen_add_i32(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
}
static void decode_bit_sh_logic2(DisasContext *ctx)
@@ -4203,8 +4204,8 @@ static void decode_bit_sh_logic2(DisasContext *ctx)
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
- tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1);
- tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
+ tcg_gen_shli_i32(cpu_gpr_d[r3], cpu_gpr_d[r3], 1);
+ tcg_gen_add_i32(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
}
/* BO-format */
@@ -4233,14 +4234,14 @@ static void decode_bo_addrmode_post_pre_base(DisasContext *ctx)
case OPC2_32_BO_CACHEA_I_POSTINC:
/* instruction to access the cache, but we still need to handle
the addressing mode */
- tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
+ tcg_gen_addi_i32(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_CACHEA_WI_PREINC:
case OPC2_32_BO_CACHEA_W_PREINC:
case OPC2_32_BO_CACHEA_I_PREINC:
/* instruction to access the cache, but we still need to handle
the addressing mode */
- tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
+ tcg_gen_addi_i32(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_CACHEI_WI_SHORTOFF:
case OPC2_32_BO_CACHEI_W_SHORTOFF:
@@ -4251,7 +4252,7 @@ static void decode_bo_addrmode_post_pre_base(DisasContext *ctx)
case OPC2_32_BO_CACHEI_W_POSTINC:
case OPC2_32_BO_CACHEI_WI_POSTINC:
if (has_feature(ctx, TRICORE_FEATURE_131)) {
- tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
+ tcg_gen_addi_i32(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
@@ -4259,7 +4260,7 @@ static void decode_bo_addrmode_post_pre_base(DisasContext *ctx)
case OPC2_32_BO_CACHEI_W_PREINC:
case OPC2_32_BO_CACHEI_WI_PREINC:
if (has_feature(ctx, TRICORE_FEATURE_131)) {
- tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
+ tcg_gen_addi_i32(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
@@ -4268,9 +4269,9 @@ static void decode_bo_addrmode_post_pre_base(DisasContext *ctx)
gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL);
break;
case OPC2_32_BO_ST_A_POSTINC:
- tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx,
+ tcg_gen_qemu_st_i32(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx,
MO_LESL);
- tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
+ tcg_gen_addi_i32(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_ST_A_PREINC:
gen_st_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL);
@@ -4279,82 +4280,82 @@ static void decode_bo_addrmode_post_pre_base(DisasContext *ctx)
gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
break;
case OPC2_32_BO_ST_B_POSTINC:
- tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
+ tcg_gen_qemu_st_i32(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
MO_UB);
- tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
+ tcg_gen_addi_i32(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_ST_B_PREINC:
gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
break;
case OPC2_32_BO_ST_D_SHORTOFF:
CHECK_REG_PAIR(r1);
- gen_offset_st_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2],
+ gen_offset_st_2regs(cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], cpu_gpr_a[r2],
off10, ctx);
break;
case OPC2_32_BO_ST_D_POSTINC:
CHECK_REG_PAIR(r1);
- gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx);
- tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
+ gen_st_2regs_64(cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx);
+ tcg_gen_addi_i32(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_ST_D_PREINC:
CHECK_REG_PAIR(r1);
temp = tcg_temp_new();
- tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
- gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
- tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
+ tcg_gen_addi_i32(temp, cpu_gpr_a[r2], off10);
+ gen_st_2regs_64(cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], temp, ctx);
+ tcg_gen_mov_i32(cpu_gpr_a[r2], temp);
break;
case OPC2_32_BO_ST_DA_SHORTOFF:
CHECK_REG_PAIR(r1);
- gen_offset_st_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2],
+ gen_offset_st_2regs(cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], cpu_gpr_a[r2],
off10, ctx);
break;
case OPC2_32_BO_ST_DA_POSTINC:
CHECK_REG_PAIR(r1);
- gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx);
- tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
+ gen_st_2regs_64(cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx);
+ tcg_gen_addi_i32(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_ST_DA_PREINC:
CHECK_REG_PAIR(r1);
temp = tcg_temp_new();
- tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
- gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
- tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
+ tcg_gen_addi_i32(temp, cpu_gpr_a[r2], off10);
+ gen_st_2regs_64(cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], temp, ctx);
+ tcg_gen_mov_i32(cpu_gpr_a[r2], temp);
break;
case OPC2_32_BO_ST_H_SHORTOFF:
gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
break;
case OPC2_32_BO_ST_H_POSTINC:
- tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
+ tcg_gen_qemu_st_i32(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
MO_LEUW);
- tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
+ tcg_gen_addi_i32(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_ST_H_PREINC:
gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
break;
case OPC2_32_BO_ST_Q_SHORTOFF:
temp = tcg_temp_new();
- tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
+ tcg_gen_shri_i32(temp, cpu_gpr_d[r1], 16);
gen_offset_st(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW);
break;
case OPC2_32_BO_ST_Q_POSTINC:
temp = tcg_temp_new();
- tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
- tcg_gen_qemu_st_tl(temp, cpu_gpr_a[r2], ctx->mem_idx,
+ tcg_gen_shri_i32(temp, cpu_gpr_d[r1], 16);
+ tcg_gen_qemu_st_i32(temp, cpu_gpr_a[r2], ctx->mem_idx,
MO_LEUW);
- tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
+ tcg_gen_addi_i32(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_ST_Q_PREINC:
temp = tcg_temp_new();
- tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
+ tcg_gen_shri_i32(temp, cpu_gpr_d[r1], 16);
gen_st_preincr(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW);
break;
case OPC2_32_BO_ST_W_SHORTOFF:
gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
break;
case OPC2_32_BO_ST_W_POSTINC:
- tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
+ tcg_gen_qemu_st_i32(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
MO_LEUL);
- tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
+ tcg_gen_addi_i32(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_ST_W_PREINC:
gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
@@ -4380,91 +4381,91 @@ static void decode_bo_addrmode_bitreverse_circular(DisasContext *ctx)
temp2 = tcg_temp_new();
t_off10 = tcg_constant_i32(off10);
CHECK_REG_PAIR(r2);
- tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
- tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
+ tcg_gen_ext16u_i32(temp, cpu_gpr_a[r2 + 1]);
+ tcg_gen_add_i32(temp2, cpu_gpr_a[r2], temp);
switch (op2) {
case OPC2_32_BO_CACHEA_WI_BR:
case OPC2_32_BO_CACHEA_W_BR:
case OPC2_32_BO_CACHEA_I_BR:
- gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
+ gen_helper_br_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1]);
break;
case OPC2_32_BO_CACHEA_WI_CIRC:
case OPC2_32_BO_CACHEA_W_CIRC:
case OPC2_32_BO_CACHEA_I_CIRC:
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
+ gen_helper_circ_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1], t_off10);
break;
case OPC2_32_BO_ST_A_BR:
- tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
- gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
+ tcg_gen_qemu_st_i32(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
+ gen_helper_br_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1]);
break;
case OPC2_32_BO_ST_A_CIRC:
- tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
+ tcg_gen_qemu_st_i32(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
+ gen_helper_circ_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1], t_off10);
break;
case OPC2_32_BO_ST_B_BR:
- tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
- gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
+ tcg_gen_qemu_st_i32(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
+ gen_helper_br_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1]);
break;
case OPC2_32_BO_ST_B_CIRC:
- tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
+ tcg_gen_qemu_st_i32(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
+ gen_helper_circ_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1], t_off10);
break;
case OPC2_32_BO_ST_D_BR:
CHECK_REG_PAIR(r1);
- gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx);
- gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
+ gen_st_2regs_64(cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], temp2, ctx);
+ gen_helper_br_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1]);
break;
case OPC2_32_BO_ST_D_CIRC:
CHECK_REG_PAIR(r1);
- tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
- tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
- tcg_gen_addi_tl(temp, temp, 4);
- tcg_gen_rem_tl(temp, temp, temp2);
- tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
- tcg_gen_qemu_st_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
+ tcg_gen_qemu_st_i32(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
+ tcg_gen_shri_i32(temp2, cpu_gpr_a[r2 + 1], 16);
+ tcg_gen_addi_i32(temp, temp, 4);
+ tcg_gen_rem_i32(temp, temp, temp2);
+ tcg_gen_add_i32(temp2, cpu_gpr_a[r2], temp);
+ tcg_gen_qemu_st_i32(cpu_gpr_d[r1 + 1], temp2, ctx->mem_idx, MO_LEUL);
+ gen_helper_circ_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1], t_off10);
break;
case OPC2_32_BO_ST_DA_BR:
CHECK_REG_PAIR(r1);
- gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx);
- gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
+ gen_st_2regs_64(cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], temp2, ctx);
+ gen_helper_br_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1]);
break;
case OPC2_32_BO_ST_DA_CIRC:
CHECK_REG_PAIR(r1);
- tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
- tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
- tcg_gen_addi_tl(temp, temp, 4);
- tcg_gen_rem_tl(temp, temp, temp2);
- tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
- tcg_gen_qemu_st_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
+ tcg_gen_qemu_st_i32(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
+ tcg_gen_shri_i32(temp2, cpu_gpr_a[r2 + 1], 16);
+ tcg_gen_addi_i32(temp, temp, 4);
+ tcg_gen_rem_i32(temp, temp, temp2);
+ tcg_gen_add_i32(temp2, cpu_gpr_a[r2], temp);
+ tcg_gen_qemu_st_i32(cpu_gpr_a[r1 + 1], temp2, ctx->mem_idx, MO_LEUL);
+ gen_helper_circ_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1], t_off10);
break;
case OPC2_32_BO_ST_H_BR:
- tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
- gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
+ tcg_gen_qemu_st_i32(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
+ gen_helper_br_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1]);
break;
case OPC2_32_BO_ST_H_CIRC:
- tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
+ tcg_gen_qemu_st_i32(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
+ gen_helper_circ_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1], t_off10);
break;
case OPC2_32_BO_ST_Q_BR:
- tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
- tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW);
- gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
+ tcg_gen_shri_i32(temp, cpu_gpr_d[r1], 16);
+ tcg_gen_qemu_st_i32(temp, temp2, ctx->mem_idx, MO_LEUW);
+ gen_helper_br_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1]);
break;
case OPC2_32_BO_ST_Q_CIRC:
- tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
- tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
+ tcg_gen_shri_i32(temp, cpu_gpr_d[r1], 16);
+ tcg_gen_qemu_st_i32(temp, temp2, ctx->mem_idx, MO_LEUW);
+ gen_helper_circ_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1], t_off10);
break;
case OPC2_32_BO_ST_W_BR:
- tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
- gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
+ tcg_gen_qemu_st_i32(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
+ gen_helper_br_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1]);
break;
case OPC2_32_BO_ST_W_CIRC:
- tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
+ tcg_gen_qemu_st_i32(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
+ gen_helper_circ_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1], t_off10);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
@@ -4488,9 +4489,9 @@ static void decode_bo_addrmode_ld_post_pre_base(DisasContext *ctx)
gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL);
break;
case OPC2_32_BO_LD_A_POSTINC:
- tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx,
+ tcg_gen_qemu_ld_i32(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx,
MO_LEUL);
- tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
+ tcg_gen_addi_i32(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_LD_A_PREINC:
gen_ld_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL);
@@ -4499,9 +4500,9 @@ static void decode_bo_addrmode_ld_post_pre_base(DisasContext *ctx)
gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB);
break;
case OPC2_32_BO_LD_B_POSTINC:
- tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
+ tcg_gen_qemu_ld_i32(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
MO_SB);
- tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
+ tcg_gen_addi_i32(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_LD_B_PREINC:
gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB);
@@ -4510,54 +4511,54 @@ static void decode_bo_addrmode_ld_post_pre_base(DisasContext *ctx)
gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
break;
case OPC2_32_BO_LD_BU_POSTINC:
- tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
+ tcg_gen_qemu_ld_i32(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
MO_UB);
- tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
+ tcg_gen_addi_i32(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_LD_BU_PREINC:
gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
break;
case OPC2_32_BO_LD_D_SHORTOFF:
CHECK_REG_PAIR(r1);
- gen_offset_ld_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2],
+ gen_offset_ld_2regs(cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], cpu_gpr_a[r2],
off10, ctx);
break;
case OPC2_32_BO_LD_D_POSTINC:
CHECK_REG_PAIR(r1);
- gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx);
- tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
+ gen_ld_2regs_64(cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx);
+ tcg_gen_addi_i32(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_LD_D_PREINC:
CHECK_REG_PAIR(r1);
temp = tcg_temp_new();
- tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
- gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
- tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
+ tcg_gen_addi_i32(temp, cpu_gpr_a[r2], off10);
+ gen_ld_2regs_64(cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], temp, ctx);
+ tcg_gen_mov_i32(cpu_gpr_a[r2], temp);
break;
case OPC2_32_BO_LD_DA_SHORTOFF:
CHECK_REG_PAIR(r1);
- gen_offset_ld_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2],
+ gen_offset_ld_2regs(cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], cpu_gpr_a[r2],
off10, ctx);
break;
case OPC2_32_BO_LD_DA_POSTINC:
CHECK_REG_PAIR(r1);
- gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx);
- tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
+ gen_ld_2regs_64(cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx);
+ tcg_gen_addi_i32(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_LD_DA_PREINC:
CHECK_REG_PAIR(r1);
temp = tcg_temp_new();
- tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
- gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
- tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
+ tcg_gen_addi_i32(temp, cpu_gpr_a[r2], off10);
+ gen_ld_2regs_64(cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], temp, ctx);
+ tcg_gen_mov_i32(cpu_gpr_a[r2], temp);
break;
case OPC2_32_BO_LD_H_SHORTOFF:
gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW);
break;
case OPC2_32_BO_LD_H_POSTINC:
- tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
+ tcg_gen_qemu_ld_i32(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
MO_LESW);
- tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
+ tcg_gen_addi_i32(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_LD_H_PREINC:
gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW);
@@ -4566,34 +4567,34 @@ static void decode_bo_addrmode_ld_post_pre_base(DisasContext *ctx)
gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
break;
case OPC2_32_BO_LD_HU_POSTINC:
- tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
+ tcg_gen_qemu_ld_i32(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
MO_LEUW);
- tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
+ tcg_gen_addi_i32(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_LD_HU_PREINC:
gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
break;
case OPC2_32_BO_LD_Q_SHORTOFF:
gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
- tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
+ tcg_gen_shli_i32(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
break;
case OPC2_32_BO_LD_Q_POSTINC:
- tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
+ tcg_gen_qemu_ld_i32(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
MO_LEUW);
- tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
- tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
+ tcg_gen_shli_i32(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
+ tcg_gen_addi_i32(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_LD_Q_PREINC:
gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
- tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
+ tcg_gen_shli_i32(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
break;
case OPC2_32_BO_LD_W_SHORTOFF:
gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
break;
case OPC2_32_BO_LD_W_POSTINC:
- tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
+ tcg_gen_qemu_ld_i32(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
MO_LEUL);
- tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
+ tcg_gen_addi_i32(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_LD_W_PREINC:
gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
@@ -4619,98 +4620,98 @@ static void decode_bo_addrmode_ld_bitreverse_circular(DisasContext *ctx)
temp2 = tcg_temp_new();
t_off10 = tcg_constant_i32(off10);
CHECK_REG_PAIR(r2);
- tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
- tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
+ tcg_gen_ext16u_i32(temp, cpu_gpr_a[r2 + 1]);
+ tcg_gen_add_i32(temp2, cpu_gpr_a[r2], temp);
switch (op2) {
case OPC2_32_BO_LD_A_BR:
- tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
- gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
+ tcg_gen_qemu_ld_i32(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
+ gen_helper_br_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1]);
break;
case OPC2_32_BO_LD_A_CIRC:
- tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
+ tcg_gen_qemu_ld_i32(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
+ gen_helper_circ_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1], t_off10);
break;
case OPC2_32_BO_LD_B_BR:
- tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB);
- gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
+ tcg_gen_qemu_ld_i32(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB);
+ gen_helper_br_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1]);
break;
case OPC2_32_BO_LD_B_CIRC:
- tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
+ tcg_gen_qemu_ld_i32(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB);
+ gen_helper_circ_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1], t_off10);
break;
case OPC2_32_BO_LD_BU_BR:
- tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
- gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
+ tcg_gen_qemu_ld_i32(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
+ gen_helper_br_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1]);
break;
case OPC2_32_BO_LD_BU_CIRC:
- tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
+ tcg_gen_qemu_ld_i32(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
+ gen_helper_circ_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1], t_off10);
break;
case OPC2_32_BO_LD_D_BR:
CHECK_REG_PAIR(r1);
- gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx);
- gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
+ gen_ld_2regs_64(cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], temp2, ctx);
+ gen_helper_br_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1]);
break;
case OPC2_32_BO_LD_D_CIRC:
CHECK_REG_PAIR(r1);
- tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
- tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
- tcg_gen_addi_tl(temp, temp, 4);
- tcg_gen_rem_tl(temp, temp, temp2);
- tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
- tcg_gen_qemu_ld_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
+ tcg_gen_qemu_ld_i32(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
+ tcg_gen_shri_i32(temp2, cpu_gpr_a[r2 + 1], 16);
+ tcg_gen_addi_i32(temp, temp, 4);
+ tcg_gen_rem_i32(temp, temp, temp2);
+ tcg_gen_add_i32(temp2, cpu_gpr_a[r2], temp);
+ tcg_gen_qemu_ld_i32(cpu_gpr_d[r1 + 1], temp2, ctx->mem_idx, MO_LEUL);
+ gen_helper_circ_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1], t_off10);
break;
case OPC2_32_BO_LD_DA_BR:
CHECK_REG_PAIR(r1);
- gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx);
- gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
+ gen_ld_2regs_64(cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], temp2, ctx);
+ gen_helper_br_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1]);
break;
case OPC2_32_BO_LD_DA_CIRC:
CHECK_REG_PAIR(r1);
- tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
- tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
- tcg_gen_addi_tl(temp, temp, 4);
- tcg_gen_rem_tl(temp, temp, temp2);
- tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
- tcg_gen_qemu_ld_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
+ tcg_gen_qemu_ld_i32(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
+ tcg_gen_shri_i32(temp2, cpu_gpr_a[r2 + 1], 16);
+ tcg_gen_addi_i32(temp, temp, 4);
+ tcg_gen_rem_i32(temp, temp, temp2);
+ tcg_gen_add_i32(temp2, cpu_gpr_a[r2], temp);
+ tcg_gen_qemu_ld_i32(cpu_gpr_a[r1 + 1], temp2, ctx->mem_idx, MO_LEUL);
+ gen_helper_circ_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1], t_off10);
break;
case OPC2_32_BO_LD_H_BR:
- tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW);
- gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
+ tcg_gen_qemu_ld_i32(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW);
+ gen_helper_br_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1]);
break;
case OPC2_32_BO_LD_H_CIRC:
- tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
+ tcg_gen_qemu_ld_i32(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW);
+ gen_helper_circ_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1], t_off10);
break;
case OPC2_32_BO_LD_HU_BR:
- tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
- gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
+ tcg_gen_qemu_ld_i32(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
+ gen_helper_br_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1]);
break;
case OPC2_32_BO_LD_HU_CIRC:
- tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
+ tcg_gen_qemu_ld_i32(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
+ gen_helper_circ_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1], t_off10);
break;
case OPC2_32_BO_LD_Q_BR:
- tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
- tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
- gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
+ tcg_gen_qemu_ld_i32(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
+ tcg_gen_shli_i32(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
+ gen_helper_br_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1]);
break;
case OPC2_32_BO_LD_Q_CIRC:
- tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
- tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
+ tcg_gen_qemu_ld_i32(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
+ tcg_gen_shli_i32(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
+ gen_helper_circ_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1], t_off10);
break;
case OPC2_32_BO_LD_W_BR:
- tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
- gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
+ tcg_gen_qemu_ld_i32(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
+ gen_helper_br_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1]);
break;
case OPC2_32_BO_LD_W_CIRC:
- tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
+ tcg_gen_qemu_ld_i32(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
+ gen_helper_circ_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1], t_off10);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
@@ -4735,70 +4736,70 @@ static void decode_bo_addrmode_stctx_post_pre_base(DisasContext *ctx)
switch (op2) {
case OPC2_32_BO_LDLCX_SHORTOFF:
- tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
+ tcg_gen_addi_i32(temp, cpu_gpr_a[r2], off10);
gen_helper_ldlcx(tcg_env, temp);
break;
case OPC2_32_BO_LDMST_SHORTOFF:
- tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
+ tcg_gen_addi_i32(temp, cpu_gpr_a[r2], off10);
gen_ldmst(ctx, r1, temp);
break;
case OPC2_32_BO_LDMST_POSTINC:
gen_ldmst(ctx, r1, cpu_gpr_a[r2]);
- tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
+ tcg_gen_addi_i32(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_LDMST_PREINC:
- tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
+ tcg_gen_addi_i32(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
gen_ldmst(ctx, r1, cpu_gpr_a[r2]);
break;
case OPC2_32_BO_LDUCX_SHORTOFF:
- tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
+ tcg_gen_addi_i32(temp, cpu_gpr_a[r2], off10);
gen_helper_lducx(tcg_env, temp);
break;
case OPC2_32_BO_LEA_SHORTOFF:
- tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], off10);
+ tcg_gen_addi_i32(cpu_gpr_a[r1], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_STLCX_SHORTOFF:
- tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
+ tcg_gen_addi_i32(temp, cpu_gpr_a[r2], off10);
gen_helper_stlcx(tcg_env, temp);
break;
case OPC2_32_BO_STUCX_SHORTOFF:
- tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
+ tcg_gen_addi_i32(temp, cpu_gpr_a[r2], off10);
gen_helper_stucx(tcg_env, temp);
break;
case OPC2_32_BO_SWAP_W_SHORTOFF:
- tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
+ tcg_gen_addi_i32(temp, cpu_gpr_a[r2], off10);
gen_swap(ctx, r1, temp);
break;
case OPC2_32_BO_SWAP_W_POSTINC:
gen_swap(ctx, r1, cpu_gpr_a[r2]);
- tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
+ tcg_gen_addi_i32(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_SWAP_W_PREINC:
- tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
+ tcg_gen_addi_i32(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
gen_swap(ctx, r1, cpu_gpr_a[r2]);
break;
case OPC2_32_BO_CMPSWAP_W_SHORTOFF:
- tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
+ tcg_gen_addi_i32(temp, cpu_gpr_a[r2], off10);
gen_cmpswap(ctx, r1, temp);
break;
case OPC2_32_BO_CMPSWAP_W_POSTINC:
gen_cmpswap(ctx, r1, cpu_gpr_a[r2]);
- tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
+ tcg_gen_addi_i32(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_CMPSWAP_W_PREINC:
- tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
+ tcg_gen_addi_i32(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
gen_cmpswap(ctx, r1, cpu_gpr_a[r2]);
break;
case OPC2_32_BO_SWAPMSK_W_SHORTOFF:
- tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
+ tcg_gen_addi_i32(temp, cpu_gpr_a[r2], off10);
gen_swapmsk(ctx, r1, temp);
break;
case OPC2_32_BO_SWAPMSK_W_POSTINC:
gen_swapmsk(ctx, r1, cpu_gpr_a[r2]);
- tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
+ tcg_gen_addi_i32(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_SWAPMSK_W_PREINC:
- tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
+ tcg_gen_addi_i32(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
gen_swapmsk(ctx, r1, cpu_gpr_a[r2]);
break;
default:
@@ -4822,41 +4823,41 @@ static void decode_bo_addrmode_ldmst_bitreverse_circular(DisasContext *ctx)
temp2 = tcg_temp_new();
t_off10 = tcg_constant_i32(off10);
CHECK_REG_PAIR(r2);
- tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
- tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
+ tcg_gen_ext16u_i32(temp, cpu_gpr_a[r2 + 1]);
+ tcg_gen_add_i32(temp2, cpu_gpr_a[r2], temp);
switch (op2) {
case OPC2_32_BO_LDMST_BR:
gen_ldmst(ctx, r1, temp2);
- gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
+ gen_helper_br_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1]);
break;
case OPC2_32_BO_LDMST_CIRC:
gen_ldmst(ctx, r1, temp2);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
+ gen_helper_circ_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1], t_off10);
break;
case OPC2_32_BO_SWAP_W_BR:
gen_swap(ctx, r1, temp2);
- gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
+ gen_helper_br_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1]);
break;
case OPC2_32_BO_SWAP_W_CIRC:
gen_swap(ctx, r1, temp2);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
+ gen_helper_circ_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1], t_off10);
break;
case OPC2_32_BO_CMPSWAP_W_BR:
gen_cmpswap(ctx, r1, temp2);
- gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
+ gen_helper_br_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1]);
break;
case OPC2_32_BO_CMPSWAP_W_CIRC:
gen_cmpswap(ctx, r1, temp2);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
+ gen_helper_circ_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1], t_off10);
break;
case OPC2_32_BO_SWAPMSK_W_BR:
gen_swapmsk(ctx, r1, temp2);
- gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
+ gen_helper_br_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1]);
break;
case OPC2_32_BO_SWAPMSK_W_CIRC:
gen_swapmsk(ctx, r1, temp2);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
+ gen_helper_circ_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1], t_off10);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
@@ -4876,16 +4877,16 @@ static void decode_bol_opc(DisasContext *ctx, int32_t op1)
switch (op1) {
case OPC1_32_BOL_LD_A_LONGOFF:
temp = tcg_temp_new();
- tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address);
- tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LEUL);
+ tcg_gen_addi_i32(temp, cpu_gpr_a[r2], address);
+ tcg_gen_qemu_ld_i32(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LEUL);
break;
case OPC1_32_BOL_LD_W_LONGOFF:
temp = tcg_temp_new();
- tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address);
- tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUL);
+ tcg_gen_addi_i32(temp, cpu_gpr_a[r2], address);
+ tcg_gen_qemu_ld_i32(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUL);
break;
case OPC1_32_BOL_LEA_LONGOFF:
- tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], address);
+ tcg_gen_addi_i32(cpu_gpr_a[r1], cpu_gpr_a[r2], address);
break;
case OPC1_32_BOL_ST_A_LONGOFF:
if (has_feature(ctx, TRICORE_FEATURE_16)) {
@@ -4959,26 +4960,26 @@ static void decode_rc_logical_shift(DisasContext *ctx)
switch (op2) {
case OPC2_32_RC_AND:
- tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
+ tcg_gen_andi_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_ANDN:
- tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9);
+ tcg_gen_andi_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9);
break;
case OPC2_32_RC_NAND:
temp = tcg_temp_new();
- tcg_gen_movi_tl(temp, const9);
- tcg_gen_nand_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp);
+ tcg_gen_movi_i32(temp, const9);
+ tcg_gen_nand_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], temp);
break;
case OPC2_32_RC_NOR:
temp = tcg_temp_new();
- tcg_gen_movi_tl(temp, const9);
- tcg_gen_nor_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp);
+ tcg_gen_movi_i32(temp, const9);
+ tcg_gen_nor_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], temp);
break;
case OPC2_32_RC_OR:
- tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
+ tcg_gen_ori_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_ORN:
- tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9);
+ tcg_gen_ori_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9);
break;
case OPC2_32_RC_SH:
const9 = sextract32(const9, 0, 6);
@@ -5000,11 +5001,11 @@ static void decode_rc_logical_shift(DisasContext *ctx)
gen_shasi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_XNOR:
- tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
- tcg_gen_not_tl(cpu_gpr_d[r2], cpu_gpr_d[r2]);
+ tcg_gen_xori_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
+ tcg_gen_not_i32(cpu_gpr_d[r2], cpu_gpr_d[r2]);
break;
case OPC2_32_RC_XOR:
- tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
+ tcg_gen_xori_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_SHUFFLE:
if (has_feature(ctx, TRICORE_FEATURE_162)) {
@@ -5084,7 +5085,7 @@ static void decode_rc_accumulator(DisasContext *ctx)
const9, &tcg_gen_and_tl);
break;
case OPC2_32_RC_EQ:
- tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
+ tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_EQANY_B:
gen_eqany_bi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
@@ -5093,41 +5094,41 @@ static void decode_rc_accumulator(DisasContext *ctx)
gen_eqany_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_GE:
- tcg_gen_setcondi_tl(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
+ tcg_gen_setcondi_i32(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_GE_U:
const9 = MASK_OP_RC_CONST9(ctx->opcode);
- tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
+ tcg_gen_setcondi_i32(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_LT:
- tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
+ tcg_gen_setcondi_i32(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_LT_U:
const9 = MASK_OP_RC_CONST9(ctx->opcode);
- tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
+ tcg_gen_setcondi_i32(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_MAX:
- tcg_gen_movi_tl(temp, const9);
- tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
+ tcg_gen_movi_i32(temp, const9);
+ tcg_gen_movcond_i32(TCG_COND_GT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
cpu_gpr_d[r1], temp);
break;
case OPC2_32_RC_MAX_U:
- tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode));
- tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
+ tcg_gen_movi_i32(temp, MASK_OP_RC_CONST9(ctx->opcode));
+ tcg_gen_movcond_i32(TCG_COND_GTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
cpu_gpr_d[r1], temp);
break;
case OPC2_32_RC_MIN:
- tcg_gen_movi_tl(temp, const9);
- tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
+ tcg_gen_movi_i32(temp, const9);
+ tcg_gen_movcond_i32(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
cpu_gpr_d[r1], temp);
break;
case OPC2_32_RC_MIN_U:
- tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode));
- tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
+ tcg_gen_movi_i32(temp, MASK_OP_RC_CONST9(ctx->opcode));
+ tcg_gen_movcond_i32(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
cpu_gpr_d[r1], temp);
break;
case OPC2_32_RC_NE:
- tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
+ tcg_gen_setcondi_i32(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_OR_EQ:
gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1],
@@ -5156,15 +5157,15 @@ static void decode_rc_accumulator(DisasContext *ctx)
const9, &tcg_gen_or_tl);
break;
case OPC2_32_RC_RSUB:
- tcg_gen_movi_tl(temp, const9);
+ tcg_gen_movi_i32(temp, const9);
gen_sub_d(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]);
break;
case OPC2_32_RC_RSUBS:
- tcg_gen_movi_tl(temp, const9);
+ tcg_gen_movi_i32(temp, const9);
gen_subs(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]);
break;
case OPC2_32_RC_RSUBS_U:
- tcg_gen_movi_tl(temp, const9);
+ tcg_gen_movi_i32(temp, const9);
gen_subsu(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]);
break;
case OPC2_32_RC_SH_EQ:
@@ -5260,7 +5261,7 @@ static void decode_rc_mul(DisasContext *ctx)
break;
case OPC2_32_RC_MUL_64:
CHECK_REG_PAIR(r2);
- gen_muli_i64s(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9);
+ gen_muli_i64s(cpu_gpr_d[r2], cpu_gpr_d[r2 + 1], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_MULS_32:
gen_mulsi_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
@@ -5268,7 +5269,7 @@ static void decode_rc_mul(DisasContext *ctx)
case OPC2_32_RC_MUL_U_64:
const9 = MASK_OP_RC_CONST9(ctx->opcode);
CHECK_REG_PAIR(r2);
- gen_muli_i64u(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9);
+ gen_muli_i64u(cpu_gpr_d[r2], cpu_gpr_d[r2 + 1], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_MULS_U_32:
const9 = MASK_OP_RC_CONST9(ctx->opcode);
@@ -5300,18 +5301,18 @@ static void decode_rcpw_insert(DisasContext *ctx)
CHECK_REG_PAIR(r2);
/* if pos + width > 32 undefined result */
if (pos + width <= 32) {
- tcg_gen_movi_tl(cpu_gpr_d[r2+1], ((1u << width) - 1) << pos);
- tcg_gen_movi_tl(cpu_gpr_d[r2], (const4 << pos));
+ tcg_gen_movi_i32(cpu_gpr_d[r2 + 1], ((1u << width) - 1) << pos);
+ tcg_gen_movi_i32(cpu_gpr_d[r2], (const4 << pos));
}
break;
case OPC2_32_RCPW_INSERT:
- /* tcg_gen_deposit_tl() does not handle the case of width = 0 */
+ /* tcg_gen_deposit_i32() does not handle the case of width = 0 */
if (width == 0) {
- tcg_gen_mov_tl(cpu_gpr_d[r2], cpu_gpr_d[r1]);
+ tcg_gen_mov_i32(cpu_gpr_d[r2], cpu_gpr_d[r1]);
/* if pos + width > 32 undefined result */
} else if (pos + width <= 32) {
temp = tcg_constant_i32(const4);
- tcg_gen_deposit_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, pos, width);
+ tcg_gen_deposit_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, pos, width);
}
break;
default:
@@ -5342,18 +5343,18 @@ static void decode_rcrw_insert(DisasContext *ctx)
switch (op2) {
case OPC2_32_RCRW_IMASK:
CHECK_REG_PAIR(r4);
- tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f);
- tcg_gen_movi_tl(temp2, (1 << width) - 1);
- tcg_gen_shl_tl(cpu_gpr_d[r4 + 1], temp2, temp);
- tcg_gen_movi_tl(temp2, const4);
- tcg_gen_shl_tl(cpu_gpr_d[r4], temp2, temp);
+ tcg_gen_andi_i32(temp, cpu_gpr_d[r3], 0x1f);
+ tcg_gen_movi_i32(temp2, (1 << width) - 1);
+ tcg_gen_shl_i32(cpu_gpr_d[r4 + 1], temp2, temp);
+ tcg_gen_movi_i32(temp2, const4);
+ tcg_gen_shl_i32(cpu_gpr_d[r4], temp2, temp);
break;
case OPC2_32_RCRW_INSERT:
temp3 = tcg_temp_new();
- tcg_gen_movi_tl(temp, width);
- tcg_gen_movi_tl(temp2, const4);
- tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f);
+ tcg_gen_movi_i32(temp, width);
+ tcg_gen_movi_i32(temp2, const4);
+ tcg_gen_andi_i32(temp3, cpu_gpr_d[r3], 0x1f);
gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], temp2, temp, temp3);
break;
default:
@@ -5389,13 +5390,13 @@ static void decode_rcr_cond_select(DisasContext *ctx)
case OPC2_32_RCR_SEL:
temp = tcg_constant_i32(0);
temp2 = tcg_constant_i32(const9);
- tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
+ tcg_gen_movcond_i32(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
cpu_gpr_d[r1], temp2);
break;
case OPC2_32_RCR_SELN:
temp = tcg_constant_i32(0);
temp2 = tcg_constant_i32(const9);
- tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
+ tcg_gen_movcond_i32(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
cpu_gpr_d[r1], temp2);
break;
default:
@@ -5423,8 +5424,8 @@ static void decode_rcr_madd(DisasContext *ctx)
case OPC2_32_RCR_MADD_64:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_maddi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
- cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
+ gen_maddi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r1],
+ cpu_gpr_d[r3], cpu_gpr_d[r3 + 1], const9);
break;
case OPC2_32_RCR_MADDS_32:
gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
@@ -5432,15 +5433,15 @@ static void decode_rcr_madd(DisasContext *ctx)
case OPC2_32_RCR_MADDS_64:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_maddsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
- cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
+ gen_maddsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r1],
+ cpu_gpr_d[r3], cpu_gpr_d[r3 + 1], const9);
break;
case OPC2_32_RCR_MADD_U_64:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
const9 = MASK_OP_RCR_CONST9(ctx->opcode);
- gen_maddui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
- cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
+ gen_maddui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r1],
+ cpu_gpr_d[r3], cpu_gpr_d[r3 + 1], const9);
break;
case OPC2_32_RCR_MADDS_U_32:
const9 = MASK_OP_RCR_CONST9(ctx->opcode);
@@ -5450,8 +5451,8 @@ static void decode_rcr_madd(DisasContext *ctx)
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
const9 = MASK_OP_RCR_CONST9(ctx->opcode);
- gen_maddsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
- cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
+ gen_maddsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r1],
+ cpu_gpr_d[r3], cpu_gpr_d[r3 + 1], const9);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
@@ -5478,8 +5479,8 @@ static void decode_rcr_msub(DisasContext *ctx)
case OPC2_32_RCR_MSUB_64:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_msubi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
- cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
+ gen_msubi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r1],
+ cpu_gpr_d[r3], cpu_gpr_d[r3 + 1], const9);
break;
case OPC2_32_RCR_MSUBS_32:
gen_msubsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
@@ -5487,15 +5488,15 @@ static void decode_rcr_msub(DisasContext *ctx)
case OPC2_32_RCR_MSUBS_64:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_msubsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
- cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
+ gen_msubsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r1],
+ cpu_gpr_d[r3], cpu_gpr_d[r3 + 1], const9);
break;
case OPC2_32_RCR_MSUB_U_64:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
const9 = MASK_OP_RCR_CONST9(ctx->opcode);
- gen_msubui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
- cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
+ gen_msubui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r1],
+ cpu_gpr_d[r3], cpu_gpr_d[r3 + 1], const9);
break;
case OPC2_32_RCR_MSUBS_U_32:
const9 = MASK_OP_RCR_CONST9(ctx->opcode);
@@ -5505,8 +5506,8 @@ static void decode_rcr_msub(DisasContext *ctx)
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
const9 = MASK_OP_RCR_CONST9(ctx->opcode);
- gen_msubsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
- cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
+ gen_msubsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r1],
+ cpu_gpr_d[r3], cpu_gpr_d[r3 + 1], const9);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
@@ -5533,33 +5534,33 @@ static void decode_rlc_opc(DisasContext *ctx,
gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16 << 16);
break;
case OPC1_32_RLC_ADDIH_A:
- tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r1], const16 << 16);
+ tcg_gen_addi_i32(cpu_gpr_a[r2], cpu_gpr_a[r1], const16 << 16);
break;
case OPC1_32_RLC_MFCR:
const16 = MASK_OP_RLC_CONST16(ctx->opcode);
gen_mfcr(ctx, cpu_gpr_d[r2], const16);
break;
case OPC1_32_RLC_MOV:
- tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
+ tcg_gen_movi_i32(cpu_gpr_d[r2], const16);
break;
case OPC1_32_RLC_MOV_64:
if (has_feature(ctx, TRICORE_FEATURE_16)) {
CHECK_REG_PAIR(r2);
- tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
- tcg_gen_movi_tl(cpu_gpr_d[r2+1], const16 >> 15);
+ tcg_gen_movi_i32(cpu_gpr_d[r2], const16);
+ tcg_gen_movi_i32(cpu_gpr_d[r2 + 1], const16 >> 15);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC1_32_RLC_MOV_U:
const16 = MASK_OP_RLC_CONST16(ctx->opcode);
- tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
+ tcg_gen_movi_i32(cpu_gpr_d[r2], const16);
break;
case OPC1_32_RLC_MOV_H:
- tcg_gen_movi_tl(cpu_gpr_d[r2], const16 << 16);
+ tcg_gen_movi_i32(cpu_gpr_d[r2], const16 << 16);
break;
case OPC1_32_RLC_MOVH_A:
- tcg_gen_movi_tl(cpu_gpr_a[r2], const16 << 16);
+ tcg_gen_movi_i32(cpu_gpr_a[r2], const16 << 16);
break;
case OPC1_32_RLC_MTCR:
const16 = MASK_OP_RLC_CONST16(ctx->opcode);
@@ -5673,7 +5674,7 @@ static void decode_rr_accumulator(DisasContext *ctx)
cpu_gpr_d[r2], &tcg_gen_and_tl);
break;
case OPC2_32_RR_EQ:
- tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
+ tcg_gen_setcond_i32(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC2_32_RR_EQ_B:
@@ -5683,7 +5684,7 @@ static void decode_rr_accumulator(DisasContext *ctx)
gen_helper_eq_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_EQ_W:
- tcg_gen_negsetcond_tl(TCG_COND_EQ, cpu_gpr_d[r3],
+ tcg_gen_negsetcond_i32(TCG_COND_EQ, cpu_gpr_d[r3],
cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_EQANY_B:
@@ -5693,19 +5694,19 @@ static void decode_rr_accumulator(DisasContext *ctx)
gen_helper_eqany_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_GE:
- tcg_gen_setcond_tl(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
+ tcg_gen_setcond_i32(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC2_32_RR_GE_U:
- tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
+ tcg_gen_setcond_i32(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC2_32_RR_LT:
- tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
+ tcg_gen_setcond_i32(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC2_32_RR_LT_U:
- tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
+ tcg_gen_setcond_i32(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC2_32_RR_LT_B:
@@ -5721,19 +5722,19 @@ static void decode_rr_accumulator(DisasContext *ctx)
gen_helper_lt_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_LT_W:
- tcg_gen_negsetcond_tl(TCG_COND_LT, cpu_gpr_d[r3],
+ tcg_gen_negsetcond_i32(TCG_COND_LT, cpu_gpr_d[r3],
cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_LT_WU:
- tcg_gen_negsetcond_tl(TCG_COND_LTU, cpu_gpr_d[r3],
+ tcg_gen_negsetcond_i32(TCG_COND_LTU, cpu_gpr_d[r3],
cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_MAX:
- tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r3], cpu_gpr_d[r1],
+ tcg_gen_movcond_i32(TCG_COND_GT, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_MAX_U:
- tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
+ tcg_gen_movcond_i32(TCG_COND_GTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_MAX_B:
@@ -5749,11 +5750,11 @@ static void decode_rr_accumulator(DisasContext *ctx)
gen_helper_max_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_MIN:
- tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
+ tcg_gen_movcond_i32(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_MIN_U:
- tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
+ tcg_gen_movcond_i32(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_MIN_B:
@@ -5769,16 +5770,16 @@ static void decode_rr_accumulator(DisasContext *ctx)
gen_helper_min_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_MOV:
- tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]);
+ tcg_gen_mov_i32(cpu_gpr_d[r3], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_MOV_64:
if (has_feature(ctx, TRICORE_FEATURE_16)) {
temp = tcg_temp_new();
CHECK_REG_PAIR(r3);
- tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
- tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]);
- tcg_gen_mov_tl(cpu_gpr_d[r3 + 1], temp);
+ tcg_gen_mov_i32(temp, cpu_gpr_d[r1]);
+ tcg_gen_mov_i32(cpu_gpr_d[r3], cpu_gpr_d[r2]);
+ tcg_gen_mov_i32(cpu_gpr_d[r3 + 1], temp);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
@@ -5786,14 +5787,14 @@ static void decode_rr_accumulator(DisasContext *ctx)
case OPC2_32_RR_MOVS_64:
if (has_feature(ctx, TRICORE_FEATURE_16)) {
CHECK_REG_PAIR(r3);
- tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]);
- tcg_gen_sari_tl(cpu_gpr_d[r3 + 1], cpu_gpr_d[r2], 31);
+ tcg_gen_mov_i32(cpu_gpr_d[r3], cpu_gpr_d[r2]);
+ tcg_gen_sari_i32(cpu_gpr_d[r3 + 1], cpu_gpr_d[r2], 31);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC2_32_RR_NE:
- tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
+ tcg_gen_setcond_i32(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC2_32_RR_OR_EQ:
@@ -5926,41 +5927,41 @@ static void decode_rr_logical_shift(DisasContext *ctx)
switch (op2) {
case OPC2_32_RR_AND:
- tcg_gen_and_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ tcg_gen_and_i32(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_ANDN:
- tcg_gen_andc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ tcg_gen_andc_i32(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_CLO:
- tcg_gen_not_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
- tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], TARGET_LONG_BITS);
+ tcg_gen_not_i32(cpu_gpr_d[r3], cpu_gpr_d[r1]);
+ tcg_gen_clzi_i32(cpu_gpr_d[r3], cpu_gpr_d[r3], TARGET_LONG_BITS);
break;
case OPC2_32_RR_CLO_H:
gen_helper_clo_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
break;
case OPC2_32_RR_CLS:
- tcg_gen_clrsb_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
+ tcg_gen_clrsb_i32(cpu_gpr_d[r3], cpu_gpr_d[r1]);
break;
case OPC2_32_RR_CLS_H:
gen_helper_cls_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
break;
case OPC2_32_RR_CLZ:
- tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], TARGET_LONG_BITS);
+ tcg_gen_clzi_i32(cpu_gpr_d[r3], cpu_gpr_d[r1], TARGET_LONG_BITS);
break;
case OPC2_32_RR_CLZ_H:
gen_helper_clz_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
break;
case OPC2_32_RR_NAND:
- tcg_gen_nand_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ tcg_gen_nand_i32(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_NOR:
- tcg_gen_nor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ tcg_gen_nor_i32(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_OR:
- tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ tcg_gen_or_i32(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_ORN:
- tcg_gen_orc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ tcg_gen_orc_i32(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_SH:
gen_helper_sh(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
@@ -5978,10 +5979,10 @@ static void decode_rr_logical_shift(DisasContext *ctx)
gen_shas(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_XNOR:
- tcg_gen_eqv_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ tcg_gen_eqv_i32(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_XOR:
- tcg_gen_xor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ tcg_gen_xor_i32(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
@@ -6002,52 +6003,52 @@ static void decode_rr_address(DisasContext *ctx)
switch (op2) {
case OPC2_32_RR_ADD_A:
- tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]);
+ tcg_gen_add_i32(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]);
break;
case OPC2_32_RR_ADDSC_A:
temp = tcg_temp_new();
- tcg_gen_shli_tl(temp, cpu_gpr_d[r1], n);
- tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r2], temp);
+ tcg_gen_shli_i32(temp, cpu_gpr_d[r1], n);
+ tcg_gen_add_i32(cpu_gpr_a[r3], cpu_gpr_a[r2], temp);
break;
case OPC2_32_RR_ADDSC_AT:
temp = tcg_temp_new();
- tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 3);
- tcg_gen_add_tl(temp, cpu_gpr_a[r2], temp);
- tcg_gen_andi_tl(cpu_gpr_a[r3], temp, 0xFFFFFFFC);
+ tcg_gen_sari_i32(temp, cpu_gpr_d[r1], 3);
+ tcg_gen_add_i32(temp, cpu_gpr_a[r2], temp);
+ tcg_gen_andi_i32(cpu_gpr_a[r3], temp, 0xFFFFFFFC);
break;
case OPC2_32_RR_EQ_A:
- tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1],
+ tcg_gen_setcond_i32(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1],
cpu_gpr_a[r2]);
break;
case OPC2_32_RR_EQZ:
- tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1], 0);
+ tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1], 0);
break;
case OPC2_32_RR_GE_A:
- tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_a[r1],
+ tcg_gen_setcond_i32(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_a[r1],
cpu_gpr_a[r2]);
break;
case OPC2_32_RR_LT_A:
- tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_a[r1],
+ tcg_gen_setcond_i32(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_a[r1],
cpu_gpr_a[r2]);
break;
case OPC2_32_RR_MOV_A:
- tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_d[r2]);
+ tcg_gen_mov_i32(cpu_gpr_a[r3], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_MOV_AA:
- tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_a[r2]);
+ tcg_gen_mov_i32(cpu_gpr_a[r3], cpu_gpr_a[r2]);
break;
case OPC2_32_RR_MOV_D:
- tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_a[r2]);
+ tcg_gen_mov_i32(cpu_gpr_d[r3], cpu_gpr_a[r2]);
break;
case OPC2_32_RR_NE_A:
- tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1],
+ tcg_gen_setcond_i32(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1],
cpu_gpr_a[r2]);
break;
case OPC2_32_RR_NEZ_A:
- tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1], 0);
+ tcg_gen_setcondi_i32(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1], 0);
break;
case OPC2_32_RR_SUB_A:
- tcg_gen_sub_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]);
+ tcg_gen_sub_i32(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
@@ -6064,19 +6065,19 @@ static void decode_rr_idirect(DisasContext *ctx)
switch (op2) {
case OPC2_32_RR_JI:
- tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
+ tcg_gen_andi_i32(cpu_PC, cpu_gpr_a[r1], ~0x1);
break;
case OPC2_32_RR_JLI:
- tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
- tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn);
+ tcg_gen_andi_i32(cpu_PC, cpu_gpr_a[r1], ~0x1);
+ tcg_gen_movi_i32(cpu_gpr_a[11], ctx->pc_succ_insn);
break;
case OPC2_32_RR_CALLI:
gen_helper_1arg(call, ctx->pc_succ_insn);
- tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
+ tcg_gen_andi_i32(cpu_PC, cpu_gpr_a[r1], ~0x1);
break;
case OPC2_32_RR_FCALLI:
gen_fcall_save_ctx(ctx);
- tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
+ tcg_gen_andi_i32(cpu_PC, cpu_gpr_a[r1], ~0x1);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
@@ -6103,11 +6104,11 @@ static void decode_rr_divide(DisasContext *ctx)
break;
case OPC2_32_RR_BSPLIT:
CHECK_REG_PAIR(r3);
- gen_bsplit(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
+ gen_bsplit(cpu_gpr_d[r3], cpu_gpr_d[r3 + 1], cpu_gpr_d[r1]);
break;
case OPC2_32_RR_DVINIT_B:
CHECK_REG_PAIR(r3);
- gen_dvinit_b(ctx, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
+ gen_dvinit_b(ctx, cpu_gpr_d[r3], cpu_gpr_d[r3 + 1], cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC2_32_RR_DVINIT_BU:
@@ -6115,28 +6116,28 @@ static void decode_rr_divide(DisasContext *ctx)
temp2 = tcg_temp_new();
temp3 = tcg_temp_new();
CHECK_REG_PAIR(r3);
- tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 8);
+ tcg_gen_shri_i32(temp3, cpu_gpr_d[r1], 8);
/* reset av */
- tcg_gen_movi_tl(cpu_PSW_AV, 0);
+ tcg_gen_movi_i32(cpu_PSW_AV, 0);
if (!has_feature(ctx, TRICORE_FEATURE_131)) {
- /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
- tcg_gen_abs_tl(temp, temp3);
- tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]);
- tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2);
+ /* overflow = (abs(D[r3 + 1]) >= abs(D[r2])) */
+ tcg_gen_abs_i32(temp, temp3);
+ tcg_gen_abs_i32(temp2, cpu_gpr_d[r2]);
+ tcg_gen_setcond_i32(TCG_COND_GE, cpu_PSW_V, temp, temp2);
} else {
/* overflow = (D[b] == 0) */
- tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0);
+ tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0);
}
- tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
+ tcg_gen_shli_i32(cpu_PSW_V, cpu_PSW_V, 31);
/* sv */
- tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
+ tcg_gen_or_i32(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* write result */
- tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 24);
- tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3);
+ tcg_gen_shli_i32(cpu_gpr_d[r3], cpu_gpr_d[r1], 24);
+ tcg_gen_mov_i32(cpu_gpr_d[r3 + 1], temp3);
break;
case OPC2_32_RR_DVINIT_H:
CHECK_REG_PAIR(r3);
- gen_dvinit_h(ctx, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
+ gen_dvinit_h(ctx, cpu_gpr_d[r3], cpu_gpr_d[r3 + 1], cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC2_32_RR_DVINIT_HU:
@@ -6144,24 +6145,24 @@ static void decode_rr_divide(DisasContext *ctx)
temp2 = tcg_temp_new();
temp3 = tcg_temp_new();
CHECK_REG_PAIR(r3);
- tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 16);
+ tcg_gen_shri_i32(temp3, cpu_gpr_d[r1], 16);
/* reset av */
- tcg_gen_movi_tl(cpu_PSW_AV, 0);
+ tcg_gen_movi_i32(cpu_PSW_AV, 0);
if (!has_feature(ctx, TRICORE_FEATURE_131)) {
- /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
- tcg_gen_abs_tl(temp, temp3);
- tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]);
- tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2);
+ /* overflow = (abs(D[r3 + 1]) >= abs(D[r2])) */
+ tcg_gen_abs_i32(temp, temp3);
+ tcg_gen_abs_i32(temp2, cpu_gpr_d[r2]);
+ tcg_gen_setcond_i32(TCG_COND_GE, cpu_PSW_V, temp, temp2);
} else {
/* overflow = (D[b] == 0) */
- tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0);
+ tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0);
}
- tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
+ tcg_gen_shli_i32(cpu_PSW_V, cpu_PSW_V, 31);
/* sv */
- tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
+ tcg_gen_or_i32(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* write result */
- tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 16);
- tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3);
+ tcg_gen_shli_i32(cpu_gpr_d[r3], cpu_gpr_d[r1], 16);
+ tcg_gen_mov_i32(cpu_gpr_d[r3 + 1], temp3);
break;
case OPC2_32_RR_DVINIT:
temp = tcg_temp_new();
@@ -6169,41 +6170,41 @@ static void decode_rr_divide(DisasContext *ctx)
CHECK_REG_PAIR(r3);
/* overflow = ((D[b] == 0) ||
((D[b] == 0xFFFFFFFF) && (D[a] == 0x80000000))) */
- tcg_gen_setcondi_tl(TCG_COND_EQ, temp, cpu_gpr_d[r2], 0xffffffff);
- tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r1], 0x80000000);
- tcg_gen_and_tl(temp, temp, temp2);
- tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r2], 0);
- tcg_gen_or_tl(cpu_PSW_V, temp, temp2);
- tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
+ tcg_gen_setcondi_i32(TCG_COND_EQ, temp, cpu_gpr_d[r2], 0xffffffff);
+ tcg_gen_setcondi_i32(TCG_COND_EQ, temp2, cpu_gpr_d[r1], 0x80000000);
+ tcg_gen_and_i32(temp, temp, temp2);
+ tcg_gen_setcondi_i32(TCG_COND_EQ, temp2, cpu_gpr_d[r2], 0);
+ tcg_gen_or_i32(cpu_PSW_V, temp, temp2);
+ tcg_gen_shli_i32(cpu_PSW_V, cpu_PSW_V, 31);
/* sv */
- tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
+ tcg_gen_or_i32(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* reset av */
- tcg_gen_movi_tl(cpu_PSW_AV, 0);
+ tcg_gen_movi_i32(cpu_PSW_AV, 0);
/* write result */
- tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
+ tcg_gen_mov_i32(cpu_gpr_d[r3], cpu_gpr_d[r1]);
/* sign extend to high reg */
- tcg_gen_sari_tl(cpu_gpr_d[r3+1], cpu_gpr_d[r1], 31);
+ tcg_gen_sari_i32(cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], 31);
break;
case OPC2_32_RR_DVINIT_U:
CHECK_REG_PAIR(r3);
/* overflow = (D[b] == 0) */
- tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0);
- tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
+ tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0);
+ tcg_gen_shli_i32(cpu_PSW_V, cpu_PSW_V, 31);
/* sv */
- tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
+ tcg_gen_or_i32(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* reset av */
- tcg_gen_movi_tl(cpu_PSW_AV, 0);
+ tcg_gen_movi_i32(cpu_PSW_AV, 0);
/* write result */
- tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
+ tcg_gen_mov_i32(cpu_gpr_d[r3], cpu_gpr_d[r1]);
/* zero extend to high reg*/
- tcg_gen_movi_tl(cpu_gpr_d[r3+1], 0);
+ tcg_gen_movi_i32(cpu_gpr_d[r3 + 1], 0);
break;
case OPC2_32_RR_PARITY:
gen_helper_parity(cpu_gpr_d[r3], cpu_gpr_d[r1]);
break;
case OPC2_32_RR_UNPACK:
CHECK_REG_PAIR(r3);
- gen_unpack(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
+ gen_unpack(cpu_gpr_d[r3], cpu_gpr_d[r3 + 1], cpu_gpr_d[r1]);
break;
case OPC2_32_RR_CRC32_B:
if (has_feature(ctx, TRICORE_FEATURE_162)) {
@@ -6229,7 +6230,7 @@ static void decode_rr_divide(DisasContext *ctx)
case OPC2_32_RR_POPCNT_W:
if (has_feature(ctx, TRICORE_FEATURE_162)) {
- tcg_gen_ctpop_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
+ tcg_gen_ctpop_i32(cpu_gpr_d[r3], cpu_gpr_d[r1]);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
@@ -6237,7 +6238,7 @@ static void decode_rr_divide(DisasContext *ctx)
case OPC2_32_RR_DIV:
if (has_feature(ctx, TRICORE_FEATURE_16)) {
CHECK_REG_PAIR(r3);
- GEN_HELPER_RR(divide, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
+ GEN_HELPER_RR(divide, cpu_gpr_d[r3], cpu_gpr_d[r3 + 1], cpu_gpr_d[r1],
cpu_gpr_d[r2]);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
@@ -6246,7 +6247,7 @@ static void decode_rr_divide(DisasContext *ctx)
case OPC2_32_RR_DIV_U:
if (has_feature(ctx, TRICORE_FEATURE_16)) {
CHECK_REG_PAIR(r3);
- GEN_HELPER_RR(divide_u, cpu_gpr_d[r3], cpu_gpr_d[r3+1],
+ GEN_HELPER_RR(divide_u, cpu_gpr_d[r3], cpu_gpr_d[r3 + 1],
cpu_gpr_d[r1], cpu_gpr_d[r2]);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
@@ -6328,69 +6329,69 @@ static void decode_rr1_mul(DisasContext *ctx)
temp64 = tcg_temp_new_i64();
CHECK_REG_PAIR(r3);
GEN_HELPER_LL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
- tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
- gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
+ tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3 + 1], temp64);
+ gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3 + 1]);
break;
case OPC2_32_RR1_MUL_H_32_LU:
temp64 = tcg_temp_new_i64();
CHECK_REG_PAIR(r3);
GEN_HELPER_LU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
- tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
- gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
+ tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3 + 1], temp64);
+ gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3 + 1]);
break;
case OPC2_32_RR1_MUL_H_32_UL:
temp64 = tcg_temp_new_i64();
CHECK_REG_PAIR(r3);
GEN_HELPER_UL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
- tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
- gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
+ tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3 + 1], temp64);
+ gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3 + 1]);
break;
case OPC2_32_RR1_MUL_H_32_UU:
temp64 = tcg_temp_new_i64();
CHECK_REG_PAIR(r3);
GEN_HELPER_UU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
- tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
- gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
+ tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3 + 1], temp64);
+ gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3 + 1]);
break;
case OPC2_32_RR1_MULM_H_64_LL:
temp64 = tcg_temp_new_i64();
CHECK_REG_PAIR(r3);
GEN_HELPER_LL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
- tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
+ tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3 + 1], temp64);
/* reset V bit */
- tcg_gen_movi_tl(cpu_PSW_V, 0);
+ tcg_gen_movi_i32(cpu_PSW_V, 0);
/* reset AV bit */
- tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
+ tcg_gen_mov_i32(cpu_PSW_AV, cpu_PSW_V);
break;
case OPC2_32_RR1_MULM_H_64_LU:
temp64 = tcg_temp_new_i64();
CHECK_REG_PAIR(r3);
GEN_HELPER_LU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
- tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
+ tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3 + 1], temp64);
/* reset V bit */
- tcg_gen_movi_tl(cpu_PSW_V, 0);
+ tcg_gen_movi_i32(cpu_PSW_V, 0);
/* reset AV bit */
- tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
+ tcg_gen_mov_i32(cpu_PSW_AV, cpu_PSW_V);
break;
case OPC2_32_RR1_MULM_H_64_UL:
temp64 = tcg_temp_new_i64();
CHECK_REG_PAIR(r3);
GEN_HELPER_UL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
- tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
+ tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3 + 1], temp64);
/* reset V bit */
- tcg_gen_movi_tl(cpu_PSW_V, 0);
+ tcg_gen_movi_i32(cpu_PSW_V, 0);
/* reset AV bit */
- tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
+ tcg_gen_mov_i32(cpu_PSW_AV, cpu_PSW_V);
break;
case OPC2_32_RR1_MULM_H_64_UU:
temp64 = tcg_temp_new_i64();
CHECK_REG_PAIR(r3);
GEN_HELPER_UU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
- tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
+ tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3 + 1], temp64);
/* reset V bit */
- tcg_gen_movi_tl(cpu_PSW_V, 0);
+ tcg_gen_movi_i32(cpu_PSW_V, 0);
/* reset AV bit */
- tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
+ tcg_gen_mov_i32(cpu_PSW_AV, cpu_PSW_V);
break;
case OPC2_32_RR1_MULR_H_16_LL:
GEN_HELPER_LL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
@@ -6436,45 +6437,45 @@ static void decode_rr1_mulq(DisasContext *ctx)
break;
case OPC2_32_RR1_MUL_Q_64:
CHECK_REG_PAIR(r3);
- gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
+ gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, 0);
break;
case OPC2_32_RR1_MUL_Q_32_L:
- tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
+ tcg_gen_ext16s_i32(temp, cpu_gpr_d[r2]);
gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16);
break;
case OPC2_32_RR1_MUL_Q_64_L:
CHECK_REG_PAIR(r3);
- tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
- gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0);
+ tcg_gen_ext16s_i32(temp, cpu_gpr_d[r2]);
+ gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], temp, n, 0);
break;
case OPC2_32_RR1_MUL_Q_32_U:
- tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
+ tcg_gen_sari_i32(temp, cpu_gpr_d[r2], 16);
gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16);
break;
case OPC2_32_RR1_MUL_Q_64_U:
CHECK_REG_PAIR(r3);
- tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
- gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0);
+ tcg_gen_sari_i32(temp, cpu_gpr_d[r2], 16);
+ gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], temp, n, 0);
break;
case OPC2_32_RR1_MUL_Q_32_LL:
- tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
- tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
+ tcg_gen_ext16s_i32(temp, cpu_gpr_d[r1]);
+ tcg_gen_ext16s_i32(temp2, cpu_gpr_d[r2]);
gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n);
break;
case OPC2_32_RR1_MUL_Q_32_UU:
- tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
- tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
+ tcg_gen_sari_i32(temp, cpu_gpr_d[r1], 16);
+ tcg_gen_sari_i32(temp2, cpu_gpr_d[r2], 16);
gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n);
break;
case OPC2_32_RR1_MULR_Q_32_L:
- tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
- tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
+ tcg_gen_ext16s_i32(temp, cpu_gpr_d[r1]);
+ tcg_gen_ext16s_i32(temp2, cpu_gpr_d[r2]);
gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n);
break;
case OPC2_32_RR1_MULR_Q_32_U:
- tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
- tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
+ tcg_gen_sari_i32(temp, cpu_gpr_d[r1], 16);
+ tcg_gen_sari_i32(temp2, cpu_gpr_d[r2], 16);
gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n);
break;
default:
@@ -6498,7 +6499,7 @@ static void decode_rr2_mul(DisasContext *ctx)
break;
case OPC2_32_RR2_MUL_64:
CHECK_REG_PAIR(r3);
- gen_mul_i64s(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
+ gen_mul_i64s(cpu_gpr_d[r3], cpu_gpr_d[r3 + 1], cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC2_32_RR2_MULS_32:
@@ -6507,7 +6508,7 @@ static void decode_rr2_mul(DisasContext *ctx)
break;
case OPC2_32_RR2_MUL_U_64:
CHECK_REG_PAIR(r3);
- gen_mul_i64u(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
+ gen_mul_i64u(cpu_gpr_d[r3], cpu_gpr_d[r3 + 1], cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC2_32_RR2_MULS_U_32:
@@ -6537,16 +6538,16 @@ static void decode_rrpw_extract_insert(DisasContext *ctx)
switch (op2) {
case OPC2_32_RRPW_EXTR:
if (width == 0) {
- tcg_gen_movi_tl(cpu_gpr_d[r3], 0);
+ tcg_gen_movi_i32(cpu_gpr_d[r3], 0);
} else if (pos + width <= 32) {
- tcg_gen_sextract_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], pos, width);
+ tcg_gen_sextract_i32(cpu_gpr_d[r3], cpu_gpr_d[r1], pos, width);
}
break;
case OPC2_32_RRPW_EXTR_U:
if (width == 0) {
- tcg_gen_movi_tl(cpu_gpr_d[r3], 0);
+ tcg_gen_movi_i32(cpu_gpr_d[r3], 0);
} else {
- tcg_gen_extract_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], pos, width);
+ tcg_gen_extract_i32(cpu_gpr_d[r3], cpu_gpr_d[r1], pos, width);
}
break;
case OPC2_32_RRPW_IMASK:
@@ -6554,18 +6555,18 @@ static void decode_rrpw_extract_insert(DisasContext *ctx)
if (pos + width <= 32) {
temp = tcg_temp_new();
- tcg_gen_movi_tl(temp, ((1u << width) - 1) << pos);
- tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], pos);
- tcg_gen_mov_tl(cpu_gpr_d[r3 + 1], temp);
+ tcg_gen_movi_i32(temp, ((1u << width) - 1) << pos);
+ tcg_gen_shli_i32(cpu_gpr_d[r3], cpu_gpr_d[r2], pos);
+ tcg_gen_mov_i32(cpu_gpr_d[r3 + 1], temp);
}
break;
case OPC2_32_RRPW_INSERT:
- /* tcg_gen_deposit_tl() does not handle the case of width = 0 */
+ /* tcg_gen_deposit_i32() does not handle the case of width = 0 */
if (width == 0) {
- tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
+ tcg_gen_mov_i32(cpu_gpr_d[r3], cpu_gpr_d[r1]);
} else if (pos + width <= 32) {
- tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
+ tcg_gen_deposit_i32(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
pos, width);
}
break;
@@ -6606,12 +6607,12 @@ static void decode_rrr_cond_select(DisasContext *ctx)
break;
case OPC2_32_RRR_SEL:
temp = tcg_constant_i32(0);
- tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
+ tcg_gen_movcond_i32(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR_SELN:
temp = tcg_constant_i32(0);
- tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
+ tcg_gen_movcond_i32(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
default:
@@ -6635,49 +6636,49 @@ static void decode_rrr_divide(DisasContext *ctx)
case OPC2_32_RRR_DVADJ:
CHECK_REG_PAIR(r3);
CHECK_REG_PAIR(r4);
- GEN_HELPER_RRR(dvadj, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
+ GEN_HELPER_RRR(dvadj, cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR_DVSTEP:
CHECK_REG_PAIR(r3);
CHECK_REG_PAIR(r4);
- GEN_HELPER_RRR(dvstep, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
+ GEN_HELPER_RRR(dvstep, cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR_DVSTEP_U:
CHECK_REG_PAIR(r3);
CHECK_REG_PAIR(r4);
- GEN_HELPER_RRR(dvstep_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
+ GEN_HELPER_RRR(dvstep_u, cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR_IXMAX:
CHECK_REG_PAIR(r3);
CHECK_REG_PAIR(r4);
- GEN_HELPER_RRR(ixmax, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
+ GEN_HELPER_RRR(ixmax, cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR_IXMAX_U:
CHECK_REG_PAIR(r3);
CHECK_REG_PAIR(r4);
- GEN_HELPER_RRR(ixmax_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
+ GEN_HELPER_RRR(ixmax_u, cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR_IXMIN:
CHECK_REG_PAIR(r3);
CHECK_REG_PAIR(r4);
- GEN_HELPER_RRR(ixmin, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
+ GEN_HELPER_RRR(ixmin, cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR_IXMIN_U:
CHECK_REG_PAIR(r3);
CHECK_REG_PAIR(r4);
- GEN_HELPER_RRR(ixmin_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
+ GEN_HELPER_RRR(ixmin_u, cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR_PACK:
CHECK_REG_PAIR(r3);
gen_helper_pack(cpu_gpr_d[r4], cpu_PSW_C, cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1]);
break;
case OPC2_32_RRR_CRCN:
if (has_feature(ctx, TRICORE_FEATURE_162)) {
@@ -6725,8 +6726,8 @@ static void decode_rrr2_madd(DisasContext *ctx)
case OPC2_32_RRR2_MADD_64:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_madd64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
- cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
+ gen_madd64_d(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r1],
+ cpu_gpr_d[r3], cpu_gpr_d[r3 + 1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR2_MADDS_32:
gen_helper_madd32_ssov(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1],
@@ -6735,14 +6736,14 @@ static void decode_rrr2_madd(DisasContext *ctx)
case OPC2_32_RRR2_MADDS_64:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_madds_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
- cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
+ gen_madds_64(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r1],
+ cpu_gpr_d[r3], cpu_gpr_d[r3 + 1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR2_MADD_U_64:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_maddu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
- cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
+ gen_maddu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r1],
+ cpu_gpr_d[r3], cpu_gpr_d[r3 + 1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR2_MADDS_U_32:
gen_helper_madd32_suov(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1],
@@ -6751,8 +6752,8 @@ static void decode_rrr2_madd(DisasContext *ctx)
case OPC2_32_RRR2_MADDS_U_64:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_maddsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
- cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
+ gen_maddsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r1],
+ cpu_gpr_d[r3], cpu_gpr_d[r3 + 1], cpu_gpr_d[r2]);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
@@ -6778,8 +6779,8 @@ static void decode_rrr2_msub(DisasContext *ctx)
case OPC2_32_RRR2_MSUB_64:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_msub64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
- cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
+ gen_msub64_d(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r1],
+ cpu_gpr_d[r3], cpu_gpr_d[r3 + 1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR2_MSUBS_32:
gen_helper_msub32_ssov(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1],
@@ -6788,14 +6789,14 @@ static void decode_rrr2_msub(DisasContext *ctx)
case OPC2_32_RRR2_MSUBS_64:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_msubs_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
- cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
+ gen_msubs_64(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r1],
+ cpu_gpr_d[r3], cpu_gpr_d[r3 + 1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR2_MSUB_U_64:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_msubu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
- cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
+ gen_msubu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r1],
+ cpu_gpr_d[r3], cpu_gpr_d[r3 + 1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR2_MSUBS_U_32:
gen_helper_msub32_suov(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1],
@@ -6804,8 +6805,8 @@ static void decode_rrr2_msub(DisasContext *ctx)
case OPC2_32_RRR2_MSUBS_U_64:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_msubsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
- cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
+ gen_msubsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r1],
+ cpu_gpr_d[r3], cpu_gpr_d[r3 + 1], cpu_gpr_d[r2]);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
@@ -6829,98 +6830,98 @@ static void decode_rrr1_madd(DisasContext *ctx)
case OPC2_32_RRR1_MADD_H_LL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
+ gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
break;
case OPC2_32_RRR1_MADD_H_LU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
+ gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
break;
case OPC2_32_RRR1_MADD_H_UL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
+ gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
break;
case OPC2_32_RRR1_MADD_H_UU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
+ gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
break;
case OPC2_32_RRR1_MADDS_H_LL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
+ gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
break;
case OPC2_32_RRR1_MADDS_H_LU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
+ gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
break;
case OPC2_32_RRR1_MADDS_H_UL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
+ gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
break;
case OPC2_32_RRR1_MADDS_H_UU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
+ gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
break;
case OPC2_32_RRR1_MADDM_H_LL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
+ gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
break;
case OPC2_32_RRR1_MADDM_H_LU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
+ gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
break;
case OPC2_32_RRR1_MADDM_H_UL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
+ gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
break;
case OPC2_32_RRR1_MADDM_H_UU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
+ gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
break;
case OPC2_32_RRR1_MADDMS_H_LL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
+ gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
break;
case OPC2_32_RRR1_MADDMS_H_LU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
+ gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
break;
case OPC2_32_RRR1_MADDMS_H_UL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
+ gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
break;
case OPC2_32_RRR1_MADDMS_H_UU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
+ gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
break;
case OPC2_32_RRR1_MADDR_H_LL:
gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
@@ -6983,61 +6984,61 @@ static void decode_rrr1_maddq_h(DisasContext *ctx)
case OPC2_32_RRR1_MADD_Q_64:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
+ gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n);
break;
case OPC2_32_RRR1_MADD_Q_32_L:
- tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
+ tcg_gen_ext16s_i32(temp, cpu_gpr_d[r2]);
gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
temp, n, 16);
break;
case OPC2_32_RRR1_MADD_Q_64_L:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
- gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
+ tcg_gen_ext16s_i32(temp, cpu_gpr_d[r2]);
+ gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], temp,
n);
break;
case OPC2_32_RRR1_MADD_Q_32_U:
- tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
+ tcg_gen_sari_i32(temp, cpu_gpr_d[r2], 16);
gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
temp, n, 16);
break;
case OPC2_32_RRR1_MADD_Q_64_U:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
- gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
+ tcg_gen_sari_i32(temp, cpu_gpr_d[r2], 16);
+ gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], temp,
n);
break;
case OPC2_32_RRR1_MADD_Q_32_LL:
- tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
- tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
+ tcg_gen_ext16s_i32(temp, cpu_gpr_d[r1]);
+ tcg_gen_ext16s_i32(temp2, cpu_gpr_d[r2]);
gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
break;
case OPC2_32_RRR1_MADD_Q_64_LL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
- tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
- gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], temp, temp2, n);
+ tcg_gen_ext16s_i32(temp, cpu_gpr_d[r1]);
+ tcg_gen_ext16s_i32(temp2, cpu_gpr_d[r2]);
+ gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], temp, temp2, n);
break;
case OPC2_32_RRR1_MADD_Q_32_UU:
- tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
- tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
+ tcg_gen_sari_i32(temp, cpu_gpr_d[r1], 16);
+ tcg_gen_sari_i32(temp2, cpu_gpr_d[r2], 16);
gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
break;
case OPC2_32_RRR1_MADD_Q_64_UU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
- tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
- gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], temp, temp2, n);
+ tcg_gen_sari_i32(temp, cpu_gpr_d[r1], 16);
+ tcg_gen_sari_i32(temp2, cpu_gpr_d[r2], 16);
+ gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], temp, temp2, n);
break;
case OPC2_32_RRR1_MADDS_Q_32:
gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
@@ -7046,90 +7047,90 @@ static void decode_rrr1_maddq_h(DisasContext *ctx)
case OPC2_32_RRR1_MADDS_Q_64:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
+ gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n);
break;
case OPC2_32_RRR1_MADDS_Q_32_L:
- tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
+ tcg_gen_ext16s_i32(temp, cpu_gpr_d[r2]);
gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
temp, n, 16);
break;
case OPC2_32_RRR1_MADDS_Q_64_L:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
- gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
+ tcg_gen_ext16s_i32(temp, cpu_gpr_d[r2]);
+ gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], temp,
n);
break;
case OPC2_32_RRR1_MADDS_Q_32_U:
- tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
+ tcg_gen_sari_i32(temp, cpu_gpr_d[r2], 16);
gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
temp, n, 16);
break;
case OPC2_32_RRR1_MADDS_Q_64_U:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
- gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
+ tcg_gen_sari_i32(temp, cpu_gpr_d[r2], 16);
+ gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], temp,
n);
break;
case OPC2_32_RRR1_MADDS_Q_32_LL:
- tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
- tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
+ tcg_gen_ext16s_i32(temp, cpu_gpr_d[r1]);
+ tcg_gen_ext16s_i32(temp2, cpu_gpr_d[r2]);
gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
break;
case OPC2_32_RRR1_MADDS_Q_64_LL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
- tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
- gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], temp, temp2, n);
+ tcg_gen_ext16s_i32(temp, cpu_gpr_d[r1]);
+ tcg_gen_ext16s_i32(temp2, cpu_gpr_d[r2]);
+ gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], temp, temp2, n);
break;
case OPC2_32_RRR1_MADDS_Q_32_UU:
- tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
- tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
+ tcg_gen_sari_i32(temp, cpu_gpr_d[r1], 16);
+ tcg_gen_sari_i32(temp2, cpu_gpr_d[r2], 16);
gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
break;
case OPC2_32_RRR1_MADDS_Q_64_UU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
- tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
- gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], temp, temp2, n);
+ tcg_gen_sari_i32(temp, cpu_gpr_d[r1], 16);
+ tcg_gen_sari_i32(temp2, cpu_gpr_d[r2], 16);
+ gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], temp, temp2, n);
break;
case OPC2_32_RRR1_MADDR_H_64_UL:
CHECK_REG_PAIR(r3);
- gen_maddr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
+ gen_maddr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3 + 1],
cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
break;
case OPC2_32_RRR1_MADDRS_H_64_UL:
CHECK_REG_PAIR(r3);
- gen_maddr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
+ gen_maddr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3 + 1],
cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
break;
case OPC2_32_RRR1_MADDR_Q_32_LL:
- tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
- tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
+ tcg_gen_ext16s_i32(temp, cpu_gpr_d[r1]);
+ tcg_gen_ext16s_i32(temp2, cpu_gpr_d[r2]);
gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
break;
case OPC2_32_RRR1_MADDR_Q_32_UU:
- tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
- tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
+ tcg_gen_sari_i32(temp, cpu_gpr_d[r1], 16);
+ tcg_gen_sari_i32(temp2, cpu_gpr_d[r2], 16);
gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
break;
case OPC2_32_RRR1_MADDRS_Q_32_LL:
- tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
- tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
+ tcg_gen_ext16s_i32(temp, cpu_gpr_d[r1]);
+ tcg_gen_ext16s_i32(temp2, cpu_gpr_d[r2]);
gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
break;
case OPC2_32_RRR1_MADDRS_Q_32_UU:
- tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
- tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
+ tcg_gen_sari_i32(temp, cpu_gpr_d[r1], 16);
+ tcg_gen_sari_i32(temp2, cpu_gpr_d[r2], 16);
gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
break;
default:
@@ -7153,109 +7154,109 @@ static void decode_rrr1_maddsu_h(DisasContext *ctx)
case OPC2_32_RRR1_MADDSU_H_32_LL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
+ gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
break;
case OPC2_32_RRR1_MADDSU_H_32_LU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
+ gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
break;
case OPC2_32_RRR1_MADDSU_H_32_UL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
+ gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
break;
case OPC2_32_RRR1_MADDSU_H_32_UU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
+ gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
break;
case OPC2_32_RRR1_MADDSUS_H_32_LL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
+ gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_LL);
break;
case OPC2_32_RRR1_MADDSUS_H_32_LU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
+ gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_LU);
break;
case OPC2_32_RRR1_MADDSUS_H_32_UL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
+ gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_UL);
break;
case OPC2_32_RRR1_MADDSUS_H_32_UU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
+ gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_UU);
break;
case OPC2_32_RRR1_MADDSUM_H_64_LL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
+ gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_LL);
break;
case OPC2_32_RRR1_MADDSUM_H_64_LU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
+ gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_LU);
break;
case OPC2_32_RRR1_MADDSUM_H_64_UL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
+ gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_UL);
break;
case OPC2_32_RRR1_MADDSUM_H_64_UU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
+ gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_UU);
break;
case OPC2_32_RRR1_MADDSUMS_H_64_LL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
+ gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_LL);
break;
case OPC2_32_RRR1_MADDSUMS_H_64_LU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
+ gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_LU);
break;
case OPC2_32_RRR1_MADDSUMS_H_64_UL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
+ gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_UL);
break;
case OPC2_32_RRR1_MADDSUMS_H_64_UU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
+ gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_UU);
break;
case OPC2_32_RRR1_MADDSUR_H_16_LL:
@@ -7311,98 +7312,98 @@ static void decode_rrr1_msub(DisasContext *ctx)
case OPC2_32_RRR1_MSUB_H_LL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
+ gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
break;
case OPC2_32_RRR1_MSUB_H_LU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
+ gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
break;
case OPC2_32_RRR1_MSUB_H_UL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
+ gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
break;
case OPC2_32_RRR1_MSUB_H_UU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
+ gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
break;
case OPC2_32_RRR1_MSUBS_H_LL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
+ gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
break;
case OPC2_32_RRR1_MSUBS_H_LU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
+ gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
break;
case OPC2_32_RRR1_MSUBS_H_UL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
+ gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
break;
case OPC2_32_RRR1_MSUBS_H_UU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
+ gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
break;
case OPC2_32_RRR1_MSUBM_H_LL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
+ gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
break;
case OPC2_32_RRR1_MSUBM_H_LU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
+ gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
break;
case OPC2_32_RRR1_MSUBM_H_UL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
+ gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
break;
case OPC2_32_RRR1_MSUBM_H_UU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
+ gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
break;
case OPC2_32_RRR1_MSUBMS_H_LL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
+ gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
break;
case OPC2_32_RRR1_MSUBMS_H_LU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
+ gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
break;
case OPC2_32_RRR1_MSUBMS_H_UL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
+ gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
break;
case OPC2_32_RRR1_MSUBMS_H_UU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
+ gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
break;
case OPC2_32_RRR1_MSUBR_H_LL:
gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
@@ -7465,61 +7466,61 @@ static void decode_rrr1_msubq_h(DisasContext *ctx)
case OPC2_32_RRR1_MSUB_Q_64:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
+ gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n);
break;
case OPC2_32_RRR1_MSUB_Q_32_L:
- tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
+ tcg_gen_ext16s_i32(temp, cpu_gpr_d[r2]);
gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
temp, n, 16);
break;
case OPC2_32_RRR1_MSUB_Q_64_L:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
- gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
+ tcg_gen_ext16s_i32(temp, cpu_gpr_d[r2]);
+ gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], temp,
n);
break;
case OPC2_32_RRR1_MSUB_Q_32_U:
- tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
+ tcg_gen_sari_i32(temp, cpu_gpr_d[r2], 16);
gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
temp, n, 16);
break;
case OPC2_32_RRR1_MSUB_Q_64_U:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
- gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
+ tcg_gen_sari_i32(temp, cpu_gpr_d[r2], 16);
+ gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], temp,
n);
break;
case OPC2_32_RRR1_MSUB_Q_32_LL:
- tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
- tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
+ tcg_gen_ext16s_i32(temp, cpu_gpr_d[r1]);
+ tcg_gen_ext16s_i32(temp2, cpu_gpr_d[r2]);
gen_m16sub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
break;
case OPC2_32_RRR1_MSUB_Q_64_LL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
- tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
- gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], temp, temp2, n);
+ tcg_gen_ext16s_i32(temp, cpu_gpr_d[r1]);
+ tcg_gen_ext16s_i32(temp2, cpu_gpr_d[r2]);
+ gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], temp, temp2, n);
break;
case OPC2_32_RRR1_MSUB_Q_32_UU:
- tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
- tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
+ tcg_gen_sari_i32(temp, cpu_gpr_d[r1], 16);
+ tcg_gen_sari_i32(temp2, cpu_gpr_d[r2], 16);
gen_m16sub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
break;
case OPC2_32_RRR1_MSUB_Q_64_UU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
- tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
- gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], temp, temp2, n);
+ tcg_gen_sari_i32(temp, cpu_gpr_d[r1], 16);
+ tcg_gen_sari_i32(temp2, cpu_gpr_d[r2], 16);
+ gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], temp, temp2, n);
break;
case OPC2_32_RRR1_MSUBS_Q_32:
gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
@@ -7528,90 +7529,90 @@ static void decode_rrr1_msubq_h(DisasContext *ctx)
case OPC2_32_RRR1_MSUBS_Q_64:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
+ gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n);
break;
case OPC2_32_RRR1_MSUBS_Q_32_L:
- tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
+ tcg_gen_ext16s_i32(temp, cpu_gpr_d[r2]);
gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
temp, n, 16);
break;
case OPC2_32_RRR1_MSUBS_Q_64_L:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
- gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
+ tcg_gen_ext16s_i32(temp, cpu_gpr_d[r2]);
+ gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], temp,
n);
break;
case OPC2_32_RRR1_MSUBS_Q_32_U:
- tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
+ tcg_gen_sari_i32(temp, cpu_gpr_d[r2], 16);
gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
temp, n, 16);
break;
case OPC2_32_RRR1_MSUBS_Q_64_U:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
- gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
+ tcg_gen_sari_i32(temp, cpu_gpr_d[r2], 16);
+ gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], temp,
n);
break;
case OPC2_32_RRR1_MSUBS_Q_32_LL:
- tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
- tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
+ tcg_gen_ext16s_i32(temp, cpu_gpr_d[r1]);
+ tcg_gen_ext16s_i32(temp2, cpu_gpr_d[r2]);
gen_m16subs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
break;
case OPC2_32_RRR1_MSUBS_Q_64_LL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
- tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
- gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], temp, temp2, n);
+ tcg_gen_ext16s_i32(temp, cpu_gpr_d[r1]);
+ tcg_gen_ext16s_i32(temp2, cpu_gpr_d[r2]);
+ gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], temp, temp2, n);
break;
case OPC2_32_RRR1_MSUBS_Q_32_UU:
- tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
- tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
+ tcg_gen_sari_i32(temp, cpu_gpr_d[r1], 16);
+ tcg_gen_sari_i32(temp2, cpu_gpr_d[r2], 16);
gen_m16subs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
break;
case OPC2_32_RRR1_MSUBS_Q_64_UU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
- tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
- gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], temp, temp2, n);
+ tcg_gen_sari_i32(temp, cpu_gpr_d[r1], 16);
+ tcg_gen_sari_i32(temp2, cpu_gpr_d[r2], 16);
+ gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], temp, temp2, n);
break;
case OPC2_32_RRR1_MSUBR_H_64_UL:
CHECK_REG_PAIR(r3);
- gen_msubr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
+ gen_msubr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3 + 1],
cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
break;
case OPC2_32_RRR1_MSUBRS_H_64_UL:
CHECK_REG_PAIR(r3);
- gen_msubr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
+ gen_msubr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3 + 1],
cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
break;
case OPC2_32_RRR1_MSUBR_Q_32_LL:
- tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
- tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
+ tcg_gen_ext16s_i32(temp, cpu_gpr_d[r1]);
+ tcg_gen_ext16s_i32(temp2, cpu_gpr_d[r2]);
gen_msubr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
break;
case OPC2_32_RRR1_MSUBR_Q_32_UU:
- tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
- tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
+ tcg_gen_sari_i32(temp, cpu_gpr_d[r1], 16);
+ tcg_gen_sari_i32(temp2, cpu_gpr_d[r2], 16);
gen_msubr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
break;
case OPC2_32_RRR1_MSUBRS_Q_32_LL:
- tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
- tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
+ tcg_gen_ext16s_i32(temp, cpu_gpr_d[r1]);
+ tcg_gen_ext16s_i32(temp2, cpu_gpr_d[r2]);
gen_msubrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
break;
case OPC2_32_RRR1_MSUBRS_Q_32_UU:
- tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
- tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
+ tcg_gen_sari_i32(temp, cpu_gpr_d[r1], 16);
+ tcg_gen_sari_i32(temp2, cpu_gpr_d[r2], 16);
gen_msubrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
break;
default:
@@ -7635,109 +7636,109 @@ static void decode_rrr1_msubad_h(DisasContext *ctx)
case OPC2_32_RRR1_MSUBAD_H_32_LL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
+ gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
break;
case OPC2_32_RRR1_MSUBAD_H_32_LU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
+ gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
break;
case OPC2_32_RRR1_MSUBAD_H_32_UL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
+ gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
break;
case OPC2_32_RRR1_MSUBAD_H_32_UU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
+ gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
break;
case OPC2_32_RRR1_MSUBADS_H_32_LL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
+ gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_LL);
break;
case OPC2_32_RRR1_MSUBADS_H_32_LU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
+ gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_LU);
break;
case OPC2_32_RRR1_MSUBADS_H_32_UL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
+ gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_UL);
break;
case OPC2_32_RRR1_MSUBADS_H_32_UU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
+ gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_UU);
break;
case OPC2_32_RRR1_MSUBADM_H_64_LL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
+ gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_LL);
break;
case OPC2_32_RRR1_MSUBADM_H_64_LU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
+ gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_LU);
break;
case OPC2_32_RRR1_MSUBADM_H_64_UL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
+ gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_UL);
break;
case OPC2_32_RRR1_MSUBADM_H_64_UU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
+ gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_UU);
break;
case OPC2_32_RRR1_MSUBADMS_H_64_LL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
+ gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_LL);
break;
case OPC2_32_RRR1_MSUBADMS_H_64_LU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
+ gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_LU);
break;
case OPC2_32_RRR1_MSUBADMS_H_64_UL:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
+ gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_UL);
break;
case OPC2_32_RRR1_MSUBADMS_H_64_UU:
CHECK_REG_PAIR(r4);
CHECK_REG_PAIR(r3);
- gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
- cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
+ gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4 + 1], cpu_gpr_d[r3],
+ cpu_gpr_d[r3 + 1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_UU);
break;
case OPC2_32_RRR1_MSUBADR_H_16_LL:
@@ -7795,43 +7796,43 @@ static void decode_rrrr_extract_insert(DisasContext *ctx)
switch (op2) {
case OPC2_32_RRRR_DEXTR:
- tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f);
+ tcg_gen_andi_i32(tmp_pos, cpu_gpr_d[r3], 0x1f);
if (r1 == r2) {
- tcg_gen_rotl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos);
+ tcg_gen_rotl_i32(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos);
} else {
TCGv msw = tcg_temp_new();
- TCGv zero = tcg_constant_tl(0);
- tcg_gen_shl_tl(tmp_width, cpu_gpr_d[r1], tmp_pos);
- tcg_gen_subfi_tl(msw, 32, tmp_pos);
- tcg_gen_shr_tl(msw, cpu_gpr_d[r2], msw);
+ TCGv zero = tcg_constant_i32(0);
+ tcg_gen_shl_i32(tmp_width, cpu_gpr_d[r1], tmp_pos);
+ tcg_gen_subfi_i32(msw, 32, tmp_pos);
+ tcg_gen_shr_i32(msw, cpu_gpr_d[r2], msw);
/*
* if pos == 0, then we do cpu_gpr_d[r2] << 32, which is undefined
* behaviour. So check that case here and set the low bits to zero
* which effectivly returns cpu_gpr_d[r1]
*/
- tcg_gen_movcond_tl(TCG_COND_EQ, msw, tmp_pos, zero, zero, msw);
- tcg_gen_or_tl(cpu_gpr_d[r4], tmp_width, msw);
+ tcg_gen_movcond_i32(TCG_COND_EQ, msw, tmp_pos, zero, zero, msw);
+ tcg_gen_or_i32(cpu_gpr_d[r4], tmp_width, msw);
}
break;
case OPC2_32_RRRR_EXTR:
case OPC2_32_RRRR_EXTR_U:
CHECK_REG_PAIR(r3);
- tcg_gen_andi_tl(tmp_width, cpu_gpr_d[r3+1], 0x1f);
- tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f);
- tcg_gen_add_tl(tmp_pos, tmp_pos, tmp_width);
- tcg_gen_subfi_tl(tmp_pos, 32, tmp_pos);
- tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos);
- tcg_gen_subfi_tl(tmp_width, 32, tmp_width);
+ tcg_gen_andi_i32(tmp_width, cpu_gpr_d[r3 + 1], 0x1f);
+ tcg_gen_andi_i32(tmp_pos, cpu_gpr_d[r3], 0x1f);
+ tcg_gen_add_i32(tmp_pos, tmp_pos, tmp_width);
+ tcg_gen_subfi_i32(tmp_pos, 32, tmp_pos);
+ tcg_gen_shl_i32(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos);
+ tcg_gen_subfi_i32(tmp_width, 32, tmp_width);
if (op2 == OPC2_32_RRRR_EXTR) {
- tcg_gen_sar_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], tmp_width);
+ tcg_gen_sar_i32(cpu_gpr_d[r4], cpu_gpr_d[r4], tmp_width);
} else {
- tcg_gen_shr_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], tmp_width);
+ tcg_gen_shr_i32(cpu_gpr_d[r4], cpu_gpr_d[r4], tmp_width);
}
break;
case OPC2_32_RRRR_INSERT:
CHECK_REG_PAIR(r3);
- tcg_gen_andi_tl(tmp_width, cpu_gpr_d[r3+1], 0x1f);
- tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f);
+ tcg_gen_andi_i32(tmp_width, cpu_gpr_d[r3 + 1], 0x1f);
+ tcg_gen_andi_i32(tmp_pos, cpu_gpr_d[r3], 0x1f);
gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], tmp_width,
tmp_pos);
break;
@@ -7860,35 +7861,35 @@ static void decode_rrrw_extract_insert(DisasContext *ctx)
switch (op2) {
case OPC2_32_RRRW_EXTR:
- tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f);
- tcg_gen_addi_tl(temp, temp, width);
- tcg_gen_subfi_tl(temp, 32, temp);
- tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp);
- tcg_gen_sari_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], 32 - width);
+ tcg_gen_andi_i32(temp, cpu_gpr_d[r3], 0x1f);
+ tcg_gen_addi_i32(temp, temp, width);
+ tcg_gen_subfi_i32(temp, 32, temp);
+ tcg_gen_shl_i32(cpu_gpr_d[r4], cpu_gpr_d[r1], temp);
+ tcg_gen_sari_i32(cpu_gpr_d[r4], cpu_gpr_d[r4], 32 - width);
break;
case OPC2_32_RRRW_EXTR_U:
if (width == 0) {
- tcg_gen_movi_tl(cpu_gpr_d[r4], 0);
+ tcg_gen_movi_i32(cpu_gpr_d[r4], 0);
} else {
- tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f);
- tcg_gen_shr_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp);
- tcg_gen_andi_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], ~0u >> (32-width));
+ tcg_gen_andi_i32(temp, cpu_gpr_d[r3], 0x1f);
+ tcg_gen_shr_i32(cpu_gpr_d[r4], cpu_gpr_d[r1], temp);
+ tcg_gen_andi_i32(cpu_gpr_d[r4], cpu_gpr_d[r4], ~0u >> (32 - width));
}
break;
case OPC2_32_RRRW_IMASK:
temp2 = tcg_temp_new();
CHECK_REG_PAIR(r4);
- tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f);
- tcg_gen_movi_tl(temp2, (1 << width) - 1);
- tcg_gen_shl_tl(temp2, temp2, temp);
- tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r2], temp);
- tcg_gen_mov_tl(cpu_gpr_d[r4+1], temp2);
+ tcg_gen_andi_i32(temp, cpu_gpr_d[r3], 0x1f);
+ tcg_gen_movi_i32(temp2, (1 << width) - 1);
+ tcg_gen_shl_i32(temp2, temp2, temp);
+ tcg_gen_shl_i32(cpu_gpr_d[r4], cpu_gpr_d[r2], temp);
+ tcg_gen_mov_i32(cpu_gpr_d[r4 + 1], temp2);
break;
case OPC2_32_RRRW_INSERT:
temp2 = tcg_temp_new();
- tcg_gen_movi_tl(temp, width);
- tcg_gen_andi_tl(temp2, cpu_gpr_d[r3], 0x1f);
+ tcg_gen_movi_i32(temp, width);
+ tcg_gen_andi_i32(temp2, cpu_gpr_d[r3], 0x1f);
gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], temp, temp2);
break;
default:
@@ -7913,7 +7914,7 @@ static void decode_sys_interrupts(DisasContext *ctx)
break;
case OPC2_32_SYS_DISABLE:
if (ctx->priv == TRICORE_PRIV_SM || ctx->priv == TRICORE_PRIV_UM1) {
- tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~ctx->icr_ie_mask);
+ tcg_gen_andi_i32(cpu_ICR, cpu_ICR, ~ctx->icr_ie_mask);
} else {
generate_trap(ctx, TRAPC_PROT, TIN1_PRIV);
}
@@ -7921,9 +7922,9 @@ static void decode_sys_interrupts(DisasContext *ctx)
case OPC2_32_SYS_DISABLE_D:
if (has_feature(ctx, TRICORE_FEATURE_16)) {
if (ctx->priv == TRICORE_PRIV_SM || ctx->priv == TRICORE_PRIV_UM1) {
- tcg_gen_extract_tl(cpu_gpr_d[r1], cpu_ICR,
+ tcg_gen_extract_i32(cpu_gpr_d[r1], cpu_ICR,
ctx->icr_ie_offset, 1);
- tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~ctx->icr_ie_mask);
+ tcg_gen_andi_i32(cpu_ICR, cpu_ICR, ~ctx->icr_ie_mask);
} else {
generate_trap(ctx, TRAPC_PROT, TIN1_PRIV);
}
@@ -7934,7 +7935,7 @@ static void decode_sys_interrupts(DisasContext *ctx)
break;
case OPC2_32_SYS_ENABLE:
if (ctx->priv == TRICORE_PRIV_SM || ctx->priv == TRICORE_PRIV_UM1) {
- tcg_gen_ori_tl(cpu_ICR, cpu_ICR, ctx->icr_ie_mask);
+ tcg_gen_ori_i32(cpu_ICR, cpu_ICR, ctx->icr_ie_mask);
ctx->base.is_jmp = DISAS_EXIT_UPDATE;
} else {
generate_trap(ctx, TRAPC_PROT, TIN1_PRIV);
@@ -7960,8 +7961,8 @@ static void decode_sys_interrupts(DisasContext *ctx)
l1 = gen_new_label();
tcg_gen_ld_i32(tmp, tcg_env, offsetof(CPUTriCoreState, DBGSR));
- tcg_gen_andi_tl(tmp, tmp, MASK_DBGSR_DE);
- tcg_gen_brcondi_tl(TCG_COND_NE, tmp, 1, l1);
+ tcg_gen_andi_i32(tmp, tmp, MASK_DBGSR_DE);
+ tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 1, l1);
gen_helper_rfm(tcg_env);
gen_set_label(l1);
ctx->base.is_jmp = DISAS_EXIT;
@@ -7978,7 +7979,7 @@ static void decode_sys_interrupts(DisasContext *ctx)
case OPC2_32_SYS_RESTORE:
if (has_feature(ctx, TRICORE_FEATURE_16)) {
if (ctx->priv == TRICORE_PRIV_SM || ctx->priv == TRICORE_PRIV_UM1) {
- tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1],
+ tcg_gen_deposit_i32(cpu_ICR, cpu_ICR, cpu_gpr_d[r1],
ctx->icr_ie_offset, 1);
ctx->base.is_jmp = DISAS_EXIT_UPDATE;
} else {
@@ -7990,13 +7991,13 @@ static void decode_sys_interrupts(DisasContext *ctx)
break;
case OPC2_32_SYS_TRAPSV:
l1 = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_GE, cpu_PSW_SV, 0, l1);
+ tcg_gen_brcondi_i32(TCG_COND_GE, cpu_PSW_SV, 0, l1);
generate_trap(ctx, TRAPC_ASSERT, TIN5_SOVF);
gen_set_label(l1);
break;
case OPC2_32_SYS_TRAPV:
l1 = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_GE, cpu_PSW_V, 0, l1);
+ tcg_gen_brcondi_i32(TCG_COND_GE, cpu_PSW_V, 0, l1);
generate_trap(ctx, TRAPC_ASSERT, TIN5_OVF);
gen_set_label(l1);
break;
@@ -8047,16 +8048,16 @@ static void decode_32Bit_opc(DisasContext *ctx)
temp = tcg_constant_i32(EA_ABS_FORMAT(address));
temp2 = tcg_temp_new();
- tcg_gen_shri_tl(temp2, cpu_gpr_d[r1], 16);
- tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_LEUW);
+ tcg_gen_shri_i32(temp2, cpu_gpr_d[r1], 16);
+ tcg_gen_qemu_st_i32(temp2, temp, ctx->mem_idx, MO_LEUW);
break;
case OPC1_32_ABS_LD_Q:
address = MASK_OP_ABS_OFF18(ctx->opcode);
r1 = MASK_OP_ABS_S1D(ctx->opcode);
temp = tcg_constant_i32(EA_ABS_FORMAT(address));
- tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
- tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
+ tcg_gen_qemu_ld_i32(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
+ tcg_gen_shli_i32(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
break;
case OPCM_32_ABS_LEA_LHA:
address = MASK_OP_ABS_OFF18(ctx->opcode);
@@ -8065,13 +8066,13 @@ static void decode_32Bit_opc(DisasContext *ctx)
if (has_feature(ctx, TRICORE_FEATURE_162)) {
op2 = MASK_OP_ABS_OP2(ctx->opcode);
if (op2 == OPC2_32_ABS_LHA) {
- tcg_gen_movi_tl(cpu_gpr_a[r1], address << 14);
+ tcg_gen_movi_i32(cpu_gpr_a[r1], address << 14);
break;
}
/* otherwise translate regular LEA */
}
- tcg_gen_movi_tl(cpu_gpr_a[r1], EA_ABS_FORMAT(address));
+ tcg_gen_movi_i32(cpu_gpr_a[r1], EA_ABS_FORMAT(address));
break;
/* ABSB-format */
case OPC1_32_ABSB_ST_T:
@@ -8082,10 +8083,10 @@ static void decode_32Bit_opc(DisasContext *ctx)
temp = tcg_constant_i32(EA_ABS_FORMAT(address));
temp2 = tcg_temp_new();
- tcg_gen_qemu_ld_tl(temp2, temp, ctx->mem_idx, MO_UB);
- tcg_gen_andi_tl(temp2, temp2, ~(0x1u << bpos));
- tcg_gen_ori_tl(temp2, temp2, (b << bpos));
- tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_UB);
+ tcg_gen_qemu_ld_i32(temp2, temp, ctx->mem_idx, MO_UB);
+ tcg_gen_andi_i32(temp2, temp2, ~(0x1u << bpos));
+ tcg_gen_ori_i32(temp2, temp2, (b << bpos));
+ tcg_gen_qemu_st_i32(temp2, temp, ctx->mem_idx, MO_UB);
break;
/* B-format */
case OPC1_32_B_CALL:
@@ -8212,8 +8213,8 @@ static void decode_32Bit_opc(DisasContext *ctx)
CHECK_REG_PAIR(r2);
- tcg_gen_andi_tl(temp2, cpu_gpr_d[r2 + 1], 0x1f);
- tcg_gen_andi_tl(temp3, cpu_gpr_d[r2], 0x1f);
+ tcg_gen_andi_i32(temp2, cpu_gpr_d[r2 + 1], 0x1f);
+ tcg_gen_andi_i32(temp3, cpu_gpr_d[r2], 0x1f);
gen_insert(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, temp2, temp3);
break;
@@ -8281,7 +8282,7 @@ static void decode_32Bit_opc(DisasContext *ctx)
r3 = MASK_OP_RRPW_D(ctx->opcode);
const16 = MASK_OP_RRPW_POS(ctx->opcode);
- tcg_gen_extract2_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], cpu_gpr_d[r1],
+ tcg_gen_extract2_i32(cpu_gpr_d[r3], cpu_gpr_d[r2], cpu_gpr_d[r1],
32 - const16);
break;
/* RRR Format */
@@ -8330,10 +8331,10 @@ static void decode_32Bit_opc(DisasContext *ctx)
decode_sys_interrupts(ctx);
break;
case OPC1_32_SYS_RSTV:
- tcg_gen_movi_tl(cpu_PSW_V, 0);
- tcg_gen_mov_tl(cpu_PSW_SV, cpu_PSW_V);
- tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
- tcg_gen_mov_tl(cpu_PSW_SAV, cpu_PSW_V);
+ tcg_gen_movi_i32(cpu_PSW_V, 0);
+ tcg_gen_mov_i32(cpu_PSW_SV, cpu_PSW_V);
+ tcg_gen_mov_i32(cpu_PSW_AV, cpu_PSW_V);
+ tcg_gen_mov_i32(cpu_PSW_SAV, cpu_PSW_V);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
--
2.51.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 10/12] target/tricore: Pass DisasContext as first argument
2025-10-10 5:21 [PATCH 00/12] target/tricore: Remove all uses of target_ulong types Philippe Mathieu-Daudé
` (8 preceding siblings ...)
2025-10-10 5:21 ` [PATCH 09/12] target/tricore: Expand TCG helpers for 32-bit target Philippe Mathieu-Daudé
@ 2025-10-10 5:21 ` Philippe Mathieu-Daudé
2025-10-10 17:07 ` Richard Henderson
2025-10-10 5:21 ` [PATCH 11/12] target/tricore: Un-inline various helpers Philippe Mathieu-Daudé
2025-10-10 5:21 ` [PATCH 12/12] target/tricore: Expand TCGv type for 32-bit target Philippe Mathieu-Daudé
11 siblings, 1 reply; 25+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-10 5:21 UTC (permalink / raw)
To: qemu-devel
Cc: Bastian Koppelmann, Pierrick Bouvier, Anton Johansson,
Philippe Mathieu-Daudé
Unify style, always pass DisasContext as the first argument.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/tricore/translate.c | 68 +++++++++++++++++++-------------------
1 file changed, 34 insertions(+), 34 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index ce4e3f6202e..595db14bb2b 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -226,7 +226,7 @@ static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2,
tcg_gen_qemu_st_i32(r1, temp, ctx->mem_idx, mop);
}
-static void gen_st_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx)
+static void gen_st_2regs_64(DisasContext *ctx, TCGv rh, TCGv rl, TCGv address)
{
TCGv_i64 temp = tcg_temp_new_i64();
@@ -234,15 +234,15 @@ static void gen_st_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx)
tcg_gen_qemu_st_i64(temp, address, ctx->mem_idx, MO_LEUQ);
}
-static void gen_offset_st_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con,
- DisasContext *ctx)
+static void gen_offset_st_2regs(DisasContext *ctx,
+ TCGv rh, TCGv rl, TCGv base, int16_t con)
{
TCGv temp = tcg_temp_new();
tcg_gen_addi_i32(temp, base, con);
- gen_st_2regs_64(rh, rl, temp, ctx);
+ gen_st_2regs_64(ctx, rh, rl, temp);
}
-static void gen_ld_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx)
+static void gen_ld_2regs_64(DisasContext *ctx, TCGv rh, TCGv rl, TCGv address)
{
TCGv_i64 temp = tcg_temp_new_i64();
@@ -251,12 +251,12 @@ static void gen_ld_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx)
tcg_gen_extr_i64_i32(rl, rh, temp);
}
-static void gen_offset_ld_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con,
- DisasContext *ctx)
+static void gen_offset_ld_2regs(DisasContext *ctx,
+ TCGv rh, TCGv rl, TCGv base, int16_t con)
{
TCGv temp = tcg_temp_new();
tcg_gen_addi_i32(temp, base, con);
- gen_ld_2regs_64(rh, rl, temp, ctx);
+ gen_ld_2regs_64(ctx, rh, rl, temp);
}
static void gen_st_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,
@@ -3798,11 +3798,11 @@ static void decode_abs_ldw(DisasContext *ctx)
break;
case OPC2_32_ABS_LD_D:
CHECK_REG_PAIR(r1);
- gen_ld_2regs_64(cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], temp, ctx);
+ gen_ld_2regs_64(ctx, cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], temp);
break;
case OPC2_32_ABS_LD_DA:
CHECK_REG_PAIR(r1);
- gen_ld_2regs_64(cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], temp, ctx);
+ gen_ld_2regs_64(ctx, cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], temp);
break;
case OPC2_32_ABS_LD_W:
tcg_gen_qemu_ld_i32(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL);
@@ -3913,11 +3913,11 @@ static void decode_abs_store(DisasContext *ctx)
break;
case OPC2_32_ABS_ST_D:
CHECK_REG_PAIR(r1);
- gen_st_2regs_64(cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], temp, ctx);
+ gen_st_2regs_64(ctx, cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], temp);
break;
case OPC2_32_ABS_ST_DA:
CHECK_REG_PAIR(r1);
- gen_st_2regs_64(cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], temp, ctx);
+ gen_st_2regs_64(ctx, cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], temp);
break;
case OPC2_32_ABS_ST_W:
tcg_gen_qemu_st_i32(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL);
@@ -4289,36 +4289,36 @@ static void decode_bo_addrmode_post_pre_base(DisasContext *ctx)
break;
case OPC2_32_BO_ST_D_SHORTOFF:
CHECK_REG_PAIR(r1);
- gen_offset_st_2regs(cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], cpu_gpr_a[r2],
- off10, ctx);
+ gen_offset_st_2regs(ctx, cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], cpu_gpr_a[r2],
+ off10);
break;
case OPC2_32_BO_ST_D_POSTINC:
CHECK_REG_PAIR(r1);
- gen_st_2regs_64(cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx);
+ gen_st_2regs_64(ctx, cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], cpu_gpr_a[r2]);
tcg_gen_addi_i32(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_ST_D_PREINC:
CHECK_REG_PAIR(r1);
temp = tcg_temp_new();
tcg_gen_addi_i32(temp, cpu_gpr_a[r2], off10);
- gen_st_2regs_64(cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], temp, ctx);
+ gen_st_2regs_64(ctx, cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], temp);
tcg_gen_mov_i32(cpu_gpr_a[r2], temp);
break;
case OPC2_32_BO_ST_DA_SHORTOFF:
CHECK_REG_PAIR(r1);
- gen_offset_st_2regs(cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], cpu_gpr_a[r2],
- off10, ctx);
+ gen_offset_st_2regs(ctx, cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], cpu_gpr_a[r2],
+ off10);
break;
case OPC2_32_BO_ST_DA_POSTINC:
CHECK_REG_PAIR(r1);
- gen_st_2regs_64(cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx);
+ gen_st_2regs_64(ctx, cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], cpu_gpr_a[r2]);
tcg_gen_addi_i32(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_ST_DA_PREINC:
CHECK_REG_PAIR(r1);
temp = tcg_temp_new();
tcg_gen_addi_i32(temp, cpu_gpr_a[r2], off10);
- gen_st_2regs_64(cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], temp, ctx);
+ gen_st_2regs_64(ctx, cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], temp);
tcg_gen_mov_i32(cpu_gpr_a[r2], temp);
break;
case OPC2_32_BO_ST_H_SHORTOFF:
@@ -4413,7 +4413,7 @@ static void decode_bo_addrmode_bitreverse_circular(DisasContext *ctx)
break;
case OPC2_32_BO_ST_D_BR:
CHECK_REG_PAIR(r1);
- gen_st_2regs_64(cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], temp2, ctx);
+ gen_st_2regs_64(ctx, cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], temp2);
gen_helper_br_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1]);
break;
case OPC2_32_BO_ST_D_CIRC:
@@ -4428,7 +4428,7 @@ static void decode_bo_addrmode_bitreverse_circular(DisasContext *ctx)
break;
case OPC2_32_BO_ST_DA_BR:
CHECK_REG_PAIR(r1);
- gen_st_2regs_64(cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], temp2, ctx);
+ gen_st_2regs_64(ctx, cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], temp2);
gen_helper_br_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1]);
break;
case OPC2_32_BO_ST_DA_CIRC:
@@ -4520,36 +4520,36 @@ static void decode_bo_addrmode_ld_post_pre_base(DisasContext *ctx)
break;
case OPC2_32_BO_LD_D_SHORTOFF:
CHECK_REG_PAIR(r1);
- gen_offset_ld_2regs(cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], cpu_gpr_a[r2],
- off10, ctx);
+ gen_offset_ld_2regs(ctx, cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], cpu_gpr_a[r2],
+ off10);
break;
case OPC2_32_BO_LD_D_POSTINC:
CHECK_REG_PAIR(r1);
- gen_ld_2regs_64(cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx);
+ gen_ld_2regs_64(ctx, cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], cpu_gpr_a[r2]);
tcg_gen_addi_i32(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_LD_D_PREINC:
CHECK_REG_PAIR(r1);
temp = tcg_temp_new();
tcg_gen_addi_i32(temp, cpu_gpr_a[r2], off10);
- gen_ld_2regs_64(cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], temp, ctx);
+ gen_ld_2regs_64(ctx, cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], temp);
tcg_gen_mov_i32(cpu_gpr_a[r2], temp);
break;
case OPC2_32_BO_LD_DA_SHORTOFF:
CHECK_REG_PAIR(r1);
- gen_offset_ld_2regs(cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], cpu_gpr_a[r2],
- off10, ctx);
+ gen_offset_ld_2regs(ctx, cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], cpu_gpr_a[r2],
+ off10);
break;
case OPC2_32_BO_LD_DA_POSTINC:
CHECK_REG_PAIR(r1);
- gen_ld_2regs_64(cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx);
+ gen_ld_2regs_64(ctx, cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], cpu_gpr_a[r2]);
tcg_gen_addi_i32(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_LD_DA_PREINC:
CHECK_REG_PAIR(r1);
temp = tcg_temp_new();
tcg_gen_addi_i32(temp, cpu_gpr_a[r2], off10);
- gen_ld_2regs_64(cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], temp, ctx);
+ gen_ld_2regs_64(ctx, cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], temp);
tcg_gen_mov_i32(cpu_gpr_a[r2], temp);
break;
case OPC2_32_BO_LD_H_SHORTOFF:
@@ -4651,7 +4651,7 @@ static void decode_bo_addrmode_ld_bitreverse_circular(DisasContext *ctx)
break;
case OPC2_32_BO_LD_D_BR:
CHECK_REG_PAIR(r1);
- gen_ld_2regs_64(cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], temp2, ctx);
+ gen_ld_2regs_64(ctx, cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], temp2);
gen_helper_br_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1]);
break;
case OPC2_32_BO_LD_D_CIRC:
@@ -4666,7 +4666,7 @@ static void decode_bo_addrmode_ld_bitreverse_circular(DisasContext *ctx)
break;
case OPC2_32_BO_LD_DA_BR:
CHECK_REG_PAIR(r1);
- gen_ld_2regs_64(cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], temp2, ctx);
+ gen_ld_2regs_64(ctx, cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], temp2);
gen_helper_br_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1]);
break;
case OPC2_32_BO_LD_DA_CIRC:
@@ -8377,7 +8377,7 @@ static void tricore_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
tcg_gen_insn_start(ctx->base.pc_next);
}
-static bool insn_crosses_page(CPUTriCoreState *env, DisasContext *ctx)
+static bool insn_crosses_page(DisasContext *ctx, CPUTriCoreState *env)
{
/*
* Return true if the insn at ctx->base.pc_next might cross a page boundary.
@@ -8420,7 +8420,7 @@ static void tricore_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE
|| (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE - 3
- && insn_crosses_page(env, ctx))) {
+ && insn_crosses_page(ctx, env))) {
ctx->base.is_jmp = DISAS_TOO_MANY;
}
}
--
2.51.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 11/12] target/tricore: Un-inline various helpers
2025-10-10 5:21 [PATCH 00/12] target/tricore: Remove all uses of target_ulong types Philippe Mathieu-Daudé
` (9 preceding siblings ...)
2025-10-10 5:21 ` [PATCH 10/12] target/tricore: Pass DisasContext as first argument Philippe Mathieu-Daudé
@ 2025-10-10 5:21 ` Philippe Mathieu-Daudé
2025-10-10 17:07 ` Richard Henderson
2025-10-10 5:21 ` [PATCH 12/12] target/tricore: Expand TCGv type for 32-bit target Philippe Mathieu-Daudé
11 siblings, 1 reply; 25+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-10 5:21 UTC (permalink / raw)
To: qemu-devel
Cc: Bastian Koppelmann, Pierrick Bouvier, Anton Johansson,
Philippe Mathieu-Daudé
Rely on the linker to optimize at linking time.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/tricore/translate.c | 274 ++++++++++++++++++-------------------
1 file changed, 135 insertions(+), 139 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 595db14bb2b..677116cb6d9 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -201,7 +201,7 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f, int flags)
/* For two 32-bit registers used a 64-bit register, the first
registernumber needs to be even. Otherwise we trap. */
-static inline void generate_trap(DisasContext *ctx, int class, int tin);
+static void generate_trap(DisasContext *ctx, int class, int tin);
#define CHECK_REG_PAIR(reg) do { \
if (reg & 0x1) { \
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_OPD); \
@@ -210,16 +210,16 @@ static inline void generate_trap(DisasContext *ctx, int class, int tin);
/* Functions for load/save to/from memory */
-static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2,
- int16_t con, MemOp mop)
+static void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2,
+ int16_t con, MemOp mop)
{
TCGv temp = tcg_temp_new();
tcg_gen_addi_i32(temp, r2, con);
tcg_gen_qemu_ld_i32(r1, temp, ctx->mem_idx, mop);
}
-static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2,
- int16_t con, MemOp mop)
+static void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2,
+ int16_t con, MemOp mop)
{
TCGv temp = tcg_temp_new();
tcg_gen_addi_i32(temp, r2, con);
@@ -346,7 +346,7 @@ static void gen_swapmsk(DisasContext *ctx, int reg, TCGv ea)
break;
#define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE)
#define E(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE)
-static inline void gen_mfcr(DisasContext *ctx, TCGv ret, int32_t offset)
+static void gen_mfcr(DisasContext *ctx, TCGv ret, int32_t offset)
{
/* since we're caching PSW make this a special case */
if (offset == 0xfe04) {
@@ -374,8 +374,7 @@ static inline void gen_mfcr(DisasContext *ctx, TCGv ret, int32_t offset)
watchdog device, we handle endinit protected registers like
all-access registers for now. */
#define E(ADDRESS, REG, FEATURE) A(ADDRESS, REG, FEATURE)
-static inline void gen_mtcr(DisasContext *ctx, TCGv r1,
- int32_t offset)
+static void gen_mtcr(DisasContext *ctx, TCGv r1, int32_t offset)
{
if (ctx->priv == TRICORE_PRIV_SM) {
/* since we're caching PSW make this a special case */
@@ -394,7 +393,7 @@ static inline void gen_mtcr(DisasContext *ctx, TCGv r1,
/* Functions for arithmetic instructions */
-static inline void gen_add_d(TCGv ret, TCGv r1, TCGv r2)
+static void gen_add_d(TCGv ret, TCGv r1, TCGv r2)
{
TCGv t0 = tcg_temp_new_i32();
TCGv result = tcg_temp_new_i32();
@@ -415,7 +414,7 @@ static inline void gen_add_d(TCGv ret, TCGv r1, TCGv r2)
tcg_gen_mov_i32(ret, result);
}
-static inline void
+static void
gen_add64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2)
{
TCGv temp = tcg_temp_new();
@@ -441,7 +440,7 @@ gen_add64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2)
tcg_gen_mov_i64(ret, result);
}
-static inline void
+static void
gen_addsub64_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, void(*op1)(TCGv, TCGv, TCGv),
void(*op2)(TCGv, TCGv, TCGv))
@@ -488,7 +487,7 @@ gen_addsub64_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
}
/* ret = r2 + (r1 * r3); */
-static inline void gen_madd32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3)
+static void gen_madd32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3)
{
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 t2 = tcg_temp_new_i64();
@@ -519,13 +518,13 @@ static inline void gen_madd32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3)
tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
}
-static inline void gen_maddi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con)
+static void gen_maddi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con)
{
TCGv temp = tcg_constant_i32(con);
gen_madd32_d(ret, r1, r2, temp);
}
-static inline void
+static void
gen_madd64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
TCGv r3)
{
@@ -553,7 +552,7 @@ gen_madd64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
tcg_gen_mov_i32(ret_high, t4);
}
-static inline void
+static void
gen_maddu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
TCGv r3)
{
@@ -583,7 +582,7 @@ gen_maddu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
}
-static inline void
+static void
gen_maddi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
int32_t con)
{
@@ -591,7 +590,7 @@ gen_maddi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
gen_madd64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
}
-static inline void
+static void
gen_maddui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
int32_t con)
{
@@ -599,7 +598,7 @@ gen_maddui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
gen_maddu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
}
-static inline void
+static void
gen_madd_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
@@ -626,7 +625,7 @@ gen_madd_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
tcg_gen_add_tl, tcg_gen_add_tl);
}
-static inline void
+static void
gen_maddsu_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
@@ -653,7 +652,7 @@ gen_maddsu_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
tcg_gen_sub_tl, tcg_gen_add_tl);
}
-static inline void
+static void
gen_maddsum_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
@@ -686,9 +685,9 @@ gen_maddsum_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2);
}
-static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2);
+static void gen_adds(TCGv ret, TCGv r1, TCGv r2);
-static inline void
+static void
gen_madds_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
@@ -723,9 +722,9 @@ gen_madds_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
tcg_gen_or_i32(cpu_PSW_AV, cpu_PSW_AV, temp3);
}
-static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2);
+static void gen_subs(TCGv ret, TCGv r1, TCGv r2);
-static inline void
+static void
gen_maddsus_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
@@ -760,7 +759,7 @@ gen_maddsus_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
tcg_gen_or_i32(cpu_PSW_AV, cpu_PSW_AV, temp3);
}
-static inline void
+static void
gen_maddsums_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
@@ -793,7 +792,7 @@ gen_maddsums_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
}
-static inline void
+static void
gen_maddm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
@@ -821,7 +820,7 @@ gen_maddm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3);
}
-static inline void
+static void
gen_maddms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
@@ -847,7 +846,7 @@ gen_maddms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
}
-static inline void
+static void
gen_maddr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n,
uint32_t mode)
{
@@ -870,7 +869,7 @@ gen_maddr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n,
gen_helper_addr_h(ret, tcg_env, temp64, r1_low, r1_high);
}
-static inline void
+static void
gen_maddr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
{
TCGv temp = tcg_temp_new();
@@ -881,7 +880,7 @@ gen_maddr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
gen_maddr64_h(ret, temp, temp2, r2, r3, n, mode);
}
-static inline void
+static void
gen_maddsur32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
{
TCGv t_n = tcg_constant_i32(n);
@@ -908,7 +907,7 @@ gen_maddsur32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
}
-static inline void
+static void
gen_maddr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3,
uint32_t n, uint32_t mode)
{
@@ -931,7 +930,7 @@ gen_maddr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3,
gen_helper_addr_h_ssov(ret, tcg_env, temp64, r1_low, r1_high);
}
-static inline void
+static void
gen_maddr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
{
TCGv temp = tcg_temp_new();
@@ -942,7 +941,7 @@ gen_maddr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
gen_maddr64s_h(ret, temp, temp2, r2, r3, n, mode);
}
-static inline void
+static void
gen_maddsur32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
{
TCGv t_n = tcg_constant_i32(n);
@@ -968,21 +967,21 @@ gen_maddsur32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
gen_helper_addsur_h_ssov(ret, tcg_env, temp64, temp, temp2);
}
-static inline void
+static void
gen_maddr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
{
TCGv t_n = tcg_constant_i32(n);
gen_helper_maddr_q(ret, tcg_env, r1, r2, r3, t_n);
}
-static inline void
+static void
gen_maddrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
{
TCGv t_n = tcg_constant_i32(n);
gen_helper_maddr_q_ssov(ret, tcg_env, r1, r2, r3, t_n);
}
-static inline void
+static void
gen_madd32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
uint32_t up_shift)
{
@@ -1032,7 +1031,7 @@ gen_madd32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
tcg_gen_mov_i32(ret, temp3);
}
-static inline void
+static void
gen_m16add32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
{
TCGv temp = tcg_temp_new();
@@ -1049,7 +1048,7 @@ gen_m16add32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
gen_add_d(ret, arg1, temp);
}
-static inline void
+static void
gen_m16adds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
{
TCGv temp = tcg_temp_new();
@@ -1066,7 +1065,7 @@ gen_m16adds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
gen_adds(ret, arg1, temp);
}
-static inline void
+static void
gen_m16add64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
TCGv arg3, uint32_t n)
{
@@ -1093,7 +1092,7 @@ gen_m16add64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
tcg_gen_extr_i64_i32(rl, rh, t3);
}
-static inline void
+static void
gen_m16adds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
TCGv arg3, uint32_t n)
{
@@ -1119,7 +1118,7 @@ gen_m16adds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
tcg_gen_extr_i64_i32(rl, rh, t1);
}
-static inline void
+static void
gen_madd64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
TCGv arg3, uint32_t n)
{
@@ -1167,7 +1166,7 @@ gen_madd64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
}
-static inline void
+static void
gen_madds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
uint32_t up_shift)
{
@@ -1185,7 +1184,7 @@ gen_madds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
gen_helper_madd32_q_add_ssov(ret, tcg_env, t1, t2);
}
-static inline void
+static void
gen_madds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
TCGv arg3, uint32_t n)
{
@@ -1198,7 +1197,7 @@ gen_madds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
}
/* ret = r2 - (r1 * r3); */
-static inline void gen_msub32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3)
+static void gen_msub32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3)
{
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 t2 = tcg_temp_new_i64();
@@ -1230,13 +1229,13 @@ static inline void gen_msub32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3)
tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
}
-static inline void gen_msubi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con)
+static void gen_msubi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con)
{
TCGv temp = tcg_constant_i32(con);
gen_msub32_d(ret, r1, r2, temp);
}
-static inline void
+static void
gen_msub64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
TCGv r3)
{
@@ -1264,7 +1263,7 @@ gen_msub64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
tcg_gen_mov_i32(ret_high, t4);
}
-static inline void
+static void
gen_msubi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
int32_t con)
{
@@ -1272,7 +1271,7 @@ gen_msubi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
gen_msub64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
}
-static inline void
+static void
gen_msubu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
TCGv r3)
{
@@ -1300,7 +1299,7 @@ gen_msubu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
}
-static inline void
+static void
gen_msubui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
int32_t con)
{
@@ -1308,14 +1307,14 @@ gen_msubui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
gen_msubu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
}
-static inline void gen_addi_d(TCGv ret, TCGv r1, int32_t r2)
+static void gen_addi_d(TCGv ret, TCGv r1, int32_t r2)
{
TCGv temp = tcg_constant_i32(r2);
gen_add_d(ret, r1, temp);
}
/* calculate the carry bit too */
-static inline void gen_add_CC(TCGv ret, TCGv r1, TCGv r2)
+static void gen_add_CC(TCGv ret, TCGv r1, TCGv r2)
{
TCGv t0 = tcg_temp_new_i32();
TCGv result = tcg_temp_new_i32();
@@ -1338,13 +1337,13 @@ static inline void gen_add_CC(TCGv ret, TCGv r1, TCGv r2)
tcg_gen_mov_i32(ret, result);
}
-static inline void gen_addi_CC(TCGv ret, TCGv r1, int32_t con)
+static void gen_addi_CC(TCGv ret, TCGv r1, int32_t con)
{
TCGv temp = tcg_constant_i32(con);
gen_add_CC(ret, r1, temp);
}
-static inline void gen_addc_CC(TCGv ret, TCGv r1, TCGv r2)
+static void gen_addc_CC(TCGv ret, TCGv r1, TCGv r2)
{
TCGv t0 = tcg_temp_new_i32();
TCGv result = tcg_temp_new_i32();
@@ -1366,14 +1365,13 @@ static inline void gen_addc_CC(TCGv ret, TCGv r1, TCGv r2)
tcg_gen_mov_i32(ret, result);
}
-static inline void gen_addci_CC(TCGv ret, TCGv r1, int32_t con)
+static void gen_addci_CC(TCGv ret, TCGv r1, int32_t con)
{
TCGv temp = tcg_constant_i32(con);
gen_addc_CC(ret, r1, temp);
}
-static inline void gen_cond_add(TCGCond cond, TCGv r1, TCGv r2, TCGv r3,
- TCGv r4)
+static void gen_cond_add(TCGCond cond, TCGv r1, TCGv r2, TCGv r3, TCGv r4)
{
TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
@@ -1405,14 +1403,13 @@ static inline void gen_cond_add(TCGCond cond, TCGv r1, TCGv r2, TCGv r3,
tcg_gen_movcond_i32(cond, r3, r4, t0, result, r1);
}
-static inline void gen_condi_add(TCGCond cond, TCGv r1, int32_t r2,
- TCGv r3, TCGv r4)
+static void gen_condi_add(TCGCond cond, TCGv r1, int32_t r2, TCGv r3, TCGv r4)
{
TCGv temp = tcg_constant_i32(r2);
gen_cond_add(cond, r1, temp, r3, r4);
}
-static inline void gen_sub_d(TCGv ret, TCGv r1, TCGv r2)
+static void gen_sub_d(TCGv ret, TCGv r1, TCGv r2)
{
TCGv temp = tcg_temp_new_i32();
TCGv result = tcg_temp_new_i32();
@@ -1433,7 +1430,7 @@ static inline void gen_sub_d(TCGv ret, TCGv r1, TCGv r2)
tcg_gen_mov_i32(ret, result);
}
-static inline void
+static void
gen_sub64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2)
{
TCGv temp = tcg_temp_new();
@@ -1459,7 +1456,7 @@ gen_sub64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2)
tcg_gen_mov_i64(ret, result);
}
-static inline void gen_sub_CC(TCGv ret, TCGv r1, TCGv r2)
+static void gen_sub_CC(TCGv ret, TCGv r1, TCGv r2)
{
TCGv result = tcg_temp_new();
TCGv temp = tcg_temp_new();
@@ -1482,15 +1479,14 @@ static inline void gen_sub_CC(TCGv ret, TCGv r1, TCGv r2)
tcg_gen_mov_i32(ret, result);
}
-static inline void gen_subc_CC(TCGv ret, TCGv r1, TCGv r2)
+static void gen_subc_CC(TCGv ret, TCGv r1, TCGv r2)
{
TCGv temp = tcg_temp_new();
tcg_gen_not_i32(temp, r2);
gen_addc_CC(ret, r1, temp);
}
-static inline void gen_cond_sub(TCGCond cond, TCGv r1, TCGv r2, TCGv r3,
- TCGv r4)
+static void gen_cond_sub(TCGCond cond, TCGv r1, TCGv r2, TCGv r3, TCGv r4)
{
TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
@@ -1522,7 +1518,7 @@ static inline void gen_cond_sub(TCGCond cond, TCGv r1, TCGv r2, TCGv r3,
tcg_gen_movcond_i32(cond, r3, r4, t0, result, r1);
}
-static inline void
+static void
gen_msub_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
@@ -1549,7 +1545,7 @@ gen_msub_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
tcg_gen_sub_tl, tcg_gen_sub_tl);
}
-static inline void
+static void
gen_msubs_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
@@ -1584,7 +1580,7 @@ gen_msubs_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
tcg_gen_or_i32(cpu_PSW_AV, cpu_PSW_AV, temp3);
}
-static inline void
+static void
gen_msubm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
@@ -1612,7 +1608,7 @@ gen_msubm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3);
}
-static inline void
+static void
gen_msubms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
@@ -1638,7 +1634,7 @@ gen_msubms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
}
-static inline void
+static void
gen_msubr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n,
uint32_t mode)
{
@@ -1661,7 +1657,7 @@ gen_msubr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n,
gen_helper_subr_h(ret, tcg_env, temp64, r1_low, r1_high);
}
-static inline void
+static void
gen_msubr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
{
TCGv temp = tcg_temp_new();
@@ -1672,7 +1668,7 @@ gen_msubr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
gen_msubr64_h(ret, temp, temp2, r2, r3, n, mode);
}
-static inline void
+static void
gen_msubr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3,
uint32_t n, uint32_t mode)
{
@@ -1695,7 +1691,7 @@ gen_msubr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3,
gen_helper_subr_h_ssov(ret, tcg_env, temp64, r1_low, r1_high);
}
-static inline void
+static void
gen_msubr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
{
TCGv temp = tcg_temp_new();
@@ -1706,21 +1702,21 @@ gen_msubr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
gen_msubr64s_h(ret, temp, temp2, r2, r3, n, mode);
}
-static inline void
+static void
gen_msubr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
{
TCGv temp = tcg_constant_i32(n);
gen_helper_msubr_q(ret, tcg_env, r1, r2, r3, temp);
}
-static inline void
+static void
gen_msubrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
{
TCGv temp = tcg_constant_i32(n);
gen_helper_msubr_q_ssov(ret, tcg_env, r1, r2, r3, temp);
}
-static inline void
+static void
gen_msub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
uint32_t up_shift)
{
@@ -1761,7 +1757,7 @@ gen_msub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
tcg_gen_mov_i32(ret, temp3);
}
-static inline void
+static void
gen_m16sub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
{
TCGv temp = tcg_temp_new();
@@ -1778,7 +1774,7 @@ gen_m16sub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
gen_sub_d(ret, arg1, temp);
}
-static inline void
+static void
gen_m16subs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
{
TCGv temp = tcg_temp_new();
@@ -1795,7 +1791,7 @@ gen_m16subs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
gen_subs(ret, arg1, temp);
}
-static inline void
+static void
gen_m16sub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
TCGv arg3, uint32_t n)
{
@@ -1822,7 +1818,7 @@ gen_m16sub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
tcg_gen_extr_i64_i32(rl, rh, t3);
}
-static inline void
+static void
gen_m16subs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
TCGv arg3, uint32_t n)
{
@@ -1848,7 +1844,7 @@ gen_m16subs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
tcg_gen_extr_i64_i32(rl, rh, t1);
}
-static inline void
+static void
gen_msub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
TCGv arg3, uint32_t n)
{
@@ -1896,7 +1892,7 @@ gen_msub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
}
-static inline void
+static void
gen_msubs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
uint32_t up_shift)
{
@@ -1919,7 +1915,7 @@ gen_msubs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
gen_helper_msub32_q_sub_ssov(ret, tcg_env, t1, t3);
}
-static inline void
+static void
gen_msubs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
TCGv arg3, uint32_t n)
{
@@ -1931,7 +1927,7 @@ gen_msubs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
tcg_gen_extr_i64_i32(rl, rh, r1);
}
-static inline void
+static void
gen_msubad_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
@@ -1958,7 +1954,7 @@ gen_msubad_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
tcg_gen_add_tl, tcg_gen_sub_tl);
}
-static inline void
+static void
gen_msubadm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
@@ -1991,7 +1987,7 @@ gen_msubadm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2);
}
-static inline void
+static void
gen_msubadr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
{
TCGv t_n = tcg_constant_i32(n);
@@ -2017,7 +2013,7 @@ gen_msubadr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
gen_helper_subadr_h(ret, tcg_env, temp64, temp, temp2);
}
-static inline void
+static void
gen_msubads_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
@@ -2052,7 +2048,7 @@ gen_msubads_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
tcg_gen_or_i32(cpu_PSW_AV, cpu_PSW_AV, temp3);
}
-static inline void
+static void
gen_msubadms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
TCGv r3, uint32_t n, uint32_t mode)
{
@@ -2084,7 +2080,7 @@ gen_msubadms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
}
-static inline void
+static void
gen_msubadr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
{
TCGv t_n = tcg_constant_i32(n);
@@ -2110,7 +2106,7 @@ gen_msubadr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
gen_helper_subadr_h_ssov(ret, tcg_env, temp64, temp, temp2);
}
-static inline void gen_abs(TCGv ret, TCGv r1)
+static void gen_abs(TCGv ret, TCGv r1)
{
tcg_gen_abs_i32(ret, r1);
/* overflow can only happen, if r1 = 0x80000000 */
@@ -2125,7 +2121,7 @@ static inline void gen_abs(TCGv ret, TCGv r1)
tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
}
-static inline void gen_absdif(TCGv ret, TCGv r1, TCGv r2)
+static void gen_absdif(TCGv ret, TCGv r1, TCGv r2)
{
TCGv temp = tcg_temp_new_i32();
TCGv result = tcg_temp_new_i32();
@@ -2151,19 +2147,19 @@ static inline void gen_absdif(TCGv ret, TCGv r1, TCGv r2)
tcg_gen_mov_i32(ret, result);
}
-static inline void gen_absdifi(TCGv ret, TCGv r1, int32_t con)
+static void gen_absdifi(TCGv ret, TCGv r1, int32_t con)
{
TCGv temp = tcg_constant_i32(con);
gen_absdif(ret, r1, temp);
}
-static inline void gen_absdifsi(TCGv ret, TCGv r1, int32_t con)
+static void gen_absdifsi(TCGv ret, TCGv r1, int32_t con)
{
TCGv temp = tcg_constant_i32(con);
gen_helper_absdif_ssov(ret, tcg_env, r1, temp);
}
-static inline void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2)
+static void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2)
{
TCGv high = tcg_temp_new();
TCGv low = tcg_temp_new();
@@ -2183,13 +2179,13 @@ static inline void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2)
tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
}
-static inline void gen_muli_i32s(TCGv ret, TCGv r1, int32_t con)
+static void gen_muli_i32s(TCGv ret, TCGv r1, int32_t con)
{
TCGv temp = tcg_constant_i32(con);
gen_mul_i32s(ret, r1, temp);
}
-static inline void gen_mul_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2)
+static void gen_mul_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2)
{
tcg_gen_muls2_i32(ret_low, ret_high, r1, r2);
/* clear V bit */
@@ -2203,14 +2199,14 @@ static inline void gen_mul_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2)
tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
}
-static inline void gen_muli_i64s(TCGv ret_low, TCGv ret_high, TCGv r1,
+static void gen_muli_i64s(TCGv ret_low, TCGv ret_high, TCGv r1,
int32_t con)
{
TCGv temp = tcg_constant_i32(con);
gen_mul_i64s(ret_low, ret_high, r1, temp);
}
-static inline void gen_mul_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2)
+static void gen_mul_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2)
{
tcg_gen_mulu2_i32(ret_low, ret_high, r1, r2);
/* clear V bit */
@@ -2224,33 +2220,33 @@ static inline void gen_mul_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2)
tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
}
-static inline void gen_muli_i64u(TCGv ret_low, TCGv ret_high, TCGv r1,
+static void gen_muli_i64u(TCGv ret_low, TCGv ret_high, TCGv r1,
int32_t con)
{
TCGv temp = tcg_constant_i32(con);
gen_mul_i64u(ret_low, ret_high, r1, temp);
}
-static inline void gen_mulsi_i32(TCGv ret, TCGv r1, int32_t con)
+static void gen_mulsi_i32(TCGv ret, TCGv r1, int32_t con)
{
TCGv temp = tcg_constant_i32(con);
gen_helper_mul_ssov(ret, tcg_env, r1, temp);
}
-static inline void gen_mulsui_i32(TCGv ret, TCGv r1, int32_t con)
+static void gen_mulsui_i32(TCGv ret, TCGv r1, int32_t con)
{
TCGv temp = tcg_constant_i32(con);
gen_helper_mul_suov(ret, tcg_env, r1, temp);
}
/* gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); */
-static inline void gen_maddsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
+static void gen_maddsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
{
TCGv temp = tcg_constant_i32(con);
gen_helper_madd32_ssov(ret, tcg_env, r1, r2, temp);
}
-static inline void gen_maddsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
+static void gen_maddsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
{
TCGv temp = tcg_constant_i32(con);
gen_helper_madd32_suov(ret, tcg_env, r1, r2, temp);
@@ -2361,7 +2357,7 @@ static void gen_mulr_q(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n)
tcg_gen_andi_i32(ret, ret, 0xffff0000);
}
-static inline void
+static void
gen_madds_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
TCGv r3)
{
@@ -2371,7 +2367,7 @@ gen_madds_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
}
-static inline void
+static void
gen_maddsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
int32_t con)
{
@@ -2379,7 +2375,7 @@ gen_maddsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
gen_madds_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
}
-static inline void
+static void
gen_maddsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
TCGv r3)
{
@@ -2389,7 +2385,7 @@ gen_maddsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
}
-static inline void
+static void
gen_maddsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
int32_t con)
{
@@ -2397,19 +2393,19 @@ gen_maddsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
gen_maddsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
}
-static inline void gen_msubsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
+static void gen_msubsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
{
TCGv temp = tcg_constant_i32(con);
gen_helper_msub32_ssov(ret, tcg_env, r1, r2, temp);
}
-static inline void gen_msubsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
+static void gen_msubsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
{
TCGv temp = tcg_constant_i32(con);
gen_helper_msub32_suov(ret, tcg_env, r1, r2, temp);
}
-static inline void
+static void
gen_msubs_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
TCGv r3)
{
@@ -2419,7 +2415,7 @@ gen_msubs_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
}
-static inline void
+static void
gen_msubsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
int32_t con)
{
@@ -2427,7 +2423,7 @@ gen_msubsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
gen_msubs_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
}
-static inline void
+static void
gen_msubsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
TCGv r3)
{
@@ -2437,7 +2433,7 @@ gen_msubsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
}
-static inline void
+static void
gen_msubsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
int32_t con)
{
@@ -2589,37 +2585,37 @@ static void gen_sh_condi(int cond, TCGv ret, TCGv r1, int32_t con)
gen_sh_cond(cond, ret, r1, temp);
}
-static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2)
+static void gen_adds(TCGv ret, TCGv r1, TCGv r2)
{
gen_helper_add_ssov(ret, tcg_env, r1, r2);
}
-static inline void gen_addsi(TCGv ret, TCGv r1, int32_t con)
+static void gen_addsi(TCGv ret, TCGv r1, int32_t con)
{
TCGv temp = tcg_constant_i32(con);
gen_helper_add_ssov(ret, tcg_env, r1, temp);
}
-static inline void gen_addsui(TCGv ret, TCGv r1, int32_t con)
+static void gen_addsui(TCGv ret, TCGv r1, int32_t con)
{
TCGv temp = tcg_constant_i32(con);
gen_helper_add_suov(ret, tcg_env, r1, temp);
}
-static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2)
+static void gen_subs(TCGv ret, TCGv r1, TCGv r2)
{
gen_helper_sub_ssov(ret, tcg_env, r1, r2);
}
-static inline void gen_subsu(TCGv ret, TCGv r1, TCGv r2)
+static void gen_subsu(TCGv ret, TCGv r1, TCGv r2)
{
gen_helper_sub_suov(ret, tcg_env, r1, r2);
}
-static inline void gen_bit_2op(TCGv ret, TCGv r1, TCGv r2,
- int pos1, int pos2,
- void(*op1)(TCGv, TCGv, TCGv),
- void(*op2)(TCGv, TCGv, TCGv))
+static void gen_bit_2op(TCGv ret, TCGv r1, TCGv r2,
+ int pos1, int pos2,
+ void(*op1)(TCGv, TCGv, TCGv),
+ void(*op2)(TCGv, TCGv, TCGv))
{
TCGv temp1, temp2;
@@ -2636,9 +2632,9 @@ static inline void gen_bit_2op(TCGv ret, TCGv r1, TCGv r2,
}
/* ret = r1[pos1] op1 r2[pos2]; */
-static inline void gen_bit_1op(TCGv ret, TCGv r1, TCGv r2,
- int pos1, int pos2,
- void(*op1)(TCGv, TCGv, TCGv))
+static void gen_bit_1op(TCGv ret, TCGv r1, TCGv r2,
+ int pos1, int pos2,
+ void(*op1)(TCGv, TCGv, TCGv))
{
TCGv temp1, temp2;
@@ -2653,8 +2649,8 @@ static inline void gen_bit_1op(TCGv ret, TCGv r1, TCGv r2,
tcg_gen_andi_i32(ret, ret, 0x1);
}
-static inline void gen_accumulating_cond(int cond, TCGv ret, TCGv r1, TCGv r2,
- void(*op)(TCGv, TCGv, TCGv))
+static void gen_accumulating_cond(int cond, TCGv ret, TCGv r1, TCGv r2,
+ void(*op)(TCGv, TCGv, TCGv))
{
TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
@@ -2668,7 +2664,7 @@ static inline void gen_accumulating_cond(int cond, TCGv ret, TCGv r1, TCGv r2,
tcg_gen_deposit_i32(ret, ret, temp, 0, 1);
}
-static inline void
+static void
gen_accumulating_condi(int cond, TCGv ret, TCGv r1, int32_t con,
void(*op)(TCGv, TCGv, TCGv))
{
@@ -2676,7 +2672,7 @@ gen_accumulating_condi(int cond, TCGv ret, TCGv r1, int32_t con,
gen_accumulating_cond(cond, ret, r1, temp, op);
}
-static inline void gen_eqany_bi(TCGv ret, TCGv r1, int32_t con)
+static void gen_eqany_bi(TCGv ret, TCGv r1, int32_t con)
{
TCGv b0 = tcg_temp_new();
TCGv b1 = tcg_temp_new();
@@ -2705,7 +2701,7 @@ static inline void gen_eqany_bi(TCGv ret, TCGv r1, int32_t con)
tcg_gen_or_i32(ret, ret, b3);
}
-static inline void gen_eqany_hi(TCGv ret, TCGv r1, int32_t con)
+static void gen_eqany_hi(TCGv ret, TCGv r1, int32_t con)
{
TCGv h0 = tcg_temp_new();
TCGv h1 = tcg_temp_new();
@@ -2724,7 +2720,7 @@ static inline void gen_eqany_hi(TCGv ret, TCGv r1, int32_t con)
/* mask = ((1 << width) -1) << pos;
ret = (r1 & ~mask) | (r2 << pos) & mask); */
-static inline void gen_insert(TCGv ret, TCGv r1, TCGv r2, TCGv width, TCGv pos)
+static void gen_insert(TCGv ret, TCGv r1, TCGv r2, TCGv width, TCGv pos)
{
TCGv mask = tcg_temp_new();
TCGv temp = tcg_temp_new();
@@ -2740,7 +2736,7 @@ static inline void gen_insert(TCGv ret, TCGv r1, TCGv r2, TCGv width, TCGv pos)
tcg_gen_or_i32(ret, temp, temp2);
}
-static inline void gen_bsplit(TCGv rl, TCGv rh, TCGv r1)
+static void gen_bsplit(TCGv rl, TCGv rh, TCGv r1)
{
TCGv_i64 temp = tcg_temp_new_i64();
@@ -2748,7 +2744,7 @@ static inline void gen_bsplit(TCGv rl, TCGv rh, TCGv r1)
tcg_gen_extr_i64_i32(rl, rh, temp);
}
-static inline void gen_unpack(TCGv rl, TCGv rh, TCGv r1)
+static void gen_unpack(TCGv rl, TCGv rh, TCGv r1)
{
TCGv_i64 temp = tcg_temp_new_i64();
@@ -2756,7 +2752,7 @@ static inline void gen_unpack(TCGv rl, TCGv rh, TCGv r1)
tcg_gen_extr_i64_i32(rl, rh, temp);
}
-static inline void
+static void
gen_dvinit_b(DisasContext *ctx, TCGv rl, TCGv rh, TCGv r1, TCGv r2)
{
TCGv_i64 ret = tcg_temp_new_i64();
@@ -2769,7 +2765,7 @@ gen_dvinit_b(DisasContext *ctx, TCGv rl, TCGv rh, TCGv r1, TCGv r2)
tcg_gen_extr_i64_i32(rl, rh, ret);
}
-static inline void
+static void
gen_dvinit_h(DisasContext *ctx, TCGv rl, TCGv rh, TCGv r1, TCGv r2)
{
TCGv_i64 ret = tcg_temp_new_i64();
@@ -2812,7 +2808,7 @@ static void gen_calc_usb_mulr_h(TCGv arg)
/* helpers for generating program flow micro-ops */
-static inline void gen_save_pc(vaddr pc)
+static void gen_save_pc(vaddr pc)
{
tcg_gen_movi_i32(cpu_PC, pc);
}
@@ -2840,8 +2836,8 @@ static void generate_trap(DisasContext *ctx, int class, int tin)
ctx->base.is_jmp = DISAS_NORETURN;
}
-static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1,
- TCGv r2, int16_t address)
+static void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1,
+ TCGv r2, int16_t address)
{
TCGLabel *jumpLabel = gen_new_label();
tcg_gen_brcond_i32(cond, r1, r2, jumpLabel);
@@ -2852,8 +2848,8 @@ static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1,
gen_goto_tb(ctx, 0, ctx->base.pc_next + address * 2);
}
-static inline void gen_branch_condi(DisasContext *ctx, TCGCond cond, TCGv r1,
- int r2, int16_t address)
+static void gen_branch_condi(DisasContext *ctx, TCGCond cond, TCGv r1,
+ int r2, int16_t address)
{
TCGv temp = tcg_constant_i32(r2);
gen_branch_cond(ctx, cond, r1, temp, address);
--
2.51.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 12/12] target/tricore: Expand TCGv type for 32-bit target
2025-10-10 5:21 [PATCH 00/12] target/tricore: Remove all uses of target_ulong types Philippe Mathieu-Daudé
` (10 preceding siblings ...)
2025-10-10 5:21 ` [PATCH 11/12] target/tricore: Un-inline various helpers Philippe Mathieu-Daudé
@ 2025-10-10 5:21 ` Philippe Mathieu-Daudé
2025-10-10 17:09 ` Richard Henderson
11 siblings, 1 reply; 25+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-10 5:21 UTC (permalink / raw)
To: qemu-devel
Cc: Bastian Koppelmann, Pierrick Bouvier, Anton Johansson,
Philippe Mathieu-Daudé
The TriCore target is only built as 32-bit:
$ git grep TARGET_LONG_BITS configs/targets/tricore-*
configs/targets/tricore-softmmu.mak:2:TARGET_LONG_BITS=32
Replace:
TCGv -> TCGv_i32
tcg_temp_new -> tcg_temp_new_i32
This is a mechanical replacement, adapting style to pass
the checkpatch.pl script.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/tricore/translate.c | 1248 +++++++++++++++++++-----------------
1 file changed, 642 insertions(+), 606 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 677116cb6d9..5fe71a57c8f 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -136,9 +136,9 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f, int flags)
} while (0)
#define GEN_HELPER_LL(name, ret, arg0, arg1, n) do { \
- TCGv arg00 = tcg_temp_new(); \
- TCGv arg01 = tcg_temp_new(); \
- TCGv arg11 = tcg_temp_new(); \
+ TCGv_i32 arg00 = tcg_temp_new_i32(); \
+ TCGv_i32 arg01 = tcg_temp_new_i32(); \
+ TCGv_i32 arg11 = tcg_temp_new_i32(); \
tcg_gen_sari_i32(arg00, arg0, 16); \
tcg_gen_ext16s_i32(arg01, arg0); \
tcg_gen_ext16s_i32(arg11, arg1); \
@@ -146,10 +146,10 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f, int flags)
} while (0)
#define GEN_HELPER_LU(name, ret, arg0, arg1, n) do { \
- TCGv arg00 = tcg_temp_new(); \
- TCGv arg01 = tcg_temp_new(); \
- TCGv arg10 = tcg_temp_new(); \
- TCGv arg11 = tcg_temp_new(); \
+ TCGv_i32 arg00 = tcg_temp_new_i32(); \
+ TCGv_i32 arg01 = tcg_temp_new_i32(); \
+ TCGv_i32 arg10 = tcg_temp_new_i32(); \
+ TCGv_i32 arg11 = tcg_temp_new_i32(); \
tcg_gen_sari_i32(arg00, arg0, 16); \
tcg_gen_ext16s_i32(arg01, arg0); \
tcg_gen_sari_i32(arg11, arg1, 16); \
@@ -158,10 +158,10 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f, int flags)
} while (0)
#define GEN_HELPER_UL(name, ret, arg0, arg1, n) do { \
- TCGv arg00 = tcg_temp_new(); \
- TCGv arg01 = tcg_temp_new(); \
- TCGv arg10 = tcg_temp_new(); \
- TCGv arg11 = tcg_temp_new(); \
+ TCGv_i32 arg00 = tcg_temp_new_i32(); \
+ TCGv_i32 arg01 = tcg_temp_new_i32(); \
+ TCGv_i32 arg10 = tcg_temp_new_i32(); \
+ TCGv_i32 arg11 = tcg_temp_new_i32(); \
tcg_gen_sari_i32(arg00, arg0, 16); \
tcg_gen_ext16s_i32(arg01, arg0); \
tcg_gen_sari_i32(arg10, arg1, 16); \
@@ -170,9 +170,9 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f, int flags)
} while (0)
#define GEN_HELPER_UU(name, ret, arg0, arg1, n) do { \
- TCGv arg00 = tcg_temp_new(); \
- TCGv arg01 = tcg_temp_new(); \
- TCGv arg11 = tcg_temp_new(); \
+ TCGv_i32 arg00 = tcg_temp_new_i32(); \
+ TCGv_i32 arg01 = tcg_temp_new_i32(); \
+ TCGv_i32 arg11 = tcg_temp_new_i32(); \
tcg_gen_sari_i32(arg01, arg0, 16); \
tcg_gen_ext16s_i32(arg00, arg0); \
tcg_gen_sari_i32(arg11, arg1, 16); \
@@ -210,23 +210,24 @@ static void generate_trap(DisasContext *ctx, int class, int tin);
/* Functions for load/save to/from memory */
-static void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2,
+static void gen_offset_ld(DisasContext *ctx, TCGv_i32 r1, TCGv_i32 r2,
int16_t con, MemOp mop)
{
- TCGv temp = tcg_temp_new();
+ TCGv_i32 temp = tcg_temp_new_i32();
tcg_gen_addi_i32(temp, r2, con);
tcg_gen_qemu_ld_i32(r1, temp, ctx->mem_idx, mop);
}
-static void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2,
+static void gen_offset_st(DisasContext *ctx, TCGv_i32 r1, TCGv_i32 r2,
int16_t con, MemOp mop)
{
- TCGv temp = tcg_temp_new();
+ TCGv_i32 temp = tcg_temp_new_i32();
tcg_gen_addi_i32(temp, r2, con);
tcg_gen_qemu_st_i32(r1, temp, ctx->mem_idx, mop);
}
-static void gen_st_2regs_64(DisasContext *ctx, TCGv rh, TCGv rl, TCGv address)
+static void gen_st_2regs_64(DisasContext *ctx, TCGv_i32 rh, TCGv_i32 rl,
+ TCGv_i32 address)
{
TCGv_i64 temp = tcg_temp_new_i64();
@@ -235,14 +236,16 @@ static void gen_st_2regs_64(DisasContext *ctx, TCGv rh, TCGv rl, TCGv address)
}
static void gen_offset_st_2regs(DisasContext *ctx,
- TCGv rh, TCGv rl, TCGv base, int16_t con)
+ TCGv_i32 rh, TCGv_i32 rl,
+ TCGv_i32 base, int16_t con)
{
- TCGv temp = tcg_temp_new();
+ TCGv_i32 temp = tcg_temp_new_i32();
tcg_gen_addi_i32(temp, base, con);
gen_st_2regs_64(ctx, rh, rl, temp);
}
-static void gen_ld_2regs_64(DisasContext *ctx, TCGv rh, TCGv rl, TCGv address)
+static void gen_ld_2regs_64(DisasContext *ctx, TCGv_i32 rh, TCGv_i32 rl,
+ TCGv_i32 address)
{
TCGv_i64 temp = tcg_temp_new_i64();
@@ -252,36 +255,37 @@ static void gen_ld_2regs_64(DisasContext *ctx, TCGv rh, TCGv rl, TCGv address)
}
static void gen_offset_ld_2regs(DisasContext *ctx,
- TCGv rh, TCGv rl, TCGv base, int16_t con)
+ TCGv_i32 rh, TCGv_i32 rl,
+ TCGv_i32 base, int16_t con)
{
- TCGv temp = tcg_temp_new();
+ TCGv_i32 temp = tcg_temp_new_i32();
tcg_gen_addi_i32(temp, base, con);
gen_ld_2regs_64(ctx, rh, rl, temp);
}
-static void gen_st_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,
- MemOp mop)
+static void gen_st_preincr(DisasContext *ctx, TCGv_i32 r1, TCGv_i32 r2,
+ int16_t off, MemOp mop)
{
- TCGv temp = tcg_temp_new();
+ TCGv_i32 temp = tcg_temp_new_i32();
tcg_gen_addi_i32(temp, r2, off);
tcg_gen_qemu_st_i32(r1, temp, ctx->mem_idx, mop);
tcg_gen_mov_i32(r2, temp);
}
-static void gen_ld_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,
- MemOp mop)
+static void gen_ld_preincr(DisasContext *ctx, TCGv_i32 r1, TCGv_i32 r2,
+ int16_t off, MemOp mop)
{
- TCGv temp = tcg_temp_new();
+ TCGv_i32 temp = tcg_temp_new_i32();
tcg_gen_addi_i32(temp, r2, off);
tcg_gen_qemu_ld_i32(r1, temp, ctx->mem_idx, mop);
tcg_gen_mov_i32(r2, temp);
}
/* M(EA, word) = (M(EA, word) & ~E[a][63:32]) | (E[a][31:0] & E[a][63:32]); */
-static void gen_ldmst(DisasContext *ctx, int ereg, TCGv ea)
+static void gen_ldmst(DisasContext *ctx, int ereg, TCGv_i32 ea)
{
- TCGv temp = tcg_temp_new();
- TCGv temp2 = tcg_temp_new();
+ TCGv_i32 temp = tcg_temp_new_i32();
+ TCGv_i32 temp2 = tcg_temp_new_i32();
CHECK_REG_PAIR(ereg);
/* temp = (M(EA, word) */
@@ -299,19 +303,19 @@ static void gen_ldmst(DisasContext *ctx, int ereg, TCGv ea)
/* tmp = M(EA, word);
M(EA, word) = D[a];
D[a] = tmp[31:0];*/
-static void gen_swap(DisasContext *ctx, int reg, TCGv ea)
+static void gen_swap(DisasContext *ctx, int reg, TCGv_i32 ea)
{
- TCGv temp = tcg_temp_new();
+ TCGv_i32 temp = tcg_temp_new_i32();
tcg_gen_qemu_ld_i32(temp, ea, ctx->mem_idx, MO_LEUL);
tcg_gen_qemu_st_i32(cpu_gpr_d[reg], ea, ctx->mem_idx, MO_LEUL);
tcg_gen_mov_i32(cpu_gpr_d[reg], temp);
}
-static void gen_cmpswap(DisasContext *ctx, int reg, TCGv ea)
+static void gen_cmpswap(DisasContext *ctx, int reg, TCGv_i32 ea)
{
- TCGv temp = tcg_temp_new();
- TCGv temp2 = tcg_temp_new();
+ TCGv_i32 temp = tcg_temp_new_i32();
+ TCGv_i32 temp2 = tcg_temp_new_i32();
CHECK_REG_PAIR(reg);
tcg_gen_qemu_ld_i32(temp, ea, ctx->mem_idx, MO_LEUL);
tcg_gen_movcond_i32(TCG_COND_EQ, temp2, cpu_gpr_d[reg + 1], temp,
@@ -320,11 +324,11 @@ static void gen_cmpswap(DisasContext *ctx, int reg, TCGv ea)
tcg_gen_mov_i32(cpu_gpr_d[reg], temp);
}
-static void gen_swapmsk(DisasContext *ctx, int reg, TCGv ea)
+static void gen_swapmsk(DisasContext *ctx, int reg, TCGv_i32 ea)
{
- TCGv temp = tcg_temp_new();
- TCGv temp2 = tcg_temp_new();
- TCGv temp3 = tcg_temp_new();
+ TCGv_i32 temp = tcg_temp_new_i32();
+ TCGv_i32 temp2 = tcg_temp_new_i32();
+ TCGv_i32 temp3 = tcg_temp_new_i32();
CHECK_REG_PAIR(reg);
tcg_gen_qemu_ld_i32(temp, ea, ctx->mem_idx, MO_LEUL);
tcg_gen_and_i32(temp2, cpu_gpr_d[reg], cpu_gpr_d[reg + 1]);
@@ -346,7 +350,7 @@ static void gen_swapmsk(DisasContext *ctx, int reg, TCGv ea)
break;
#define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE)
#define E(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE)
-static void gen_mfcr(DisasContext *ctx, TCGv ret, int32_t offset)
+static void gen_mfcr(DisasContext *ctx, TCGv_i32 ret, int32_t offset)
{
/* since we're caching PSW make this a special case */
if (offset == 0xfe04) {
@@ -374,7 +378,7 @@ static void gen_mfcr(DisasContext *ctx, TCGv ret, int32_t offset)
watchdog device, we handle endinit protected registers like
all-access registers for now. */
#define E(ADDRESS, REG, FEATURE) A(ADDRESS, REG, FEATURE)
-static void gen_mtcr(DisasContext *ctx, TCGv r1, int32_t offset)
+static void gen_mtcr(DisasContext *ctx, TCGv_i32 r1, int32_t offset)
{
if (ctx->priv == TRICORE_PRIV_SM) {
/* since we're caching PSW make this a special case */
@@ -393,10 +397,10 @@ static void gen_mtcr(DisasContext *ctx, TCGv r1, int32_t offset)
/* Functions for arithmetic instructions */
-static void gen_add_d(TCGv ret, TCGv r1, TCGv r2)
+static void gen_add_d(TCGv_i32 ret, TCGv_i32 r1, TCGv_i32 r2)
{
- TCGv t0 = tcg_temp_new_i32();
- TCGv result = tcg_temp_new_i32();
+ TCGv_i32 t0 = tcg_temp_new_i32();
+ TCGv_i32 result = tcg_temp_new_i32();
/* Addition and set V/SV bits */
tcg_gen_add_i32(result, r1, r2);
/* calc V bit */
@@ -414,10 +418,9 @@ static void gen_add_d(TCGv ret, TCGv r1, TCGv r2)
tcg_gen_mov_i32(ret, result);
}
-static void
-gen_add64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2)
+static void gen_add64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2)
{
- TCGv temp = tcg_temp_new();
+ TCGv_i32 temp = tcg_temp_new_i32();
TCGv_i64 t0 = tcg_temp_new_i64();
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 result = tcg_temp_new_i64();
@@ -440,15 +443,16 @@ gen_add64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2)
tcg_gen_mov_i64(ret, result);
}
-static void
-gen_addsub64_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
- TCGv r3, void(*op1)(TCGv, TCGv, TCGv),
- void(*op2)(TCGv, TCGv, TCGv))
+static void gen_addsub64_h(TCGv_i32 ret_low, TCGv_i32 ret_high,
+ TCGv_i32 r1_low, TCGv_i32 r1_high,
+ TCGv_i32 r2, TCGv_i32 r3,
+ void(*op1)(TCGv_i32, TCGv_i32, TCGv_i32),
+ void(*op2)(TCGv_i32, TCGv_i32, TCGv_i32))
{
- TCGv temp = tcg_temp_new();
- TCGv temp2 = tcg_temp_new();
- TCGv temp3 = tcg_temp_new();
- TCGv temp4 = tcg_temp_new();
+ TCGv_i32 temp = tcg_temp_new_i32();
+ TCGv_i32 temp2 = tcg_temp_new_i32();
+ TCGv_i32 temp3 = tcg_temp_new_i32();
+ TCGv_i32 temp4 = tcg_temp_new_i32();
(*op1)(temp, r1_low, r2);
/* calc V0 bit */
@@ -487,7 +491,7 @@ gen_addsub64_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
}
/* ret = r2 + (r1 * r3); */
-static void gen_madd32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3)
+static void gen_madd32_d(TCGv_i32 ret, TCGv_i32 r1, TCGv_i32 r2, TCGv_i32 r3)
{
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 t2 = tcg_temp_new_i64();
@@ -518,20 +522,19 @@ static void gen_madd32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3)
tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
}
-static void gen_maddi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con)
+static void gen_maddi32_d(TCGv_i32 ret, TCGv_i32 r1, TCGv_i32 r2, int32_t con)
{
- TCGv temp = tcg_constant_i32(con);
+ TCGv_i32 temp = tcg_constant_i32(con);
gen_madd32_d(ret, r1, r2, temp);
}
-static void
-gen_madd64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
- TCGv r3)
+static void gen_madd64_d(TCGv_i32 ret_low, TCGv_i32 ret_high, TCGv_i32 r1,
+ TCGv_i32 r2_low, TCGv_i32 r2_high, TCGv_i32 r3)
{
- TCGv t1 = tcg_temp_new();
- TCGv t2 = tcg_temp_new();
- TCGv t3 = tcg_temp_new();
- TCGv t4 = tcg_temp_new();
+ TCGv_i32 t1 = tcg_temp_new_i32();
+ TCGv_i32 t2 = tcg_temp_new_i32();
+ TCGv_i32 t3 = tcg_temp_new_i32();
+ TCGv_i32 t4 = tcg_temp_new_i32();
tcg_gen_muls2_i32(t1, t2, r1, r3);
/* only the add can overflow */
@@ -552,9 +555,8 @@ gen_madd64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
tcg_gen_mov_i32(ret_high, t4);
}
-static void
-gen_maddu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
- TCGv r3)
+static void gen_maddu64_d(TCGv_i32 ret_low, TCGv_i32 ret_high, TCGv_i32 r1,
+ TCGv_i32 r2_low, TCGv_i32 r2_high, TCGv_i32 r3)
{
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 t2 = tcg_temp_new_i64();
@@ -582,29 +584,28 @@ gen_maddu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
}
-static void
-gen_maddi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
- int32_t con)
+static void gen_maddi64_d(TCGv_i32 ret_low, TCGv_i32 ret_high, TCGv_i32 r1,
+ TCGv_i32 r2_low, TCGv_i32 r2_high, int32_t con)
{
- TCGv temp = tcg_constant_i32(con);
+ TCGv_i32 temp = tcg_constant_i32(con);
gen_madd64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
}
-static void
-gen_maddui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
- int32_t con)
+static void gen_maddui64_d(TCGv_i32 ret_low, TCGv_i32 ret_high, TCGv_i32 r1,
+ TCGv_i32 r2_low, TCGv_i32 r2_high, int32_t con)
{
- TCGv temp = tcg_constant_i32(con);
+ TCGv_i32 temp = tcg_constant_i32(con);
gen_maddu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
}
-static void
-gen_madd_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
- TCGv r3, uint32_t n, uint32_t mode)
+static void gen_madd_h(TCGv_i32 ret_low, TCGv_i32 ret_high,
+ TCGv_i32 r1_low, TCGv_i32 r1_high,
+ TCGv_i32 r2, TCGv_i32 r3,
+ uint32_t n, uint32_t mode)
{
- TCGv t_n = tcg_constant_i32(n);
- TCGv temp = tcg_temp_new();
- TCGv temp2 = tcg_temp_new();
+ TCGv_i32 t_n = tcg_constant_i32(n);
+ TCGv_i32 temp = tcg_temp_new_i32();
+ TCGv_i32 temp2 = tcg_temp_new_i32();
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
@@ -625,13 +626,14 @@ gen_madd_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
tcg_gen_add_tl, tcg_gen_add_tl);
}
-static void
-gen_maddsu_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
- TCGv r3, uint32_t n, uint32_t mode)
+static void gen_maddsu_h(TCGv_i32 ret_low, TCGv_i32 ret_high,
+ TCGv_i32 r1_low, TCGv_i32 r1_high,
+ TCGv_i32 r2, TCGv_i32 r3,
+ uint32_t n, uint32_t mode)
{
- TCGv t_n = tcg_constant_i32(n);
- TCGv temp = tcg_temp_new();
- TCGv temp2 = tcg_temp_new();
+ TCGv_i32 t_n = tcg_constant_i32(n);
+ TCGv_i32 temp = tcg_temp_new_i32();
+ TCGv_i32 temp2 = tcg_temp_new_i32();
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
@@ -652,11 +654,12 @@ gen_maddsu_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
tcg_gen_sub_tl, tcg_gen_add_tl);
}
-static void
-gen_maddsum_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
- TCGv r3, uint32_t n, uint32_t mode)
+static void gen_maddsum_h(TCGv_i32 ret_low, TCGv_i32 ret_high,
+ TCGv_i32 r1_low, TCGv_i32 r1_high,
+ TCGv_i32 r2, TCGv_i32 r3,
+ uint32_t n, uint32_t mode)
{
- TCGv t_n = tcg_constant_i32(n);
+ TCGv_i32 t_n = tcg_constant_i32(n);
TCGv_i64 temp64 = tcg_temp_new_i64();
TCGv_i64 temp64_2 = tcg_temp_new_i64();
TCGv_i64 temp64_3 = tcg_temp_new_i64();
@@ -685,16 +688,17 @@ gen_maddsum_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2);
}
-static void gen_adds(TCGv ret, TCGv r1, TCGv r2);
+static void gen_adds(TCGv_i32 ret, TCGv_i32 r1, TCGv_i32 r2);
-static void
-gen_madds_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
- TCGv r3, uint32_t n, uint32_t mode)
+static void gen_madds_h(TCGv_i32 ret_low, TCGv_i32 ret_high,
+ TCGv_i32 r1_low, TCGv_i32 r1_high,
+ TCGv_i32 r2, TCGv_i32 r3,
+ uint32_t n, uint32_t mode)
{
- TCGv t_n = tcg_constant_i32(n);
- TCGv temp = tcg_temp_new();
- TCGv temp2 = tcg_temp_new();
- TCGv temp3 = tcg_temp_new();
+ TCGv_i32 t_n = tcg_constant_i32(n);
+ TCGv_i32 temp = tcg_temp_new_i32();
+ TCGv_i32 temp2 = tcg_temp_new_i32();
+ TCGv_i32 temp3 = tcg_temp_new_i32();
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
@@ -722,16 +726,17 @@ gen_madds_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
tcg_gen_or_i32(cpu_PSW_AV, cpu_PSW_AV, temp3);
}
-static void gen_subs(TCGv ret, TCGv r1, TCGv r2);
+static void gen_subs(TCGv_i32 ret, TCGv_i32 r1, TCGv_i32 r2);
-static void
-gen_maddsus_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
- TCGv r3, uint32_t n, uint32_t mode)
+static void gen_maddsus_h(TCGv_i32 ret_low, TCGv_i32 ret_high,
+ TCGv_i32 r1_low, TCGv_i32 r1_high,
+ TCGv_i32 r2, TCGv_i32 r3,
+ uint32_t n, uint32_t mode)
{
- TCGv t_n = tcg_constant_i32(n);
- TCGv temp = tcg_temp_new();
- TCGv temp2 = tcg_temp_new();
- TCGv temp3 = tcg_temp_new();
+ TCGv_i32 t_n = tcg_constant_i32(n);
+ TCGv_i32 temp = tcg_temp_new_i32();
+ TCGv_i32 temp2 = tcg_temp_new_i32();
+ TCGv_i32 temp3 = tcg_temp_new_i32();
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
@@ -759,11 +764,12 @@ gen_maddsus_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
tcg_gen_or_i32(cpu_PSW_AV, cpu_PSW_AV, temp3);
}
-static void
-gen_maddsums_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
- TCGv r3, uint32_t n, uint32_t mode)
+static void gen_maddsums_h(TCGv_i32 ret_low, TCGv_i32 ret_high,
+ TCGv_i32 r1_low, TCGv_i32 r1_high,
+ TCGv_i32 r2, TCGv_i32 r3,
+ uint32_t n, uint32_t mode)
{
- TCGv t_n = tcg_constant_i32(n);
+ TCGv_i32 t_n = tcg_constant_i32(n);
TCGv_i64 temp64 = tcg_temp_new_i64();
TCGv_i64 temp64_2 = tcg_temp_new_i64();
@@ -792,11 +798,12 @@ gen_maddsums_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
}
-static void
-gen_maddm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
- TCGv r3, uint32_t n, uint32_t mode)
+static void gen_maddm_h(TCGv_i32 ret_low, TCGv_i32 ret_high,
+ TCGv_i32 r1_low, TCGv_i32 r1_high,
+ TCGv_i32 r2, TCGv_i32 r3,
+ uint32_t n, uint32_t mode)
{
- TCGv t_n = tcg_constant_i32(n);
+ TCGv_i32 t_n = tcg_constant_i32(n);
TCGv_i64 temp64 = tcg_temp_new_i64();
TCGv_i64 temp64_2 = tcg_temp_new_i64();
TCGv_i64 temp64_3 = tcg_temp_new_i64();
@@ -820,11 +827,12 @@ gen_maddm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3);
}
-static void
-gen_maddms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
- TCGv r3, uint32_t n, uint32_t mode)
+static void gen_maddms_h(TCGv_i32 ret_low, TCGv_i32 ret_high,
+ TCGv_i32 r1_low, TCGv_i32 r1_high,
+ TCGv_i32 r2, TCGv_i32 r3,
+ uint32_t n, uint32_t mode)
{
- TCGv t_n = tcg_constant_i32(n);
+ TCGv_i32 t_n = tcg_constant_i32(n);
TCGv_i64 temp64 = tcg_temp_new_i64();
TCGv_i64 temp64_2 = tcg_temp_new_i64();
switch (mode) {
@@ -846,11 +854,11 @@ gen_maddms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
}
-static void
-gen_maddr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n,
- uint32_t mode)
+static void gen_maddr64_h(TCGv_i32 ret, TCGv_i32 r1_low, TCGv_i32 r1_high,
+ TCGv_i32 r2, TCGv_i32 r3,
+ uint32_t n, uint32_t mode)
{
- TCGv t_n = tcg_constant_i32(n);
+ TCGv_i32 t_n = tcg_constant_i32(n);
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
@@ -869,23 +877,25 @@ gen_maddr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n,
gen_helper_addr_h(ret, tcg_env, temp64, r1_low, r1_high);
}
-static void
-gen_maddr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
+static void gen_maddr32_h(TCGv_i32 ret,
+ TCGv_i32 r1, TCGv_i32 r2, TCGv_i32 r3,
+ uint32_t n, uint32_t mode)
{
- TCGv temp = tcg_temp_new();
- TCGv temp2 = tcg_temp_new();
+ TCGv_i32 temp = tcg_temp_new_i32();
+ TCGv_i32 temp2 = tcg_temp_new_i32();
tcg_gen_andi_i32(temp2, r1, 0xffff0000);
tcg_gen_shli_i32(temp, r1, 16);
gen_maddr64_h(ret, temp, temp2, r2, r3, n, mode);
}
-static void
-gen_maddsur32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
+static void gen_maddsur32_h(TCGv_i32 ret,
+ TCGv_i32 r1, TCGv_i32 r2, TCGv_i32 r3,
+ uint32_t n, uint32_t mode)
{
- TCGv t_n = tcg_constant_i32(n);
- TCGv temp = tcg_temp_new();
- TCGv temp2 = tcg_temp_new();
+ TCGv_i32 t_n = tcg_constant_i32(n);
+ TCGv_i32 temp = tcg_temp_new_i32();
+ TCGv_i32 temp2 = tcg_temp_new_i32();
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
@@ -907,11 +917,11 @@ gen_maddsur32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
}
-static void
-gen_maddr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3,
- uint32_t n, uint32_t mode)
+static void gen_maddr64s_h(TCGv_i32 ret, TCGv_i32 r1_low, TCGv_i32 r1_high,
+ TCGv_i32 r2, TCGv_i32 r3,
+ uint32_t n, uint32_t mode)
{
- TCGv t_n = tcg_constant_i32(n);
+ TCGv_i32 t_n = tcg_constant_i32(n);
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
@@ -930,23 +940,25 @@ gen_maddr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3,
gen_helper_addr_h_ssov(ret, tcg_env, temp64, r1_low, r1_high);
}
-static void
-gen_maddr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
+static void gen_maddr32s_h(TCGv_i32 ret,
+ TCGv_i32 r1, TCGv_i32 r2, TCGv_i32 r3,
+ uint32_t n, uint32_t mode)
{
- TCGv temp = tcg_temp_new();
- TCGv temp2 = tcg_temp_new();
+ TCGv_i32 temp = tcg_temp_new_i32();
+ TCGv_i32 temp2 = tcg_temp_new_i32();
tcg_gen_andi_i32(temp2, r1, 0xffff0000);
tcg_gen_shli_i32(temp, r1, 16);
gen_maddr64s_h(ret, temp, temp2, r2, r3, n, mode);
}
-static void
-gen_maddsur32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
+static void gen_maddsur32s_h(TCGv_i32 ret,
+ TCGv_i32 r1, TCGv_i32 r2, TCGv_i32 r3,
+ uint32_t n, uint32_t mode)
{
- TCGv t_n = tcg_constant_i32(n);
- TCGv temp = tcg_temp_new();
- TCGv temp2 = tcg_temp_new();
+ TCGv_i32 t_n = tcg_constant_i32(n);
+ TCGv_i32 temp = tcg_temp_new_i32();
+ TCGv_i32 temp2 = tcg_temp_new_i32();
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
@@ -967,27 +979,27 @@ gen_maddsur32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
gen_helper_addsur_h_ssov(ret, tcg_env, temp64, temp, temp2);
}
-static void
-gen_maddr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
+static void gen_maddr_q(TCGv_i32 ret, TCGv_i32 r1, TCGv_i32 r2, TCGv_i32 r3,
+ uint32_t n)
{
- TCGv t_n = tcg_constant_i32(n);
+ TCGv_i32 t_n = tcg_constant_i32(n);
gen_helper_maddr_q(ret, tcg_env, r1, r2, r3, t_n);
}
-static void
-gen_maddrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
+static void gen_maddrs_q(TCGv_i32 ret, TCGv_i32 r1, TCGv_i32 r2, TCGv_i32 r3,
+ uint32_t n)
{
- TCGv t_n = tcg_constant_i32(n);
+ TCGv_i32 t_n = tcg_constant_i32(n);
gen_helper_maddr_q_ssov(ret, tcg_env, r1, r2, r3, t_n);
}
-static void
-gen_madd32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
- uint32_t up_shift)
+static void gen_madd32_q(TCGv_i32 ret,
+ TCGv_i32 arg1, TCGv_i32 arg2, TCGv_i32 arg3,
+ uint32_t n, uint32_t up_shift)
{
- TCGv temp = tcg_temp_new();
- TCGv temp2 = tcg_temp_new();
- TCGv temp3 = tcg_temp_new();
+ TCGv_i32 temp = tcg_temp_new_i32();
+ TCGv_i32 temp2 = tcg_temp_new_i32();
+ TCGv_i32 temp3 = tcg_temp_new_i32();
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 t2 = tcg_temp_new_i64();
TCGv_i64 t3 = tcg_temp_new_i64();
@@ -1031,11 +1043,12 @@ gen_madd32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
tcg_gen_mov_i32(ret, temp3);
}
-static void
-gen_m16add32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
+static void gen_m16add32_q(TCGv_i32 ret,
+ TCGv_i32 arg1, TCGv_i32 arg2, TCGv_i32 arg3,
+ uint32_t n)
{
- TCGv temp = tcg_temp_new();
- TCGv temp2 = tcg_temp_new();
+ TCGv_i32 temp = tcg_temp_new_i32();
+ TCGv_i32 temp2 = tcg_temp_new_i32();
if (n == 0) {
tcg_gen_mul_i32(temp, arg2, arg3);
} else { /* n is expected to be 1 */
@@ -1048,11 +1061,12 @@ gen_m16add32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
gen_add_d(ret, arg1, temp);
}
-static void
-gen_m16adds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
+static void gen_m16adds32_q(TCGv_i32 ret,
+ TCGv_i32 arg1, TCGv_i32 arg2, TCGv_i32 arg3,
+ uint32_t n)
{
- TCGv temp = tcg_temp_new();
- TCGv temp2 = tcg_temp_new();
+ TCGv_i32 temp = tcg_temp_new_i32();
+ TCGv_i32 temp2 = tcg_temp_new_i32();
if (n == 0) {
tcg_gen_mul_i32(temp, arg2, arg3);
} else { /* n is expected to be 1 */
@@ -1065,12 +1079,12 @@ gen_m16adds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
gen_adds(ret, arg1, temp);
}
-static void
-gen_m16add64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
- TCGv arg3, uint32_t n)
+static void gen_m16add64_q(TCGv_i32 rl, TCGv_i32 rh,
+ TCGv_i32 arg1_low, TCGv_i32 arg1_high,
+ TCGv_i32 arg2, TCGv_i32 arg3, uint32_t n)
{
- TCGv temp = tcg_temp_new();
- TCGv temp2 = tcg_temp_new();
+ TCGv_i32 temp = tcg_temp_new_i32();
+ TCGv_i32 temp2 = tcg_temp_new_i32();
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 t2 = tcg_temp_new_i64();
TCGv_i64 t3 = tcg_temp_new_i64();
@@ -1092,12 +1106,12 @@ gen_m16add64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
tcg_gen_extr_i64_i32(rl, rh, t3);
}
-static void
-gen_m16adds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
- TCGv arg3, uint32_t n)
+static void gen_m16adds64_q(TCGv_i32 rl, TCGv_i32 rh,
+ TCGv_i32 arg1_low, TCGv_i32 arg1_high,
+ TCGv_i32 arg2, TCGv_i32 arg3, uint32_t n)
{
- TCGv temp = tcg_temp_new();
- TCGv temp2 = tcg_temp_new();
+ TCGv_i32 temp = tcg_temp_new_i32();
+ TCGv_i32 temp2 = tcg_temp_new_i32();
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 t2 = tcg_temp_new_i64();
@@ -1118,15 +1132,15 @@ gen_m16adds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
tcg_gen_extr_i64_i32(rl, rh, t1);
}
-static void
-gen_madd64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
- TCGv arg3, uint32_t n)
+static void gen_madd64_q(TCGv_i32 rl, TCGv_i32 rh,
+ TCGv_i32 arg1_low, TCGv_i32 arg1_high,
+ TCGv_i32 arg2, TCGv_i32 arg3, uint32_t n)
{
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 t2 = tcg_temp_new_i64();
TCGv_i64 t3 = tcg_temp_new_i64();
TCGv_i64 t4 = tcg_temp_new_i64();
- TCGv temp, temp2;
+ TCGv_i32 temp, temp2;
tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
tcg_gen_ext_i32_i64(t2, arg2);
@@ -1146,8 +1160,8 @@ gen_madd64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
(0x80000000 * 0x80000000) << 1). If this is the
case, we negate the ovf. */
if (n == 1) {
- temp = tcg_temp_new();
- temp2 = tcg_temp_new();
+ temp = tcg_temp_new_i32();
+ temp2 = tcg_temp_new_i32();
tcg_gen_setcondi_i32(TCG_COND_EQ, temp, arg2, 0x80000000);
tcg_gen_setcond_i32(TCG_COND_EQ, temp2, arg2, arg3);
tcg_gen_and_i32(temp, temp, temp2);
@@ -1166,9 +1180,9 @@ gen_madd64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
}
-static void
-gen_madds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
- uint32_t up_shift)
+static void gen_madds32_q(TCGv_i32 ret,
+ TCGv_i32 arg1, TCGv_i32 arg2, TCGv_i32 arg3,
+ uint32_t n, uint32_t up_shift)
{
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 t2 = tcg_temp_new_i64();
@@ -1184,12 +1198,12 @@ gen_madds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
gen_helper_madd32_q_add_ssov(ret, tcg_env, t1, t2);
}
-static void
-gen_madds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
- TCGv arg3, uint32_t n)
+static void gen_madds64_q(TCGv_i32 rl, TCGv_i32 rh,
+ TCGv_i32 arg1_low, TCGv_i32 arg1_high,
+ TCGv_i32 arg2, TCGv_i32 arg3, uint32_t n)
{
TCGv_i64 r1 = tcg_temp_new_i64();
- TCGv t_n = tcg_constant_i32(n);
+ TCGv_i32 t_n = tcg_constant_i32(n);
tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high);
gen_helper_madd64_q_ssov(r1, tcg_env, r1, arg2, arg3, t_n);
@@ -1197,7 +1211,7 @@ gen_madds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
}
/* ret = r2 - (r1 * r3); */
-static void gen_msub32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3)
+static void gen_msub32_d(TCGv_i32 ret, TCGv_i32 r1, TCGv_i32 r2, TCGv_i32 r3)
{
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 t2 = tcg_temp_new_i64();
@@ -1229,20 +1243,20 @@ static void gen_msub32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3)
tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
}
-static void gen_msubi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con)
+static void gen_msubi32_d(TCGv_i32 ret, TCGv_i32 r1, TCGv_i32 r2, int32_t con)
{
- TCGv temp = tcg_constant_i32(con);
+ TCGv_i32 temp = tcg_constant_i32(con);
gen_msub32_d(ret, r1, r2, temp);
}
-static void
-gen_msub64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
- TCGv r3)
+static void gen_msub64_d(TCGv_i32 ret_low, TCGv_i32 ret_high,
+ TCGv_i32 r1, TCGv_i32 r2_low, TCGv_i32 r2_high,
+ TCGv_i32 r3)
{
- TCGv t1 = tcg_temp_new();
- TCGv t2 = tcg_temp_new();
- TCGv t3 = tcg_temp_new();
- TCGv t4 = tcg_temp_new();
+ TCGv_i32 t1 = tcg_temp_new_i32();
+ TCGv_i32 t2 = tcg_temp_new_i32();
+ TCGv_i32 t3 = tcg_temp_new_i32();
+ TCGv_i32 t4 = tcg_temp_new_i32();
tcg_gen_muls2_i32(t1, t2, r1, r3);
/* only the sub can overflow */
@@ -1263,17 +1277,16 @@ gen_msub64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
tcg_gen_mov_i32(ret_high, t4);
}
-static void
-gen_msubi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
- int32_t con)
+static void gen_msubi64_d(TCGv_i32 ret_low, TCGv_i32 ret_high,
+ TCGv_i32 r1, TCGv_i32 r2_low, TCGv_i32 r2_high,
+ int32_t con)
{
- TCGv temp = tcg_constant_i32(con);
+ TCGv_i32 temp = tcg_constant_i32(con);
gen_msub64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
}
-static void
-gen_msubu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
- TCGv r3)
+static void gen_msubu64_d(TCGv_i32 ret_low, TCGv_i32 ret_high, TCGv_i32 r1,
+ TCGv_i32 r2_low, TCGv_i32 r2_high, TCGv_i32 r3)
{
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 t2 = tcg_temp_new_i64();
@@ -1299,25 +1312,25 @@ gen_msubu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
}
-static void
-gen_msubui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
- int32_t con)
+static void gen_msubui64_d(TCGv_i32 ret_low, TCGv_i32 ret_high,
+ TCGv_i32 r1, TCGv_i32 r2_low, TCGv_i32 r2_high,
+ int32_t con)
{
- TCGv temp = tcg_constant_i32(con);
+ TCGv_i32 temp = tcg_constant_i32(con);
gen_msubu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
}
-static void gen_addi_d(TCGv ret, TCGv r1, int32_t r2)
+static void gen_addi_d(TCGv_i32 ret, TCGv_i32 r1, int32_t r2)
{
- TCGv temp = tcg_constant_i32(r2);
+ TCGv_i32 temp = tcg_constant_i32(r2);
gen_add_d(ret, r1, temp);
}
/* calculate the carry bit too */
-static void gen_add_CC(TCGv ret, TCGv r1, TCGv r2)
+static void gen_add_CC(TCGv_i32 ret, TCGv_i32 r1, TCGv_i32 r2)
{
- TCGv t0 = tcg_temp_new_i32();
- TCGv result = tcg_temp_new_i32();
+ TCGv_i32 t0 = tcg_temp_new_i32();
+ TCGv_i32 result = tcg_temp_new_i32();
tcg_gen_movi_i32(t0, 0);
/* Addition and set C/V/SV bits */
@@ -1337,16 +1350,16 @@ static void gen_add_CC(TCGv ret, TCGv r1, TCGv r2)
tcg_gen_mov_i32(ret, result);
}
-static void gen_addi_CC(TCGv ret, TCGv r1, int32_t con)
+static void gen_addi_CC(TCGv_i32 ret, TCGv_i32 r1, int32_t con)
{
- TCGv temp = tcg_constant_i32(con);
+ TCGv_i32 temp = tcg_constant_i32(con);
gen_add_CC(ret, r1, temp);
}
-static void gen_addc_CC(TCGv ret, TCGv r1, TCGv r2)
+static void gen_addc_CC(TCGv_i32 ret, TCGv_i32 r1, TCGv_i32 r2)
{
- TCGv t0 = tcg_temp_new_i32();
- TCGv result = tcg_temp_new_i32();
+ TCGv_i32 t0 = tcg_temp_new_i32();
+ TCGv_i32 result = tcg_temp_new_i32();
/* Addition, carry and set C/V/SV bits */
tcg_gen_addcio_i32(result, cpu_PSW_C, r1, r2, cpu_PSW_C);
@@ -1365,19 +1378,20 @@ static void gen_addc_CC(TCGv ret, TCGv r1, TCGv r2)
tcg_gen_mov_i32(ret, result);
}
-static void gen_addci_CC(TCGv ret, TCGv r1, int32_t con)
+static void gen_addci_CC(TCGv_i32 ret, TCGv_i32 r1, int32_t con)
{
- TCGv temp = tcg_constant_i32(con);
+ TCGv_i32 temp = tcg_constant_i32(con);
gen_addc_CC(ret, r1, temp);
}
-static void gen_cond_add(TCGCond cond, TCGv r1, TCGv r2, TCGv r3, TCGv r4)
+static void gen_cond_add(TCGCond cond,
+ TCGv_i32 r1, TCGv_i32 r2, TCGv_i32 r3, TCGv_i32 r4)
{
- TCGv temp = tcg_temp_new();
- TCGv temp2 = tcg_temp_new();
- TCGv result = tcg_temp_new();
- TCGv mask = tcg_temp_new();
- TCGv t0 = tcg_constant_i32(0);
+ TCGv_i32 temp = tcg_temp_new_i32();
+ TCGv_i32 temp2 = tcg_temp_new_i32();
+ TCGv_i32 result = tcg_temp_new_i32();
+ TCGv_i32 mask = tcg_temp_new_i32();
+ TCGv_i32 t0 = tcg_constant_i32(0);
/* create mask for sticky bits */
tcg_gen_setcond_i32(cond, mask, r4, t0);
@@ -1403,16 +1417,17 @@ static void gen_cond_add(TCGCond cond, TCGv r1, TCGv r2, TCGv r3, TCGv r4)
tcg_gen_movcond_i32(cond, r3, r4, t0, result, r1);
}
-static void gen_condi_add(TCGCond cond, TCGv r1, int32_t r2, TCGv r3, TCGv r4)
+static void gen_condi_add(TCGCond cond,
+ TCGv_i32 r1, int32_t r2, TCGv_i32 r3, TCGv_i32 r4)
{
- TCGv temp = tcg_constant_i32(r2);
+ TCGv_i32 temp = tcg_constant_i32(r2);
gen_cond_add(cond, r1, temp, r3, r4);
}
-static void gen_sub_d(TCGv ret, TCGv r1, TCGv r2)
+static void gen_sub_d(TCGv_i32 ret, TCGv_i32 r1, TCGv_i32 r2)
{
- TCGv temp = tcg_temp_new_i32();
- TCGv result = tcg_temp_new_i32();
+ TCGv_i32 temp = tcg_temp_new_i32();
+ TCGv_i32 result = tcg_temp_new_i32();
tcg_gen_sub_i32(result, r1, r2);
/* calc V bit */
@@ -1430,10 +1445,9 @@ static void gen_sub_d(TCGv ret, TCGv r1, TCGv r2)
tcg_gen_mov_i32(ret, result);
}
-static void
-gen_sub64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2)
+static void gen_sub64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2)
{
- TCGv temp = tcg_temp_new();
+ TCGv_i32 temp = tcg_temp_new_i32();
TCGv_i64 t0 = tcg_temp_new_i64();
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 result = tcg_temp_new_i64();
@@ -1456,10 +1470,10 @@ gen_sub64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2)
tcg_gen_mov_i64(ret, result);
}
-static void gen_sub_CC(TCGv ret, TCGv r1, TCGv r2)
+static void gen_sub_CC(TCGv_i32 ret, TCGv_i32 r1, TCGv_i32 r2)
{
- TCGv result = tcg_temp_new();
- TCGv temp = tcg_temp_new();
+ TCGv_i32 result = tcg_temp_new_i32();
+ TCGv_i32 temp = tcg_temp_new_i32();
tcg_gen_sub_i32(result, r1, r2);
/* calc C bit */
@@ -1479,20 +1493,21 @@ static void gen_sub_CC(TCGv ret, TCGv r1, TCGv r2)
tcg_gen_mov_i32(ret, result);
}
-static void gen_subc_CC(TCGv ret, TCGv r1, TCGv r2)
+static void gen_subc_CC(TCGv_i32 ret, TCGv_i32 r1, TCGv_i32 r2)
{
- TCGv temp = tcg_temp_new();
+ TCGv_i32 temp = tcg_temp_new_i32();
tcg_gen_not_i32(temp, r2);
gen_addc_CC(ret, r1, temp);
}
-static void gen_cond_sub(TCGCond cond, TCGv r1, TCGv r2, TCGv r3, TCGv r4)
+static void gen_cond_sub(TCGCond cond,
+ TCGv_i32 r1, TCGv_i32 r2, TCGv_i32 r3, TCGv_i32 r4)
{
- TCGv temp = tcg_temp_new();
- TCGv temp2 = tcg_temp_new();
- TCGv result = tcg_temp_new();
- TCGv mask = tcg_temp_new();
- TCGv t0 = tcg_constant_i32(0);
+ TCGv_i32 temp = tcg_temp_new_i32();
+ TCGv_i32 temp2 = tcg_temp_new_i32();
+ TCGv_i32 result = tcg_temp_new_i32();
+ TCGv_i32 mask = tcg_temp_new_i32();
+ TCGv_i32 t0 = tcg_constant_i32(0);
/* create mask for sticky bits */
tcg_gen_setcond_i32(cond, mask, r4, t0);
@@ -1518,13 +1533,14 @@ static void gen_cond_sub(TCGCond cond, TCGv r1, TCGv r2, TCGv r3, TCGv r4)
tcg_gen_movcond_i32(cond, r3, r4, t0, result, r1);
}
-static void
-gen_msub_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
- TCGv r3, uint32_t n, uint32_t mode)
+static void gen_msub_h(TCGv_i32 ret_low, TCGv_i32 ret_high,
+ TCGv_i32 r1_low, TCGv_i32 r1_high,
+ TCGv_i32 r2, TCGv_i32 r3,
+ uint32_t n, uint32_t mode)
{
- TCGv t_n = tcg_constant_i32(n);
- TCGv temp = tcg_temp_new();
- TCGv temp2 = tcg_temp_new();
+ TCGv_i32 t_n = tcg_constant_i32(n);
+ TCGv_i32 temp = tcg_temp_new_i32();
+ TCGv_i32 temp2 = tcg_temp_new_i32();
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
@@ -1545,14 +1561,15 @@ gen_msub_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
tcg_gen_sub_tl, tcg_gen_sub_tl);
}
-static void
-gen_msubs_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
- TCGv r3, uint32_t n, uint32_t mode)
+static void gen_msubs_h(TCGv_i32 ret_low, TCGv_i32 ret_high,
+ TCGv_i32 r1_low, TCGv_i32 r1_high,
+ TCGv_i32 r2, TCGv_i32 r3,
+ uint32_t n, uint32_t mode)
{
- TCGv t_n = tcg_constant_i32(n);
- TCGv temp = tcg_temp_new();
- TCGv temp2 = tcg_temp_new();
- TCGv temp3 = tcg_temp_new();
+ TCGv_i32 t_n = tcg_constant_i32(n);
+ TCGv_i32 temp = tcg_temp_new_i32();
+ TCGv_i32 temp2 = tcg_temp_new_i32();
+ TCGv_i32 temp3 = tcg_temp_new_i32();
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
@@ -1580,11 +1597,12 @@ gen_msubs_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
tcg_gen_or_i32(cpu_PSW_AV, cpu_PSW_AV, temp3);
}
-static void
-gen_msubm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
- TCGv r3, uint32_t n, uint32_t mode)
+static void gen_msubm_h(TCGv_i32 ret_low, TCGv_i32 ret_high,
+ TCGv_i32 r1_low, TCGv_i32 r1_high,
+ TCGv_i32 r2, TCGv_i32 r3,
+ uint32_t n, uint32_t mode)
{
- TCGv t_n = tcg_constant_i32(n);
+ TCGv_i32 t_n = tcg_constant_i32(n);
TCGv_i64 temp64 = tcg_temp_new_i64();
TCGv_i64 temp64_2 = tcg_temp_new_i64();
TCGv_i64 temp64_3 = tcg_temp_new_i64();
@@ -1608,11 +1626,12 @@ gen_msubm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3);
}
-static void
-gen_msubms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
- TCGv r3, uint32_t n, uint32_t mode)
+static void gen_msubms_h(TCGv_i32 ret_low, TCGv_i32 ret_high,
+ TCGv_i32 r1_low, TCGv_i32 r1_high,
+ TCGv_i32 r2, TCGv_i32 r3,
+ uint32_t n, uint32_t mode)
{
- TCGv t_n = tcg_constant_i32(n);
+ TCGv_i32 t_n = tcg_constant_i32(n);
TCGv_i64 temp64 = tcg_temp_new_i64();
TCGv_i64 temp64_2 = tcg_temp_new_i64();
switch (mode) {
@@ -1634,11 +1653,12 @@ gen_msubms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
}
-static void
-gen_msubr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n,
- uint32_t mode)
+static void gen_msubr64_h(TCGv_i32 ret,
+ TCGv_i32 r1_low, TCGv_i32 r1_high,
+ TCGv_i32 r2, TCGv_i32 r3,
+ uint32_t n, uint32_t mode)
{
- TCGv t_n = tcg_constant_i32(n);
+ TCGv_i32 t_n = tcg_constant_i32(n);
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
@@ -1657,22 +1677,24 @@ gen_msubr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n,
gen_helper_subr_h(ret, tcg_env, temp64, r1_low, r1_high);
}
-static void
-gen_msubr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
+static void gen_msubr32_h(TCGv_i32 ret,
+ TCGv_i32 r1, TCGv_i32 r2, TCGv_i32 r3,
+ uint32_t n, uint32_t mode)
{
- TCGv temp = tcg_temp_new();
- TCGv temp2 = tcg_temp_new();
+ TCGv_i32 temp = tcg_temp_new_i32();
+ TCGv_i32 temp2 = tcg_temp_new_i32();
tcg_gen_andi_i32(temp2, r1, 0xffff0000);
tcg_gen_shli_i32(temp, r1, 16);
gen_msubr64_h(ret, temp, temp2, r2, r3, n, mode);
}
-static void
-gen_msubr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3,
- uint32_t n, uint32_t mode)
+static void gen_msubr64s_h(TCGv_i32 ret,
+ TCGv_i32 r1_low, TCGv_i32 r1_high,
+ TCGv_i32 r2, TCGv_i32 r3,
+ uint32_t n, uint32_t mode)
{
- TCGv t_n = tcg_constant_i32(n);
+ TCGv_i32 t_n = tcg_constant_i32(n);
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
@@ -1691,36 +1713,37 @@ gen_msubr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3,
gen_helper_subr_h_ssov(ret, tcg_env, temp64, r1_low, r1_high);
}
-static void
-gen_msubr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
+static void gen_msubr32s_h(TCGv_i32 ret,
+ TCGv_i32 r1, TCGv_i32 r2, TCGv_i32 r3,
+ uint32_t n, uint32_t mode)
{
- TCGv temp = tcg_temp_new();
- TCGv temp2 = tcg_temp_new();
+ TCGv_i32 temp = tcg_temp_new_i32();
+ TCGv_i32 temp2 = tcg_temp_new_i32();
tcg_gen_andi_i32(temp2, r1, 0xffff0000);
tcg_gen_shli_i32(temp, r1, 16);
gen_msubr64s_h(ret, temp, temp2, r2, r3, n, mode);
}
-static void
-gen_msubr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
+static void gen_msubr_q(TCGv_i32 ret,
+ TCGv_i32 r1, TCGv_i32 r2, TCGv_i32 r3, uint32_t n)
{
- TCGv temp = tcg_constant_i32(n);
+ TCGv_i32 temp = tcg_constant_i32(n);
gen_helper_msubr_q(ret, tcg_env, r1, r2, r3, temp);
}
-static void
-gen_msubrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
+static void gen_msubrs_q(TCGv_i32 ret,
+ TCGv_i32 r1, TCGv_i32 r2, TCGv_i32 r3, uint32_t n)
{
- TCGv temp = tcg_constant_i32(n);
+ TCGv_i32 temp = tcg_constant_i32(n);
gen_helper_msubr_q_ssov(ret, tcg_env, r1, r2, r3, temp);
}
-static void
-gen_msub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
- uint32_t up_shift)
+static void gen_msub32_q(TCGv_i32 ret,
+ TCGv_i32 arg1, TCGv_i32 arg2, TCGv_i32 arg3,
+ uint32_t n, uint32_t up_shift)
{
- TCGv temp3 = tcg_temp_new();
+ TCGv_i32 temp3 = tcg_temp_new_i32();
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 t2 = tcg_temp_new_i64();
TCGv_i64 t3 = tcg_temp_new_i64();
@@ -1757,11 +1780,12 @@ gen_msub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
tcg_gen_mov_i32(ret, temp3);
}
-static void
-gen_m16sub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
+static void gen_m16sub32_q(TCGv_i32 ret,
+ TCGv_i32 arg1, TCGv_i32 arg2, TCGv_i32 arg3,
+ uint32_t n)
{
- TCGv temp = tcg_temp_new();
- TCGv temp2 = tcg_temp_new();
+ TCGv_i32 temp = tcg_temp_new_i32();
+ TCGv_i32 temp2 = tcg_temp_new_i32();
if (n == 0) {
tcg_gen_mul_i32(temp, arg2, arg3);
} else { /* n is expected to be 1 */
@@ -1774,11 +1798,12 @@ gen_m16sub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
gen_sub_d(ret, arg1, temp);
}
-static void
-gen_m16subs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
+static void gen_m16subs32_q(TCGv_i32 ret,
+ TCGv_i32 arg1, TCGv_i32 arg2, TCGv_i32 arg3,
+ uint32_t n)
{
- TCGv temp = tcg_temp_new();
- TCGv temp2 = tcg_temp_new();
+ TCGv_i32 temp = tcg_temp_new_i32();
+ TCGv_i32 temp2 = tcg_temp_new_i32();
if (n == 0) {
tcg_gen_mul_i32(temp, arg2, arg3);
} else { /* n is expected to be 1 */
@@ -1791,12 +1816,12 @@ gen_m16subs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
gen_subs(ret, arg1, temp);
}
-static void
-gen_m16sub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
- TCGv arg3, uint32_t n)
+static void gen_m16sub64_q(TCGv_i32 rl, TCGv_i32 rh,
+ TCGv_i32 arg1_low, TCGv_i32 arg1_high,
+ TCGv_i32 arg2, TCGv_i32 arg3, uint32_t n)
{
- TCGv temp = tcg_temp_new();
- TCGv temp2 = tcg_temp_new();
+ TCGv_i32 temp = tcg_temp_new_i32();
+ TCGv_i32 temp2 = tcg_temp_new_i32();
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 t2 = tcg_temp_new_i64();
TCGv_i64 t3 = tcg_temp_new_i64();
@@ -1818,12 +1843,12 @@ gen_m16sub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
tcg_gen_extr_i64_i32(rl, rh, t3);
}
-static void
-gen_m16subs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
- TCGv arg3, uint32_t n)
+static void gen_m16subs64_q(TCGv_i32 rl, TCGv_i32 rh,
+ TCGv_i32 arg1_low, TCGv_i32 arg1_high,
+ TCGv_i32 arg2, TCGv_i32 arg3, uint32_t n)
{
- TCGv temp = tcg_temp_new();
- TCGv temp2 = tcg_temp_new();
+ TCGv_i32 temp = tcg_temp_new_i32();
+ TCGv_i32 temp2 = tcg_temp_new_i32();
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 t2 = tcg_temp_new_i64();
@@ -1844,15 +1869,15 @@ gen_m16subs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
tcg_gen_extr_i64_i32(rl, rh, t1);
}
-static void
-gen_msub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
- TCGv arg3, uint32_t n)
+static void gen_msub64_q(TCGv_i32 rl, TCGv_i32 rh,
+ TCGv_i32 arg1_low, TCGv_i32 arg1_high,
+ TCGv_i32 arg2, TCGv_i32 arg3, uint32_t n)
{
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 t2 = tcg_temp_new_i64();
TCGv_i64 t3 = tcg_temp_new_i64();
TCGv_i64 t4 = tcg_temp_new_i64();
- TCGv temp, temp2;
+ TCGv_i32 temp, temp2;
tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
tcg_gen_ext_i32_i64(t2, arg2);
@@ -1872,8 +1897,8 @@ gen_msub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
(0x80000000 * 0x80000000) << 1). If this is the
case, we negate the ovf. */
if (n == 1) {
- temp = tcg_temp_new();
- temp2 = tcg_temp_new();
+ temp = tcg_temp_new_i32();
+ temp2 = tcg_temp_new_i32();
tcg_gen_setcondi_i32(TCG_COND_EQ, temp, arg2, 0x80000000);
tcg_gen_setcond_i32(TCG_COND_EQ, temp2, arg2, arg3);
tcg_gen_and_i32(temp, temp, temp2);
@@ -1892,9 +1917,9 @@ gen_msub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
}
-static void
-gen_msubs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
- uint32_t up_shift)
+static void gen_msubs32_q(TCGv_i32 ret,
+ TCGv_i32 arg1, TCGv_i32 arg2, TCGv_i32 arg3,
+ uint32_t n, uint32_t up_shift)
{
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 t2 = tcg_temp_new_i64();
@@ -1915,25 +1940,26 @@ gen_msubs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
gen_helper_msub32_q_sub_ssov(ret, tcg_env, t1, t3);
}
-static void
-gen_msubs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
- TCGv arg3, uint32_t n)
+static void gen_msubs64_q(TCGv_i32 rl, TCGv_i32 rh,
+ TCGv_i32 arg1_low, TCGv_i32 arg1_high,
+ TCGv_i32 arg2, TCGv_i32 arg3, uint32_t n)
{
TCGv_i64 r1 = tcg_temp_new_i64();
- TCGv t_n = tcg_constant_i32(n);
+ TCGv_i32 t_n = tcg_constant_i32(n);
tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high);
gen_helper_msub64_q_ssov(r1, tcg_env, r1, arg2, arg3, t_n);
tcg_gen_extr_i64_i32(rl, rh, r1);
}
-static void
-gen_msubad_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
- TCGv r3, uint32_t n, uint32_t mode)
+static void gen_msubad_h(TCGv_i32 ret_low, TCGv_i32 ret_high,
+ TCGv_i32 r1_low, TCGv_i32 r1_high,
+ TCGv_i32 r2, TCGv_i32 r3,
+ uint32_t n, uint32_t mode)
{
- TCGv t_n = tcg_constant_i32(n);
- TCGv temp = tcg_temp_new();
- TCGv temp2 = tcg_temp_new();
+ TCGv_i32 t_n = tcg_constant_i32(n);
+ TCGv_i32 temp = tcg_temp_new_i32();
+ TCGv_i32 temp2 = tcg_temp_new_i32();
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
@@ -1954,11 +1980,12 @@ gen_msubad_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
tcg_gen_add_tl, tcg_gen_sub_tl);
}
-static void
-gen_msubadm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
- TCGv r3, uint32_t n, uint32_t mode)
+static void gen_msubadm_h(TCGv_i32 ret_low, TCGv_i32 ret_high,
+ TCGv_i32 r1_low, TCGv_i32 r1_high,
+ TCGv_i32 r2, TCGv_i32 r3,
+ uint32_t n, uint32_t mode)
{
- TCGv t_n = tcg_constant_i32(n);
+ TCGv_i32 t_n = tcg_constant_i32(n);
TCGv_i64 temp64 = tcg_temp_new_i64();
TCGv_i64 temp64_2 = tcg_temp_new_i64();
TCGv_i64 temp64_3 = tcg_temp_new_i64();
@@ -1987,12 +2014,13 @@ gen_msubadm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2);
}
-static void
-gen_msubadr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
+static void gen_msubadr32_h(TCGv_i32 ret,
+ TCGv_i32 r1, TCGv_i32 r2, TCGv_i32 r3,
+ uint32_t n, uint32_t mode)
{
- TCGv t_n = tcg_constant_i32(n);
- TCGv temp = tcg_temp_new();
- TCGv temp2 = tcg_temp_new();
+ TCGv_i32 t_n = tcg_constant_i32(n);
+ TCGv_i32 temp = tcg_temp_new_i32();
+ TCGv_i32 temp2 = tcg_temp_new_i32();
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
@@ -2013,14 +2041,15 @@ gen_msubadr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
gen_helper_subadr_h(ret, tcg_env, temp64, temp, temp2);
}
-static void
-gen_msubads_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
- TCGv r3, uint32_t n, uint32_t mode)
+static void gen_msubads_h(TCGv_i32 ret_low, TCGv_i32 ret_high,
+ TCGv_i32 r1_low, TCGv_i32 r1_high,
+ TCGv_i32 r2, TCGv_i32 r3,
+ uint32_t n, uint32_t mode)
{
- TCGv t_n = tcg_constant_i32(n);
- TCGv temp = tcg_temp_new();
- TCGv temp2 = tcg_temp_new();
- TCGv temp3 = tcg_temp_new();
+ TCGv_i32 t_n = tcg_constant_i32(n);
+ TCGv_i32 temp = tcg_temp_new_i32();
+ TCGv_i32 temp2 = tcg_temp_new_i32();
+ TCGv_i32 temp3 = tcg_temp_new_i32();
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
@@ -2048,11 +2077,12 @@ gen_msubads_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
tcg_gen_or_i32(cpu_PSW_AV, cpu_PSW_AV, temp3);
}
-static void
-gen_msubadms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
- TCGv r3, uint32_t n, uint32_t mode)
+static void gen_msubadms_h(TCGv_i32 ret_low, TCGv_i32 ret_high,
+ TCGv_i32 r1_low, TCGv_i32 r1_high,
+ TCGv_i32 r2, TCGv_i32 r3,
+ uint32_t n, uint32_t mode)
{
- TCGv t_n = tcg_constant_i32(n);
+ TCGv_i32 t_n = tcg_constant_i32(n);
TCGv_i64 temp64 = tcg_temp_new_i64();
TCGv_i64 temp64_2 = tcg_temp_new_i64();
@@ -2080,12 +2110,13 @@ gen_msubadms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
}
-static void
-gen_msubadr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
+static void gen_msubadr32s_h(TCGv_i32 ret,
+ TCGv_i32 r1, TCGv_i32 r2, TCGv_i32 r3,
+ uint32_t n, uint32_t mode)
{
- TCGv t_n = tcg_constant_i32(n);
- TCGv temp = tcg_temp_new();
- TCGv temp2 = tcg_temp_new();
+ TCGv_i32 t_n = tcg_constant_i32(n);
+ TCGv_i32 temp = tcg_temp_new_i32();
+ TCGv_i32 temp2 = tcg_temp_new_i32();
TCGv_i64 temp64 = tcg_temp_new_i64();
switch (mode) {
case MODE_LL:
@@ -2106,7 +2137,7 @@ gen_msubadr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
gen_helper_subadr_h_ssov(ret, tcg_env, temp64, temp, temp2);
}
-static void gen_abs(TCGv ret, TCGv r1)
+static void gen_abs(TCGv_i32 ret, TCGv_i32 r1)
{
tcg_gen_abs_i32(ret, r1);
/* overflow can only happen, if r1 = 0x80000000 */
@@ -2121,10 +2152,10 @@ static void gen_abs(TCGv ret, TCGv r1)
tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
}
-static void gen_absdif(TCGv ret, TCGv r1, TCGv r2)
+static void gen_absdif(TCGv_i32 ret, TCGv_i32 r1, TCGv_i32 r2)
{
- TCGv temp = tcg_temp_new_i32();
- TCGv result = tcg_temp_new_i32();
+ TCGv_i32 temp = tcg_temp_new_i32();
+ TCGv_i32 result = tcg_temp_new_i32();
tcg_gen_sub_i32(result, r1, r2);
tcg_gen_sub_i32(temp, r2, r1);
@@ -2147,22 +2178,22 @@ static void gen_absdif(TCGv ret, TCGv r1, TCGv r2)
tcg_gen_mov_i32(ret, result);
}
-static void gen_absdifi(TCGv ret, TCGv r1, int32_t con)
+static void gen_absdifi(TCGv_i32 ret, TCGv_i32 r1, int32_t con)
{
- TCGv temp = tcg_constant_i32(con);
+ TCGv_i32 temp = tcg_constant_i32(con);
gen_absdif(ret, r1, temp);
}
-static void gen_absdifsi(TCGv ret, TCGv r1, int32_t con)
+static void gen_absdifsi(TCGv_i32 ret, TCGv_i32 r1, int32_t con)
{
- TCGv temp = tcg_constant_i32(con);
+ TCGv_i32 temp = tcg_constant_i32(con);
gen_helper_absdif_ssov(ret, tcg_env, r1, temp);
}
-static void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2)
+static void gen_mul_i32s(TCGv_i32 ret, TCGv_i32 r1, TCGv_i32 r2)
{
- TCGv high = tcg_temp_new();
- TCGv low = tcg_temp_new();
+ TCGv_i32 high = tcg_temp_new_i32();
+ TCGv_i32 low = tcg_temp_new_i32();
tcg_gen_muls2_i32(low, high, r1, r2);
tcg_gen_mov_i32(ret, low);
@@ -2179,13 +2210,14 @@ static void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2)
tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
}
-static void gen_muli_i32s(TCGv ret, TCGv r1, int32_t con)
+static void gen_muli_i32s(TCGv_i32 ret, TCGv_i32 r1, int32_t con)
{
- TCGv temp = tcg_constant_i32(con);
+ TCGv_i32 temp = tcg_constant_i32(con);
gen_mul_i32s(ret, r1, temp);
}
-static void gen_mul_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2)
+static void gen_mul_i64s(TCGv_i32 ret_low, TCGv_i32 ret_high,
+ TCGv_i32 r1, TCGv_i32 r2)
{
tcg_gen_muls2_i32(ret_low, ret_high, r1, r2);
/* clear V bit */
@@ -2199,14 +2231,15 @@ static void gen_mul_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2)
tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
}
-static void gen_muli_i64s(TCGv ret_low, TCGv ret_high, TCGv r1,
- int32_t con)
+static void gen_muli_i64s(TCGv_i32 ret_low, TCGv_i32 ret_high,
+ TCGv_i32 r1, int32_t con)
{
- TCGv temp = tcg_constant_i32(con);
+ TCGv_i32 temp = tcg_constant_i32(con);
gen_mul_i64s(ret_low, ret_high, r1, temp);
}
-static void gen_mul_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2)
+static void gen_mul_i64u(TCGv_i32 ret_low, TCGv_i32 ret_high,
+ TCGv_i32 r1, TCGv_i32 r2)
{
tcg_gen_mulu2_i32(ret_low, ret_high, r1, r2);
/* clear V bit */
@@ -2220,40 +2253,40 @@ static void gen_mul_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2)
tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
}
-static void gen_muli_i64u(TCGv ret_low, TCGv ret_high, TCGv r1,
- int32_t con)
+static void gen_muli_i64u(TCGv_i32 ret_low, TCGv_i32 ret_high,
+ TCGv_i32 r1, int32_t con)
{
- TCGv temp = tcg_constant_i32(con);
+ TCGv_i32 temp = tcg_constant_i32(con);
gen_mul_i64u(ret_low, ret_high, r1, temp);
}
-static void gen_mulsi_i32(TCGv ret, TCGv r1, int32_t con)
+static void gen_mulsi_i32(TCGv_i32 ret, TCGv_i32 r1, int32_t con)
{
- TCGv temp = tcg_constant_i32(con);
+ TCGv_i32 temp = tcg_constant_i32(con);
gen_helper_mul_ssov(ret, tcg_env, r1, temp);
}
-static void gen_mulsui_i32(TCGv ret, TCGv r1, int32_t con)
+static void gen_mulsui_i32(TCGv_i32 ret, TCGv_i32 r1, int32_t con)
{
- TCGv temp = tcg_constant_i32(con);
+ TCGv_i32 temp = tcg_constant_i32(con);
gen_helper_mul_suov(ret, tcg_env, r1, temp);
}
/* gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); */
-static void gen_maddsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
+static void gen_maddsi_32(TCGv_i32 ret, TCGv_i32 r1, TCGv_i32 r2, int32_t con)
{
- TCGv temp = tcg_constant_i32(con);
+ TCGv_i32 temp = tcg_constant_i32(con);
gen_helper_madd32_ssov(ret, tcg_env, r1, r2, temp);
}
-static void gen_maddsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
+static void gen_maddsui_32(TCGv_i32 ret, TCGv_i32 r1, TCGv_i32 r2, int32_t con)
{
- TCGv temp = tcg_constant_i32(con);
+ TCGv_i32 temp = tcg_constant_i32(con);
gen_helper_madd32_suov(ret, tcg_env, r1, r2, temp);
}
-static void
-gen_mul_q(TCGv rl, TCGv rh, TCGv arg1, TCGv arg2, uint32_t n, uint32_t up_shift)
+static void gen_mul_q(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2,
+ uint32_t n, uint32_t up_shift)
{
TCGv_i64 temp_64 = tcg_temp_new_i64();
TCGv_i64 temp2_64 = tcg_temp_new_i64();
@@ -2309,10 +2342,9 @@ gen_mul_q(TCGv rl, TCGv rh, TCGv arg1, TCGv arg2, uint32_t n, uint32_t up_shift)
tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
}
-static void
-gen_mul_q_16(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n)
+static void gen_mul_q_16(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2, uint32_t n)
{
- TCGv temp = tcg_temp_new();
+ TCGv_i32 temp = tcg_temp_new_i32();
if (n == 0) {
tcg_gen_mul_i32(ret, arg1, arg2);
} else { /* n is expected to be 1 */
@@ -2331,9 +2363,9 @@ gen_mul_q_16(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n)
tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
}
-static void gen_mulr_q(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n)
+static void gen_mulr_q(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2, uint32_t n)
{
- TCGv temp = tcg_temp_new();
+ TCGv_i32 temp = tcg_temp_new_i32();
if (n == 0) {
tcg_gen_mul_i32(ret, arg1, arg2);
tcg_gen_addi_i32(ret, ret, 0x8000);
@@ -2357,9 +2389,9 @@ static void gen_mulr_q(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n)
tcg_gen_andi_i32(ret, ret, 0xffff0000);
}
-static void
-gen_madds_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
- TCGv r3)
+static void gen_madds_64(TCGv_i32 ret_low, TCGv_i32 ret_high,
+ TCGv_i32 r1, TCGv_i32 r2_low, TCGv_i32 r2_high,
+ TCGv_i32 r3)
{
TCGv_i64 temp64 = tcg_temp_new_i64();
tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
@@ -2367,17 +2399,17 @@ gen_madds_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
}
-static void
-gen_maddsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
- int32_t con)
+static void gen_maddsi_64(TCGv_i32 ret_low, TCGv_i32 ret_high,
+ TCGv_i32 r1, TCGv_i32 r2_low, TCGv_i32 r2_high,
+ int32_t con)
{
- TCGv temp = tcg_constant_i32(con);
+ TCGv_i32 temp = tcg_constant_i32(con);
gen_madds_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
}
-static void
-gen_maddsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
- TCGv r3)
+static void gen_maddsu_64(TCGv_i32 ret_low, TCGv_i32 ret_high,
+ TCGv_i32 r1, TCGv_i32 r2_low, TCGv_i32 r2_high,
+ TCGv_i32 r3)
{
TCGv_i64 temp64 = tcg_temp_new_i64();
tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
@@ -2385,29 +2417,29 @@ gen_maddsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
}
-static void
-gen_maddsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
- int32_t con)
+static void gen_maddsui_64(TCGv_i32 ret_low, TCGv_i32 ret_high,
+ TCGv_i32 r1, TCGv_i32 r2_low,
+ TCGv_i32 r2_high, int32_t con)
{
- TCGv temp = tcg_constant_i32(con);
+ TCGv_i32 temp = tcg_constant_i32(con);
gen_maddsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
}
-static void gen_msubsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
+static void gen_msubsi_32(TCGv_i32 ret, TCGv_i32 r1, TCGv_i32 r2, int32_t con)
{
- TCGv temp = tcg_constant_i32(con);
+ TCGv_i32 temp = tcg_constant_i32(con);
gen_helper_msub32_ssov(ret, tcg_env, r1, r2, temp);
}
-static void gen_msubsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
+static void gen_msubsui_32(TCGv_i32 ret, TCGv_i32 r1, TCGv_i32 r2, int32_t con)
{
- TCGv temp = tcg_constant_i32(con);
+ TCGv_i32 temp = tcg_constant_i32(con);
gen_helper_msub32_suov(ret, tcg_env, r1, r2, temp);
}
-static void
-gen_msubs_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
- TCGv r3)
+static void gen_msubs_64(TCGv_i32 ret_low, TCGv_i32 ret_high,
+ TCGv_i32 r1, TCGv_i32 r2_low, TCGv_i32 r2_high,
+ TCGv_i32 r3)
{
TCGv_i64 temp64 = tcg_temp_new_i64();
tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
@@ -2415,17 +2447,17 @@ gen_msubs_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
}
-static void
-gen_msubsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
- int32_t con)
+static void gen_msubsi_64(TCGv_i32 ret_low, TCGv_i32 ret_high,
+ TCGv_i32 r1, TCGv_i32 r2_low, TCGv_i32 r2_high,
+ int32_t con)
{
- TCGv temp = tcg_constant_i32(con);
+ TCGv_i32 temp = tcg_constant_i32(con);
gen_msubs_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
}
-static void
-gen_msubsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
- TCGv r3)
+static void gen_msubsu_64(TCGv_i32 ret_low, TCGv_i32 ret_high,
+ TCGv_i32 r1, TCGv_i32 r2_low, TCGv_i32 r2_high,
+ TCGv_i32 r3)
{
TCGv_i64 temp64 = tcg_temp_new_i64();
tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
@@ -2433,26 +2465,26 @@ gen_msubsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
}
-static void
-gen_msubsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
- int32_t con)
+static void gen_msubsui_64(TCGv_i32 ret_low, TCGv_i32 ret_high,
+ TCGv_i32 r1, TCGv_i32 r2_low, TCGv_i32 r2_high,
+ int32_t con)
{
- TCGv temp = tcg_constant_i32(con);
+ TCGv_i32 temp = tcg_constant_i32(con);
gen_msubsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
}
-static void gen_saturate(TCGv ret, TCGv arg, int32_t up, int32_t low)
+static void gen_saturate(TCGv_i32 ret, TCGv_i32 arg, int32_t up, int32_t low)
{
tcg_gen_smax_i32(ret, arg, tcg_constant_i32(low));
tcg_gen_smin_i32(ret, ret, tcg_constant_i32(up));
}
-static void gen_saturate_u(TCGv ret, TCGv arg, int32_t up)
+static void gen_saturate_u(TCGv_i32 ret, TCGv_i32 arg, int32_t up)
{
tcg_gen_umin_i32(ret, arg, tcg_constant_i32(up));
}
-static void gen_shi(TCGv ret, TCGv r1, int32_t shift_count)
+static void gen_shi(TCGv_i32 ret, TCGv_i32 r1, int32_t shift_count)
{
if (shift_count == -32) {
tcg_gen_movi_i32(ret, 0);
@@ -2463,15 +2495,15 @@ static void gen_shi(TCGv ret, TCGv r1, int32_t shift_count)
}
}
-static void gen_sh_hi(TCGv ret, TCGv r1, int32_t shiftcount)
+static void gen_sh_hi(TCGv_i32 ret, TCGv_i32 r1, int32_t shiftcount)
{
- TCGv temp_low, temp_high;
+ TCGv_i32 temp_low, temp_high;
if (shiftcount == -16) {
tcg_gen_movi_i32(ret, 0);
} else {
- temp_high = tcg_temp_new();
- temp_low = tcg_temp_new();
+ temp_high = tcg_temp_new_i32();
+ temp_low = tcg_temp_new_i32();
tcg_gen_andi_i32(temp_low, r1, 0xffff);
tcg_gen_andi_i32(temp_high, r1, 0xffff0000);
@@ -2481,11 +2513,11 @@ static void gen_sh_hi(TCGv ret, TCGv r1, int32_t shiftcount)
}
}
-static void gen_shaci(TCGv ret, TCGv r1, int32_t shift_count)
+static void gen_shaci(TCGv_i32 ret, TCGv_i32 r1, int32_t shift_count)
{
uint32_t msk, msk_start;
- TCGv temp = tcg_temp_new();
- TCGv temp2 = tcg_temp_new();
+ TCGv_i32 temp = tcg_temp_new_i32();
+ TCGv_i32 temp2 = tcg_temp_new_i32();
if (shift_count == 0) {
/* Clear PSW.C and PSW.V */
@@ -2500,8 +2532,8 @@ static void gen_shaci(TCGv ret, TCGv r1, int32_t shift_count)
/* clear PSW.V */
tcg_gen_movi_i32(cpu_PSW_V, 0);
} else if (shift_count > 0) {
- TCGv t_max = tcg_constant_i32(0x7FFFFFFF >> shift_count);
- TCGv t_min = tcg_constant_i32(((int32_t) -0x80000000) >> shift_count);
+ TCGv_i32 t_max = tcg_constant_i32(0x7FFFFFFF >> shift_count);
+ TCGv_i32 t_min = tcg_constant_i32(((int32_t) -0x80000000) >> shift_count);
/* calc carry */
msk_start = 32 - shift_count;
@@ -2532,34 +2564,34 @@ static void gen_shaci(TCGv ret, TCGv r1, int32_t shift_count)
tcg_gen_or_i32(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
}
-static void gen_shas(TCGv ret, TCGv r1, TCGv r2)
+static void gen_shas(TCGv_i32 ret, TCGv_i32 r1, TCGv_i32 r2)
{
gen_helper_sha_ssov(ret, tcg_env, r1, r2);
}
-static void gen_shasi(TCGv ret, TCGv r1, int32_t con)
+static void gen_shasi(TCGv_i32 ret, TCGv_i32 r1, int32_t con)
{
- TCGv temp = tcg_constant_i32(con);
+ TCGv_i32 temp = tcg_constant_i32(con);
gen_shas(ret, r1, temp);
}
-static void gen_sha_hi(TCGv ret, TCGv r1, int32_t shift_count)
+static void gen_sha_hi(TCGv_i32 ret, TCGv_i32 r1, int32_t shift_count)
{
- TCGv low, high;
+ TCGv_i32 low, high;
if (shift_count == 0) {
tcg_gen_mov_i32(ret, r1);
} else if (shift_count > 0) {
- low = tcg_temp_new();
- high = tcg_temp_new();
+ low = tcg_temp_new_i32();
+ high = tcg_temp_new_i32();
tcg_gen_andi_i32(high, r1, 0xffff0000);
tcg_gen_shli_i32(low, r1, shift_count);
tcg_gen_shli_i32(ret, high, shift_count);
tcg_gen_deposit_i32(ret, ret, low, 0, 16);
} else {
- low = tcg_temp_new();
- high = tcg_temp_new();
+ low = tcg_temp_new_i32();
+ high = tcg_temp_new_i32();
tcg_gen_ext16s_i32(low, r1);
tcg_gen_sari_i32(low, low, -shift_count);
@@ -2569,58 +2601,58 @@ static void gen_sha_hi(TCGv ret, TCGv r1, int32_t shift_count)
}
/* ret = {ret[30:0], (r1 cond r2)}; */
-static void gen_sh_cond(int cond, TCGv ret, TCGv r1, TCGv r2)
+static void gen_sh_cond(int cond, TCGv_i32 ret, TCGv_i32 r1, TCGv_i32 r2)
{
- TCGv temp = tcg_temp_new();
- TCGv temp2 = tcg_temp_new();
+ TCGv_i32 temp = tcg_temp_new_i32();
+ TCGv_i32 temp2 = tcg_temp_new_i32();
tcg_gen_shli_i32(temp, ret, 1);
tcg_gen_setcond_i32(cond, temp2, r1, r2);
tcg_gen_or_i32(ret, temp, temp2);
}
-static void gen_sh_condi(int cond, TCGv ret, TCGv r1, int32_t con)
+static void gen_sh_condi(int cond, TCGv_i32 ret, TCGv_i32 r1, int32_t con)
{
- TCGv temp = tcg_constant_i32(con);
+ TCGv_i32 temp = tcg_constant_i32(con);
gen_sh_cond(cond, ret, r1, temp);
}
-static void gen_adds(TCGv ret, TCGv r1, TCGv r2)
+static void gen_adds(TCGv_i32 ret, TCGv_i32 r1, TCGv_i32 r2)
{
gen_helper_add_ssov(ret, tcg_env, r1, r2);
}
-static void gen_addsi(TCGv ret, TCGv r1, int32_t con)
+static void gen_addsi(TCGv_i32 ret, TCGv_i32 r1, int32_t con)
{
- TCGv temp = tcg_constant_i32(con);
+ TCGv_i32 temp = tcg_constant_i32(con);
gen_helper_add_ssov(ret, tcg_env, r1, temp);
}
-static void gen_addsui(TCGv ret, TCGv r1, int32_t con)
+static void gen_addsui(TCGv_i32 ret, TCGv_i32 r1, int32_t con)
{
- TCGv temp = tcg_constant_i32(con);
+ TCGv_i32 temp = tcg_constant_i32(con);
gen_helper_add_suov(ret, tcg_env, r1, temp);
}
-static void gen_subs(TCGv ret, TCGv r1, TCGv r2)
+static void gen_subs(TCGv_i32 ret, TCGv_i32 r1, TCGv_i32 r2)
{
gen_helper_sub_ssov(ret, tcg_env, r1, r2);
}
-static void gen_subsu(TCGv ret, TCGv r1, TCGv r2)
+static void gen_subsu(TCGv_i32 ret, TCGv_i32 r1, TCGv_i32 r2)
{
gen_helper_sub_suov(ret, tcg_env, r1, r2);
}
-static void gen_bit_2op(TCGv ret, TCGv r1, TCGv r2,
+static void gen_bit_2op(TCGv_i32 ret, TCGv_i32 r1, TCGv_i32 r2,
int pos1, int pos2,
- void(*op1)(TCGv, TCGv, TCGv),
- void(*op2)(TCGv, TCGv, TCGv))
+ void(*op1)(TCGv_i32, TCGv_i32, TCGv_i32),
+ void(*op2)(TCGv_i32, TCGv_i32, TCGv_i32))
{
- TCGv temp1, temp2;
+ TCGv_i32 temp1, temp2;
- temp1 = tcg_temp_new();
- temp2 = tcg_temp_new();
+ temp1 = tcg_temp_new_i32();
+ temp2 = tcg_temp_new_i32();
tcg_gen_shri_i32(temp2, r2, pos2);
tcg_gen_shri_i32(temp1, r1, pos1);
@@ -2632,14 +2664,14 @@ static void gen_bit_2op(TCGv ret, TCGv r1, TCGv r2,
}
/* ret = r1[pos1] op1 r2[pos2]; */
-static void gen_bit_1op(TCGv ret, TCGv r1, TCGv r2,
+static void gen_bit_1op(TCGv_i32 ret, TCGv_i32 r1, TCGv_i32 r2,
int pos1, int pos2,
- void(*op1)(TCGv, TCGv, TCGv))
+ void(*op1)(TCGv_i32, TCGv_i32, TCGv_i32))
{
- TCGv temp1, temp2;
+ TCGv_i32 temp1, temp2;
- temp1 = tcg_temp_new();
- temp2 = tcg_temp_new();
+ temp1 = tcg_temp_new_i32();
+ temp2 = tcg_temp_new_i32();
tcg_gen_shri_i32(temp2, r2, pos2);
tcg_gen_shri_i32(temp1, r1, pos1);
@@ -2649,11 +2681,12 @@ static void gen_bit_1op(TCGv ret, TCGv r1, TCGv r2,
tcg_gen_andi_i32(ret, ret, 0x1);
}
-static void gen_accumulating_cond(int cond, TCGv ret, TCGv r1, TCGv r2,
- void(*op)(TCGv, TCGv, TCGv))
+static void gen_accumulating_cond(int cond, TCGv_i32 ret,
+ TCGv_i32 r1, TCGv_i32 r2,
+ void(*op)(TCGv_i32, TCGv_i32, TCGv_i32))
{
- TCGv temp = tcg_temp_new();
- TCGv temp2 = tcg_temp_new();
+ TCGv_i32 temp = tcg_temp_new_i32();
+ TCGv_i32 temp2 = tcg_temp_new_i32();
/* temp = (arg1 cond arg2 )*/
tcg_gen_setcond_i32(cond, temp, r1, r2);
/* temp2 = ret[0]*/
@@ -2664,20 +2697,20 @@ static void gen_accumulating_cond(int cond, TCGv ret, TCGv r1, TCGv r2,
tcg_gen_deposit_i32(ret, ret, temp, 0, 1);
}
-static void
-gen_accumulating_condi(int cond, TCGv ret, TCGv r1, int32_t con,
- void(*op)(TCGv, TCGv, TCGv))
+static void gen_accumulating_condi(int cond, TCGv_i32 ret, TCGv_i32 r1,
+ int32_t con,
+ void(*op)(TCGv_i32, TCGv_i32, TCGv_i32))
{
- TCGv temp = tcg_constant_i32(con);
+ TCGv_i32 temp = tcg_constant_i32(con);
gen_accumulating_cond(cond, ret, r1, temp, op);
}
-static void gen_eqany_bi(TCGv ret, TCGv r1, int32_t con)
+static void gen_eqany_bi(TCGv_i32 ret, TCGv_i32 r1, int32_t con)
{
- TCGv b0 = tcg_temp_new();
- TCGv b1 = tcg_temp_new();
- TCGv b2 = tcg_temp_new();
- TCGv b3 = tcg_temp_new();
+ TCGv_i32 b0 = tcg_temp_new_i32();
+ TCGv_i32 b1 = tcg_temp_new_i32();
+ TCGv_i32 b2 = tcg_temp_new_i32();
+ TCGv_i32 b3 = tcg_temp_new_i32();
/* byte 0 */
tcg_gen_andi_i32(b0, r1, 0xff);
@@ -2701,10 +2734,10 @@ static void gen_eqany_bi(TCGv ret, TCGv r1, int32_t con)
tcg_gen_or_i32(ret, ret, b3);
}
-static void gen_eqany_hi(TCGv ret, TCGv r1, int32_t con)
+static void gen_eqany_hi(TCGv_i32 ret, TCGv_i32 r1, int32_t con)
{
- TCGv h0 = tcg_temp_new();
- TCGv h1 = tcg_temp_new();
+ TCGv_i32 h0 = tcg_temp_new_i32();
+ TCGv_i32 h1 = tcg_temp_new_i32();
/* halfword 0 */
tcg_gen_andi_i32(h0, r1, 0xffff);
@@ -2720,11 +2753,12 @@ static void gen_eqany_hi(TCGv ret, TCGv r1, int32_t con)
/* mask = ((1 << width) -1) << pos;
ret = (r1 & ~mask) | (r2 << pos) & mask); */
-static void gen_insert(TCGv ret, TCGv r1, TCGv r2, TCGv width, TCGv pos)
+static void gen_insert(TCGv_i32 ret,
+ TCGv_i32 r1, TCGv_i32 r2, TCGv_i32 width, TCGv_i32 pos)
{
- TCGv mask = tcg_temp_new();
- TCGv temp = tcg_temp_new();
- TCGv temp2 = tcg_temp_new();
+ TCGv_i32 mask = tcg_temp_new_i32();
+ TCGv_i32 temp = tcg_temp_new_i32();
+ TCGv_i32 temp2 = tcg_temp_new_i32();
tcg_gen_shl_i32(mask, tcg_constant_i32(1), width);
tcg_gen_subi_i32(mask, mask, 1);
@@ -2736,7 +2770,7 @@ static void gen_insert(TCGv ret, TCGv r1, TCGv r2, TCGv width, TCGv pos)
tcg_gen_or_i32(ret, temp, temp2);
}
-static void gen_bsplit(TCGv rl, TCGv rh, TCGv r1)
+static void gen_bsplit(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 r1)
{
TCGv_i64 temp = tcg_temp_new_i64();
@@ -2744,7 +2778,7 @@ static void gen_bsplit(TCGv rl, TCGv rh, TCGv r1)
tcg_gen_extr_i64_i32(rl, rh, temp);
}
-static void gen_unpack(TCGv rl, TCGv rh, TCGv r1)
+static void gen_unpack(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 r1)
{
TCGv_i64 temp = tcg_temp_new_i64();
@@ -2752,8 +2786,9 @@ static void gen_unpack(TCGv rl, TCGv rh, TCGv r1)
tcg_gen_extr_i64_i32(rl, rh, temp);
}
-static void
-gen_dvinit_b(DisasContext *ctx, TCGv rl, TCGv rh, TCGv r1, TCGv r2)
+static void gen_dvinit_b(DisasContext *ctx,
+ TCGv_i32 rl, TCGv_i32 rh,
+ TCGv_i32 r1, TCGv_i32 r2)
{
TCGv_i64 ret = tcg_temp_new_i64();
@@ -2765,8 +2800,9 @@ gen_dvinit_b(DisasContext *ctx, TCGv rl, TCGv rh, TCGv r1, TCGv r2)
tcg_gen_extr_i64_i32(rl, rh, ret);
}
-static void
-gen_dvinit_h(DisasContext *ctx, TCGv rl, TCGv rh, TCGv r1, TCGv r2)
+static void gen_dvinit_h(DisasContext *ctx,
+ TCGv_i32 rl, TCGv_i32 rh,
+ TCGv_i32 r1, TCGv_i32 r2)
{
TCGv_i64 ret = tcg_temp_new_i64();
@@ -2778,9 +2814,9 @@ gen_dvinit_h(DisasContext *ctx, TCGv rl, TCGv rh, TCGv r1, TCGv r2)
tcg_gen_extr_i64_i32(rl, rh, ret);
}
-static void gen_calc_usb_mul_h(TCGv arg_low, TCGv arg_high)
+static void gen_calc_usb_mul_h(TCGv_i32 arg_low, TCGv_i32 arg_high)
{
- TCGv temp = tcg_temp_new();
+ TCGv_i32 temp = tcg_temp_new_i32();
/* calc AV bit */
tcg_gen_add_i32(temp, arg_low, arg_low);
tcg_gen_xor_i32(temp, temp, arg_low);
@@ -2792,9 +2828,9 @@ static void gen_calc_usb_mul_h(TCGv arg_low, TCGv arg_high)
tcg_gen_movi_i32(cpu_PSW_V, 0);
}
-static void gen_calc_usb_mulr_h(TCGv arg)
+static void gen_calc_usb_mulr_h(TCGv_i32 arg)
{
- TCGv temp = tcg_temp_new();
+ TCGv_i32 temp = tcg_temp_new_i32();
/* calc AV bit */
tcg_gen_add_i32(temp, arg, arg);
tcg_gen_xor_i32(temp, temp, arg);
@@ -2836,8 +2872,8 @@ static void generate_trap(DisasContext *ctx, int class, int tin)
ctx->base.is_jmp = DISAS_NORETURN;
}
-static void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1,
- TCGv r2, int16_t address)
+static void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv_i32 r1,
+ TCGv_i32 r2, int16_t address)
{
TCGLabel *jumpLabel = gen_new_label();
tcg_gen_brcond_i32(cond, r1, r2, jumpLabel);
@@ -2848,10 +2884,10 @@ static void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1,
gen_goto_tb(ctx, 0, ctx->base.pc_next + address * 2);
}
-static void gen_branch_condi(DisasContext *ctx, TCGCond cond, TCGv r1,
+static void gen_branch_condi(DisasContext *ctx, TCGCond cond, TCGv_i32 r1,
int r2, int16_t address)
{
- TCGv temp = tcg_constant_i32(r2);
+ TCGv_i32 temp = tcg_constant_i32(r2);
gen_branch_cond(ctx, cond, r1, temp, address);
}
@@ -2868,7 +2904,7 @@ static void gen_loop(DisasContext *ctx, int r1, int32_t offset)
static void gen_fcall_save_ctx(DisasContext *ctx)
{
- TCGv temp = tcg_temp_new();
+ TCGv_i32 temp = tcg_temp_new_i32();
tcg_gen_addi_i32(temp, cpu_gpr_a[10], -4);
tcg_gen_qemu_st_i32(cpu_gpr_a[11], temp, ctx->mem_idx, MO_LESL);
@@ -2878,7 +2914,7 @@ static void gen_fcall_save_ctx(DisasContext *ctx)
static void gen_fret(DisasContext *ctx)
{
- TCGv temp = tcg_temp_new();
+ TCGv_i32 temp = tcg_temp_new_i32();
tcg_gen_andi_i32(temp, cpu_gpr_a[11], ~0x1);
tcg_gen_qemu_ld_i32(cpu_gpr_a[11], cpu_gpr_a[10], ctx->mem_idx, MO_LESL);
@@ -2890,7 +2926,7 @@ static void gen_fret(DisasContext *ctx)
static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
int r2 , int32_t constant , int32_t offset)
{
- TCGv temp, temp2;
+ TCGv_i32 temp, temp2;
int n;
switch (opc) {
@@ -2927,12 +2963,12 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
break;
/* SBRN-format jumps */
case OPC1_16_SBRN_JZ_T:
- temp = tcg_temp_new();
+ temp = tcg_temp_new_i32();
tcg_gen_andi_i32(temp, cpu_gpr_d[15], 0x1u << constant);
gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset);
break;
case OPC1_16_SBRN_JNZ_T:
- temp = tcg_temp_new();
+ temp = tcg_temp_new_i32();
tcg_gen_andi_i32(temp, cpu_gpr_d[15], 0x1u << constant);
gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset);
break;
@@ -3040,7 +3076,7 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
}
break;
case OPCM_32_BRC_JNE:
- temp = tcg_temp_new();
+ temp = tcg_temp_new_i32();
if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JNED) {
tcg_gen_mov_i32(temp, cpu_gpr_d[r1]);
/* subi is unconditional */
@@ -3057,7 +3093,7 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
case OPCM_32_BRN_JTT:
n = MASK_OP_BRN_N(ctx->opcode);
- temp = tcg_temp_new();
+ temp = tcg_temp_new_i32();
tcg_gen_andi_i32(temp, cpu_gpr_d[r1], (1 << n));
if (MASK_OP_BRN_OP2(ctx->opcode) == OPC2_32_BRN_JNZ_T) {
@@ -3112,8 +3148,8 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
}
break;
case OPCM_32_BRR_JNE:
- temp = tcg_temp_new();
- temp2 = tcg_temp_new();
+ temp = tcg_temp_new_i32();
+ temp2 = tcg_temp_new_i32();
if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRR_JNED) {
tcg_gen_mov_i32(temp, cpu_gpr_d[r1]);
/* also save r2, in case of r1 == r2, so r2 is not decremented */
@@ -3151,7 +3187,7 @@ static void decode_src_opc(DisasContext *ctx, int op1)
{
int r1;
int32_t const4;
- TCGv temp, temp2;
+ TCGv_i32 temp, temp2;
r1 = MASK_OP_SRC_S1D(ctx->opcode);
const4 = MASK_OP_SRC_CONST4_SEXT(ctx->opcode);
@@ -3227,7 +3263,7 @@ static void decode_src_opc(DisasContext *ctx, int op1)
static void decode_srr_opc(DisasContext *ctx, int op1)
{
int r1, r2;
- TCGv temp;
+ TCGv_i32 temp;
r1 = MASK_OP_SRR_S1D(ctx->opcode);
r2 = MASK_OP_SRR_S2(ctx->opcode);
@@ -3545,7 +3581,7 @@ static void decode_16Bit_opc(DisasContext *ctx)
int r1, r2;
int32_t const16;
int32_t address;
- TCGv temp;
+ TCGv_i32 temp;
op1 = MASK_OP_MAJOR(ctx->opcode);
@@ -3612,7 +3648,7 @@ static void decode_16Bit_opc(DisasContext *ctx)
r2 = MASK_OP_SRRS_S2(ctx->opcode);
r1 = MASK_OP_SRRS_S1D(ctx->opcode);
const16 = MASK_OP_SRRS_N(ctx->opcode);
- temp = tcg_temp_new();
+ temp = tcg_temp_new_i32();
tcg_gen_shli_i32(temp, cpu_gpr_d[15], const16);
tcg_gen_add_i32(cpu_gpr_a[r1], cpu_gpr_a[r2], temp);
break;
@@ -3780,7 +3816,7 @@ static void decode_abs_ldw(DisasContext *ctx)
int32_t op2;
int32_t r1;
uint32_t address;
- TCGv temp;
+ TCGv_i32 temp;
r1 = MASK_OP_ABS_S1D(ctx->opcode);
address = MASK_OP_ABS_OFF18(ctx->opcode);
@@ -3813,7 +3849,7 @@ static void decode_abs_ldb(DisasContext *ctx)
int32_t op2;
int32_t r1;
uint32_t address;
- TCGv temp;
+ TCGv_i32 temp;
r1 = MASK_OP_ABS_S1D(ctx->opcode);
address = MASK_OP_ABS_OFF18(ctx->opcode);
@@ -3844,7 +3880,7 @@ static void decode_abs_ldst_swap(DisasContext *ctx)
int32_t op2;
int32_t r1;
uint32_t address;
- TCGv temp;
+ TCGv_i32 temp;
r1 = MASK_OP_ABS_S1D(ctx->opcode);
address = MASK_OP_ABS_OFF18(ctx->opcode);
@@ -3895,7 +3931,7 @@ static void decode_abs_store(DisasContext *ctx)
int32_t op2;
int32_t r1;
uint32_t address;
- TCGv temp;
+ TCGv_i32 temp;
r1 = MASK_OP_ABS_S1D(ctx->opcode);
address = MASK_OP_ABS_OFF18(ctx->opcode);
@@ -3928,7 +3964,7 @@ static void decode_abs_storeb_h(DisasContext *ctx)
int32_t op2;
int32_t r1;
uint32_t address;
- TCGv temp;
+ TCGv_i32 temp;
r1 = MASK_OP_ABS_S1D(ctx->opcode);
address = MASK_OP_ABS_OFF18(ctx->opcode);
@@ -4030,7 +4066,7 @@ static void decode_bit_insert(DisasContext *ctx)
uint32_t op2;
int r1, r2, r3;
int pos1, pos2;
- TCGv temp;
+ TCGv_i32 temp;
op2 = MASK_OP_BIT_OP2(ctx->opcode);
r1 = MASK_OP_BIT_S1(ctx->opcode);
r2 = MASK_OP_BIT_S2(ctx->opcode);
@@ -4038,7 +4074,7 @@ static void decode_bit_insert(DisasContext *ctx)
pos1 = MASK_OP_BIT_POS1(ctx->opcode);
pos2 = MASK_OP_BIT_POS2(ctx->opcode);
- temp = tcg_temp_new();
+ temp = tcg_temp_new_i32();
tcg_gen_shri_i32(temp, cpu_gpr_d[r2], pos2);
if (op2 == OPC2_32_BIT_INSN_T) {
@@ -4129,7 +4165,7 @@ static void decode_bit_sh_logic1(DisasContext *ctx)
uint32_t op2;
int r1, r2, r3;
int pos1, pos2;
- TCGv temp;
+ TCGv_i32 temp;
op2 = MASK_OP_BIT_OP2(ctx->opcode);
r1 = MASK_OP_BIT_S1(ctx->opcode);
@@ -4138,7 +4174,7 @@ static void decode_bit_sh_logic1(DisasContext *ctx)
pos1 = MASK_OP_BIT_POS1(ctx->opcode);
pos2 = MASK_OP_BIT_POS2(ctx->opcode);
- temp = tcg_temp_new();
+ temp = tcg_temp_new_i32();
switch (op2) {
case OPC2_32_BIT_SH_AND_T:
@@ -4169,7 +4205,7 @@ static void decode_bit_sh_logic2(DisasContext *ctx)
uint32_t op2;
int r1, r2, r3;
int pos1, pos2;
- TCGv temp;
+ TCGv_i32 temp;
op2 = MASK_OP_BIT_OP2(ctx->opcode);
r1 = MASK_OP_BIT_S1(ctx->opcode);
@@ -4178,7 +4214,7 @@ static void decode_bit_sh_logic2(DisasContext *ctx)
pos1 = MASK_OP_BIT_POS1(ctx->opcode);
pos2 = MASK_OP_BIT_POS2(ctx->opcode);
- temp = tcg_temp_new();
+ temp = tcg_temp_new_i32();
switch (op2) {
case OPC2_32_BIT_SH_NAND_T:
@@ -4212,7 +4248,7 @@ static void decode_bo_addrmode_post_pre_base(DisasContext *ctx)
uint32_t op2;
uint32_t off10;
int32_t r1, r2;
- TCGv temp;
+ TCGv_i32 temp;
r1 = MASK_OP_BO_S1D(ctx->opcode);
r2 = MASK_OP_BO_S2(ctx->opcode);
@@ -4295,7 +4331,7 @@ static void decode_bo_addrmode_post_pre_base(DisasContext *ctx)
break;
case OPC2_32_BO_ST_D_PREINC:
CHECK_REG_PAIR(r1);
- temp = tcg_temp_new();
+ temp = tcg_temp_new_i32();
tcg_gen_addi_i32(temp, cpu_gpr_a[r2], off10);
gen_st_2regs_64(ctx, cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], temp);
tcg_gen_mov_i32(cpu_gpr_a[r2], temp);
@@ -4312,7 +4348,7 @@ static void decode_bo_addrmode_post_pre_base(DisasContext *ctx)
break;
case OPC2_32_BO_ST_DA_PREINC:
CHECK_REG_PAIR(r1);
- temp = tcg_temp_new();
+ temp = tcg_temp_new_i32();
tcg_gen_addi_i32(temp, cpu_gpr_a[r2], off10);
gen_st_2regs_64(ctx, cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], temp);
tcg_gen_mov_i32(cpu_gpr_a[r2], temp);
@@ -4329,19 +4365,19 @@ static void decode_bo_addrmode_post_pre_base(DisasContext *ctx)
gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
break;
case OPC2_32_BO_ST_Q_SHORTOFF:
- temp = tcg_temp_new();
+ temp = tcg_temp_new_i32();
tcg_gen_shri_i32(temp, cpu_gpr_d[r1], 16);
gen_offset_st(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW);
break;
case OPC2_32_BO_ST_Q_POSTINC:
- temp = tcg_temp_new();
+ temp = tcg_temp_new_i32();
tcg_gen_shri_i32(temp, cpu_gpr_d[r1], 16);
tcg_gen_qemu_st_i32(temp, cpu_gpr_a[r2], ctx->mem_idx,
MO_LEUW);
tcg_gen_addi_i32(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_ST_Q_PREINC:
- temp = tcg_temp_new();
+ temp = tcg_temp_new_i32();
tcg_gen_shri_i32(temp, cpu_gpr_d[r1], 16);
gen_st_preincr(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW);
break;
@@ -4366,15 +4402,15 @@ static void decode_bo_addrmode_bitreverse_circular(DisasContext *ctx)
uint32_t op2;
uint32_t off10;
int32_t r1, r2;
- TCGv temp, temp2, t_off10;
+ TCGv_i32 temp, temp2, t_off10;
r1 = MASK_OP_BO_S1D(ctx->opcode);
r2 = MASK_OP_BO_S2(ctx->opcode);
off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
op2 = MASK_OP_BO_OP2(ctx->opcode);
- temp = tcg_temp_new();
- temp2 = tcg_temp_new();
+ temp = tcg_temp_new_i32();
+ temp2 = tcg_temp_new_i32();
t_off10 = tcg_constant_i32(off10);
CHECK_REG_PAIR(r2);
tcg_gen_ext16u_i32(temp, cpu_gpr_a[r2 + 1]);
@@ -4473,7 +4509,7 @@ static void decode_bo_addrmode_ld_post_pre_base(DisasContext *ctx)
uint32_t op2;
uint32_t off10;
int32_t r1, r2;
- TCGv temp;
+ TCGv_i32 temp;
r1 = MASK_OP_BO_S1D(ctx->opcode);
r2 = MASK_OP_BO_S2(ctx->opcode);
@@ -4526,7 +4562,7 @@ static void decode_bo_addrmode_ld_post_pre_base(DisasContext *ctx)
break;
case OPC2_32_BO_LD_D_PREINC:
CHECK_REG_PAIR(r1);
- temp = tcg_temp_new();
+ temp = tcg_temp_new_i32();
tcg_gen_addi_i32(temp, cpu_gpr_a[r2], off10);
gen_ld_2regs_64(ctx, cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], temp);
tcg_gen_mov_i32(cpu_gpr_a[r2], temp);
@@ -4543,7 +4579,7 @@ static void decode_bo_addrmode_ld_post_pre_base(DisasContext *ctx)
break;
case OPC2_32_BO_LD_DA_PREINC:
CHECK_REG_PAIR(r1);
- temp = tcg_temp_new();
+ temp = tcg_temp_new_i32();
tcg_gen_addi_i32(temp, cpu_gpr_a[r2], off10);
gen_ld_2regs_64(ctx, cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], temp);
tcg_gen_mov_i32(cpu_gpr_a[r2], temp);
@@ -4605,15 +4641,15 @@ static void decode_bo_addrmode_ld_bitreverse_circular(DisasContext *ctx)
uint32_t op2;
uint32_t off10;
int r1, r2;
- TCGv temp, temp2, t_off10;
+ TCGv_i32 temp, temp2, t_off10;
r1 = MASK_OP_BO_S1D(ctx->opcode);
r2 = MASK_OP_BO_S2(ctx->opcode);
off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
op2 = MASK_OP_BO_OP2(ctx->opcode);
- temp = tcg_temp_new();
- temp2 = tcg_temp_new();
+ temp = tcg_temp_new_i32();
+ temp2 = tcg_temp_new_i32();
t_off10 = tcg_constant_i32(off10);
CHECK_REG_PAIR(r2);
tcg_gen_ext16u_i32(temp, cpu_gpr_a[r2 + 1]);
@@ -4720,7 +4756,7 @@ static void decode_bo_addrmode_stctx_post_pre_base(DisasContext *ctx)
uint32_t off10;
int r1, r2;
- TCGv temp;
+ TCGv_i32 temp;
r1 = MASK_OP_BO_S1D(ctx->opcode);
r2 = MASK_OP_BO_S2(ctx->opcode);
@@ -4728,7 +4764,7 @@ static void decode_bo_addrmode_stctx_post_pre_base(DisasContext *ctx)
op2 = MASK_OP_BO_OP2(ctx->opcode);
- temp = tcg_temp_new();
+ temp = tcg_temp_new_i32();
switch (op2) {
case OPC2_32_BO_LDLCX_SHORTOFF:
@@ -4808,15 +4844,15 @@ static void decode_bo_addrmode_ldmst_bitreverse_circular(DisasContext *ctx)
uint32_t op2;
uint32_t off10;
int r1, r2;
- TCGv temp, temp2, t_off10;
+ TCGv_i32 temp, temp2, t_off10;
r1 = MASK_OP_BO_S1D(ctx->opcode);
r2 = MASK_OP_BO_S2(ctx->opcode);
off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
op2 = MASK_OP_BO_OP2(ctx->opcode);
- temp = tcg_temp_new();
- temp2 = tcg_temp_new();
+ temp = tcg_temp_new_i32();
+ temp2 = tcg_temp_new_i32();
t_off10 = tcg_constant_i32(off10);
CHECK_REG_PAIR(r2);
tcg_gen_ext16u_i32(temp, cpu_gpr_a[r2 + 1]);
@@ -4864,7 +4900,7 @@ static void decode_bol_opc(DisasContext *ctx, int32_t op1)
{
int r1, r2;
int32_t address;
- TCGv temp;
+ TCGv_i32 temp;
r1 = MASK_OP_BOL_S1D(ctx->opcode);
r2 = MASK_OP_BOL_S2(ctx->opcode);
@@ -4872,12 +4908,12 @@ static void decode_bol_opc(DisasContext *ctx, int32_t op1)
switch (op1) {
case OPC1_32_BOL_LD_A_LONGOFF:
- temp = tcg_temp_new();
+ temp = tcg_temp_new_i32();
tcg_gen_addi_i32(temp, cpu_gpr_a[r2], address);
tcg_gen_qemu_ld_i32(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LEUL);
break;
case OPC1_32_BOL_LD_W_LONGOFF:
- temp = tcg_temp_new();
+ temp = tcg_temp_new_i32();
tcg_gen_addi_i32(temp, cpu_gpr_a[r2], address);
tcg_gen_qemu_ld_i32(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUL);
break;
@@ -4947,7 +4983,7 @@ static void decode_rc_logical_shift(DisasContext *ctx)
uint32_t op2;
int r1, r2;
int32_t const9;
- TCGv temp;
+ TCGv_i32 temp;
r2 = MASK_OP_RC_D(ctx->opcode);
r1 = MASK_OP_RC_S1(ctx->opcode);
@@ -4962,12 +4998,12 @@ static void decode_rc_logical_shift(DisasContext *ctx)
tcg_gen_andi_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9);
break;
case OPC2_32_RC_NAND:
- temp = tcg_temp_new();
+ temp = tcg_temp_new_i32();
tcg_gen_movi_i32(temp, const9);
tcg_gen_nand_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], temp);
break;
case OPC2_32_RC_NOR:
- temp = tcg_temp_new();
+ temp = tcg_temp_new_i32();
tcg_gen_movi_i32(temp, const9);
tcg_gen_nor_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], temp);
break;
@@ -5022,7 +5058,7 @@ static void decode_rc_accumulator(DisasContext *ctx)
int r1, r2;
int16_t const9;
- TCGv temp;
+ TCGv_i32 temp;
r2 = MASK_OP_RC_D(ctx->opcode);
r1 = MASK_OP_RC_S1(ctx->opcode);
@@ -5030,7 +5066,7 @@ static void decode_rc_accumulator(DisasContext *ctx)
op2 = MASK_OP_RC_OP2(ctx->opcode);
- temp = tcg_temp_new();
+ temp = tcg_temp_new_i32();
switch (op2) {
case OPC2_32_RC_ABSDIF:
@@ -5283,7 +5319,7 @@ static void decode_rcpw_insert(DisasContext *ctx)
int r1, r2;
int32_t pos, width, const4;
- TCGv temp;
+ TCGv_i32 temp;
op2 = MASK_OP_RCPW_OP2(ctx->opcode);
r1 = MASK_OP_RCPW_S1(ctx->opcode);
@@ -5324,7 +5360,7 @@ static void decode_rcrw_insert(DisasContext *ctx)
int r1, r3, r4;
int32_t width, const4;
- TCGv temp, temp2, temp3;
+ TCGv_i32 temp, temp2, temp3;
op2 = MASK_OP_RCRW_OP2(ctx->opcode);
r1 = MASK_OP_RCRW_S1(ctx->opcode);
@@ -5333,8 +5369,8 @@ static void decode_rcrw_insert(DisasContext *ctx)
width = MASK_OP_RCRW_WIDTH(ctx->opcode);
const4 = MASK_OP_RCRW_CONST4(ctx->opcode);
- temp = tcg_temp_new();
- temp2 = tcg_temp_new();
+ temp = tcg_temp_new_i32();
+ temp2 = tcg_temp_new_i32();
switch (op2) {
case OPC2_32_RCRW_IMASK:
@@ -5346,7 +5382,7 @@ static void decode_rcrw_insert(DisasContext *ctx)
tcg_gen_shl_i32(cpu_gpr_d[r4], temp2, temp);
break;
case OPC2_32_RCRW_INSERT:
- temp3 = tcg_temp_new();
+ temp3 = tcg_temp_new_i32();
tcg_gen_movi_i32(temp, width);
tcg_gen_movi_i32(temp2, const4);
@@ -5366,7 +5402,7 @@ static void decode_rcr_cond_select(DisasContext *ctx)
int r1, r3, r4;
int32_t const9;
- TCGv temp, temp2;
+ TCGv_i32 temp, temp2;
op2 = MASK_OP_RCR_OP2(ctx->opcode);
r1 = MASK_OP_RCR_S1(ctx->opcode);
@@ -5573,7 +5609,7 @@ static void decode_rr_accumulator(DisasContext *ctx)
uint32_t op2;
int r3, r2, r1;
- TCGv temp;
+ TCGv_i32 temp;
r3 = MASK_OP_RR_D(ctx->opcode);
r2 = MASK_OP_RR_S2(ctx->opcode);
@@ -5770,7 +5806,7 @@ static void decode_rr_accumulator(DisasContext *ctx)
break;
case OPC2_32_RR_MOV_64:
if (has_feature(ctx, TRICORE_FEATURE_16)) {
- temp = tcg_temp_new();
+ temp = tcg_temp_new_i32();
CHECK_REG_PAIR(r3);
tcg_gen_mov_i32(temp, cpu_gpr_d[r1]);
@@ -5989,7 +6025,7 @@ static void decode_rr_address(DisasContext *ctx)
{
uint32_t op2, n;
int r1, r2, r3;
- TCGv temp;
+ TCGv_i32 temp;
op2 = MASK_OP_RR_OP2(ctx->opcode);
r3 = MASK_OP_RR_D(ctx->opcode);
@@ -6002,12 +6038,12 @@ static void decode_rr_address(DisasContext *ctx)
tcg_gen_add_i32(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]);
break;
case OPC2_32_RR_ADDSC_A:
- temp = tcg_temp_new();
+ temp = tcg_temp_new_i32();
tcg_gen_shli_i32(temp, cpu_gpr_d[r1], n);
tcg_gen_add_i32(cpu_gpr_a[r3], cpu_gpr_a[r2], temp);
break;
case OPC2_32_RR_ADDSC_AT:
- temp = tcg_temp_new();
+ temp = tcg_temp_new_i32();
tcg_gen_sari_i32(temp, cpu_gpr_d[r1], 3);
tcg_gen_add_i32(temp, cpu_gpr_a[r2], temp);
tcg_gen_andi_i32(cpu_gpr_a[r3], temp, 0xFFFFFFFC);
@@ -6087,7 +6123,7 @@ static void decode_rr_divide(DisasContext *ctx)
uint32_t op2;
int r1, r2, r3;
- TCGv temp, temp2, temp3;
+ TCGv_i32 temp, temp2, temp3;
op2 = MASK_OP_RR_OP2(ctx->opcode);
r3 = MASK_OP_RR_D(ctx->opcode);
@@ -6108,9 +6144,9 @@ static void decode_rr_divide(DisasContext *ctx)
cpu_gpr_d[r2]);
break;
case OPC2_32_RR_DVINIT_BU:
- temp = tcg_temp_new();
- temp2 = tcg_temp_new();
- temp3 = tcg_temp_new();
+ temp = tcg_temp_new_i32();
+ temp2 = tcg_temp_new_i32();
+ temp3 = tcg_temp_new_i32();
CHECK_REG_PAIR(r3);
tcg_gen_shri_i32(temp3, cpu_gpr_d[r1], 8);
/* reset av */
@@ -6137,9 +6173,9 @@ static void decode_rr_divide(DisasContext *ctx)
cpu_gpr_d[r2]);
break;
case OPC2_32_RR_DVINIT_HU:
- temp = tcg_temp_new();
- temp2 = tcg_temp_new();
- temp3 = tcg_temp_new();
+ temp = tcg_temp_new_i32();
+ temp2 = tcg_temp_new_i32();
+ temp3 = tcg_temp_new_i32();
CHECK_REG_PAIR(r3);
tcg_gen_shri_i32(temp3, cpu_gpr_d[r1], 16);
/* reset av */
@@ -6161,8 +6197,8 @@ static void decode_rr_divide(DisasContext *ctx)
tcg_gen_mov_i32(cpu_gpr_d[r3 + 1], temp3);
break;
case OPC2_32_RR_DVINIT:
- temp = tcg_temp_new();
- temp2 = tcg_temp_new();
+ temp = tcg_temp_new_i32();
+ temp2 = tcg_temp_new_i32();
CHECK_REG_PAIR(r3);
/* overflow = ((D[b] == 0) ||
((D[b] == 0xFFFFFFFF) && (D[a] == 0x80000000))) */
@@ -6311,7 +6347,7 @@ static void decode_rr1_mul(DisasContext *ctx)
uint32_t op2;
int r1, r2, r3;
- TCGv n;
+ TCGv_i32 n;
TCGv_i64 temp64;
r1 = MASK_OP_RR1_S1(ctx->opcode);
@@ -6416,7 +6452,7 @@ static void decode_rr1_mulq(DisasContext *ctx)
int r1, r2, r3;
uint32_t n;
- TCGv temp, temp2;
+ TCGv_i32 temp, temp2;
r1 = MASK_OP_RR1_S1(ctx->opcode);
r2 = MASK_OP_RR1_S2(ctx->opcode);
@@ -6424,8 +6460,8 @@ static void decode_rr1_mulq(DisasContext *ctx)
n = MASK_OP_RR1_N(ctx->opcode);
op2 = MASK_OP_RR1_OP2(ctx->opcode);
- temp = tcg_temp_new();
- temp2 = tcg_temp_new();
+ temp = tcg_temp_new_i32();
+ temp2 = tcg_temp_new_i32();
switch (op2) {
case OPC2_32_RR1_MUL_Q_32:
@@ -6522,7 +6558,7 @@ static void decode_rrpw_extract_insert(DisasContext *ctx)
uint32_t op2;
int r1, r2, r3;
int32_t pos, width;
- TCGv temp;
+ TCGv_i32 temp;
op2 = MASK_OP_RRPW_OP2(ctx->opcode);
r1 = MASK_OP_RRPW_S1(ctx->opcode);
@@ -6550,7 +6586,7 @@ static void decode_rrpw_extract_insert(DisasContext *ctx)
CHECK_REG_PAIR(r3);
if (pos + width <= 32) {
- temp = tcg_temp_new();
+ temp = tcg_temp_new_i32();
tcg_gen_movi_i32(temp, ((1u << width) - 1) << pos);
tcg_gen_shli_i32(cpu_gpr_d[r3], cpu_gpr_d[r2], pos);
tcg_gen_mov_i32(cpu_gpr_d[r3 + 1], temp);
@@ -6576,7 +6612,7 @@ static void decode_rrr_cond_select(DisasContext *ctx)
{
uint32_t op2;
int r1, r2, r3, r4;
- TCGv temp;
+ TCGv_i32 temp;
op2 = MASK_OP_RRR_OP2(ctx->opcode);
r1 = MASK_OP_RRR_S1(ctx->opcode);
@@ -6960,7 +6996,7 @@ static void decode_rrr1_maddq_h(DisasContext *ctx)
{
uint32_t op2;
uint32_t r1, r2, r3, r4, n;
- TCGv temp, temp2;
+ TCGv_i32 temp, temp2;
op2 = MASK_OP_RRR1_OP2(ctx->opcode);
r1 = MASK_OP_RRR1_S1(ctx->opcode);
@@ -6969,8 +7005,8 @@ static void decode_rrr1_maddq_h(DisasContext *ctx)
r4 = MASK_OP_RRR1_D(ctx->opcode);
n = MASK_OP_RRR1_N(ctx->opcode);
- temp = tcg_temp_new();
- temp2 = tcg_temp_new();
+ temp = tcg_temp_new_i32();
+ temp2 = tcg_temp_new_i32();
switch (op2) {
case OPC2_32_RRR1_MADD_Q_32:
@@ -7442,7 +7478,7 @@ static void decode_rrr1_msubq_h(DisasContext *ctx)
{
uint32_t op2;
uint32_t r1, r2, r3, r4, n;
- TCGv temp, temp2;
+ TCGv_i32 temp, temp2;
op2 = MASK_OP_RRR1_OP2(ctx->opcode);
r1 = MASK_OP_RRR1_S1(ctx->opcode);
@@ -7451,8 +7487,8 @@ static void decode_rrr1_msubq_h(DisasContext *ctx)
r4 = MASK_OP_RRR1_D(ctx->opcode);
n = MASK_OP_RRR1_N(ctx->opcode);
- temp = tcg_temp_new();
- temp2 = tcg_temp_new();
+ temp = tcg_temp_new_i32();
+ temp2 = tcg_temp_new_i32();
switch (op2) {
case OPC2_32_RRR1_MSUB_Q_32:
@@ -7779,7 +7815,7 @@ static void decode_rrrr_extract_insert(DisasContext *ctx)
{
uint32_t op2;
int r1, r2, r3, r4;
- TCGv tmp_width, tmp_pos;
+ TCGv_i32 tmp_width, tmp_pos;
r1 = MASK_OP_RRRR_S1(ctx->opcode);
r2 = MASK_OP_RRRR_S2(ctx->opcode);
@@ -7787,8 +7823,8 @@ static void decode_rrrr_extract_insert(DisasContext *ctx)
r4 = MASK_OP_RRRR_D(ctx->opcode);
op2 = MASK_OP_RRRR_OP2(ctx->opcode);
- tmp_pos = tcg_temp_new();
- tmp_width = tcg_temp_new();
+ tmp_pos = tcg_temp_new_i32();
+ tmp_width = tcg_temp_new_i32();
switch (op2) {
case OPC2_32_RRRR_DEXTR:
@@ -7796,8 +7832,8 @@ static void decode_rrrr_extract_insert(DisasContext *ctx)
if (r1 == r2) {
tcg_gen_rotl_i32(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos);
} else {
- TCGv msw = tcg_temp_new();
- TCGv zero = tcg_constant_i32(0);
+ TCGv_i32 msw = tcg_temp_new_i32();
+ TCGv_i32 zero = tcg_constant_i32(0);
tcg_gen_shl_i32(tmp_width, cpu_gpr_d[r1], tmp_pos);
tcg_gen_subfi_i32(msw, 32, tmp_pos);
tcg_gen_shr_i32(msw, cpu_gpr_d[r2], msw);
@@ -7844,7 +7880,7 @@ static void decode_rrrw_extract_insert(DisasContext *ctx)
int r1, r2, r3, r4;
int32_t width;
- TCGv temp, temp2;
+ TCGv_i32 temp, temp2;
op2 = MASK_OP_RRRW_OP2(ctx->opcode);
r1 = MASK_OP_RRRW_S1(ctx->opcode);
@@ -7853,7 +7889,7 @@ static void decode_rrrw_extract_insert(DisasContext *ctx)
r4 = MASK_OP_RRRW_D(ctx->opcode);
width = MASK_OP_RRRW_WIDTH(ctx->opcode);
- temp = tcg_temp_new();
+ temp = tcg_temp_new_i32();
switch (op2) {
case OPC2_32_RRRW_EXTR:
@@ -7873,7 +7909,7 @@ static void decode_rrrw_extract_insert(DisasContext *ctx)
}
break;
case OPC2_32_RRRW_IMASK:
- temp2 = tcg_temp_new();
+ temp2 = tcg_temp_new_i32();
CHECK_REG_PAIR(r4);
tcg_gen_andi_i32(temp, cpu_gpr_d[r3], 0x1f);
tcg_gen_movi_i32(temp2, (1 << width) - 1);
@@ -7882,7 +7918,7 @@ static void decode_rrrw_extract_insert(DisasContext *ctx)
tcg_gen_mov_i32(cpu_gpr_d[r4 + 1], temp2);
break;
case OPC2_32_RRRW_INSERT:
- temp2 = tcg_temp_new();
+ temp2 = tcg_temp_new_i32();
tcg_gen_movi_i32(temp, width);
tcg_gen_andi_i32(temp2, cpu_gpr_d[r3], 0x1f);
@@ -7899,7 +7935,7 @@ static void decode_sys_interrupts(DisasContext *ctx)
uint32_t op2;
uint32_t r1;
TCGLabel *l1;
- TCGv tmp;
+ TCGv_i32 tmp;
op2 = MASK_OP_SYS_OP2(ctx->opcode);
r1 = MASK_OP_SYS_S1D(ctx->opcode);
@@ -7953,7 +7989,7 @@ static void decode_sys_interrupts(DisasContext *ctx)
break;
case OPC2_32_SYS_RFM:
if (ctx->priv == TRICORE_PRIV_SM) {
- tmp = tcg_temp_new();
+ tmp = tcg_temp_new_i32();
l1 = gen_new_label();
tcg_gen_ld_i32(tmp, tcg_env, offsetof(CPUTriCoreState, DBGSR));
@@ -8009,7 +8045,7 @@ static void decode_32Bit_opc(DisasContext *ctx)
int32_t address, const16;
int8_t b, const4;
int32_t bpos;
- TCGv temp, temp2, temp3;
+ TCGv_i32 temp, temp2, temp3;
op1 = MASK_OP_MAJOR(ctx->opcode);
@@ -8042,7 +8078,7 @@ static void decode_32Bit_opc(DisasContext *ctx)
address = MASK_OP_ABS_OFF18(ctx->opcode);
r1 = MASK_OP_ABS_S1D(ctx->opcode);
temp = tcg_constant_i32(EA_ABS_FORMAT(address));
- temp2 = tcg_temp_new();
+ temp2 = tcg_temp_new_i32();
tcg_gen_shri_i32(temp2, cpu_gpr_d[r1], 16);
tcg_gen_qemu_st_i32(temp2, temp, ctx->mem_idx, MO_LEUW);
@@ -8077,7 +8113,7 @@ static void decode_32Bit_opc(DisasContext *ctx)
bpos = MASK_OP_ABSB_BPOS(ctx->opcode);
temp = tcg_constant_i32(EA_ABS_FORMAT(address));
- temp2 = tcg_temp_new();
+ temp2 = tcg_temp_new_i32();
tcg_gen_qemu_ld_i32(temp2, temp, ctx->mem_idx, MO_UB);
tcg_gen_andi_i32(temp2, temp2, ~(0x1u << bpos));
@@ -8204,8 +8240,8 @@ static void decode_32Bit_opc(DisasContext *ctx)
r3 = MASK_OP_RCRR_D(ctx->opcode);
const16 = MASK_OP_RCRR_CONST4(ctx->opcode);
temp = tcg_constant_i32(const16);
- temp2 = tcg_temp_new(); /* width*/
- temp3 = tcg_temp_new(); /* pos */
+ temp2 = tcg_temp_new_i32(); /* width*/
+ temp3 = tcg_temp_new_i32(); /* pos */
CHECK_REG_PAIR(r2);
--
2.51.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH 01/12] target/tricore: Remove target_ulong use in gen_goto_tb()
2025-10-10 5:21 ` [PATCH 01/12] target/tricore: Remove target_ulong use in gen_goto_tb() Philippe Mathieu-Daudé
@ 2025-10-10 16:56 ` Richard Henderson
0 siblings, 0 replies; 25+ messages in thread
From: Richard Henderson @ 2025-10-10 16:56 UTC (permalink / raw)
To: qemu-devel
On 10/9/25 22:21, Philippe Mathieu-Daudé wrote:
> translator_use_goto_tb() expects a vaddr type since commit
> b1c09220b4c ("accel/tcg: Replace target_ulong with vaddr in
> translator_*()").
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> target/tricore/translate.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/target/tricore/translate.c b/target/tricore/translate.c
> index 7c6e3095971..dd09f0651f5 100644
> --- a/target/tricore/translate.c
> +++ b/target/tricore/translate.c
> @@ -72,7 +72,8 @@ static const char *regnames_d[] = {
>
> typedef struct DisasContext {
> DisasContextBase base;
> - target_ulong pc_succ_insn;
> +
> + vaddr pc_succ_insn;
> uint32_t opcode;
> /* Routine used to access memory */
> int mem_idx;
> @@ -2811,13 +2812,12 @@ static void gen_calc_usb_mulr_h(TCGv arg)
>
> /* helpers for generating program flow micro-ops */
>
> -static inline void gen_save_pc(target_ulong pc)
> +static inline void gen_save_pc(vaddr pc)
> {
> tcg_gen_movi_tl(cpu_PC, pc);
> }
>
> -static void gen_goto_tb(DisasContext *ctx, unsigned tb_slot_index,
> - target_ulong dest)
> +static void gen_goto_tb(DisasContext *ctx, unsigned tb_slot_index, vaddr dest)
> {
> if (translator_use_goto_tb(&ctx->base, dest)) {
> tcg_gen_goto_tb(tb_slot_index);
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 02/12] target/tricore: Replace target_ulong -> vaddr with tlb_fill() callees
2025-10-10 5:21 ` [PATCH 02/12] target/tricore: Replace target_ulong -> vaddr with tlb_fill() callees Philippe Mathieu-Daudé
@ 2025-10-10 16:56 ` Richard Henderson
0 siblings, 0 replies; 25+ messages in thread
From: Richard Henderson @ 2025-10-10 16:56 UTC (permalink / raw)
To: qemu-devel
On 10/9/25 22:21, Philippe Mathieu-Daudé wrote:
> tlb_fill() provides a vaddr type since commit 68d6eee73c
> ("target/tricore: Convert to CPUClass::tlb_fill").
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> target/tricore/helper.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/tricore/helper.c b/target/tricore/helper.c
> index e4c53d453dd..7574111c87d 100644
> --- a/target/tricore/helper.c
> +++ b/target/tricore/helper.c
> @@ -35,7 +35,7 @@ enum {
> };
>
> static int get_physical_address(CPUTriCoreState *env, hwaddr *physical,
> - int *prot, target_ulong address,
> + int *prot, vaddr address,
> MMUAccessType access_type, int mmu_idx)
> {
> int ret = TLBRET_MATCH;
> @@ -61,7 +61,7 @@ hwaddr tricore_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
> }
>
> /* TODO: Add exception support */
> -static void raise_mmu_exception(CPUTriCoreState *env, target_ulong address,
> +static void raise_mmu_exception(CPUTriCoreState *env, vaddr address,
> int rw, int tlb_error)
> {
> }
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 03/12] target/tricore: Remove target_ulong use in translate_insn() handler
2025-10-10 5:21 ` [PATCH 03/12] target/tricore: Remove target_ulong use in translate_insn() handler Philippe Mathieu-Daudé
@ 2025-10-10 16:57 ` Richard Henderson
0 siblings, 0 replies; 25+ messages in thread
From: Richard Henderson @ 2025-10-10 16:57 UTC (permalink / raw)
To: qemu-devel
On 10/9/25 22:21, Philippe Mathieu-Daudé wrote:
> Since commit 85c19af63e7 ("include/exec: Use vaddr in DisasContextBase
> for virtual addresses") the DisasContextBase::pc_first field is a
> vaddr type.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> target/tricore/translate.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/tricore/translate.c b/target/tricore/translate.c
> index dd09f0651f5..4b769b204ab 100644
> --- a/target/tricore/translate.c
> +++ b/target/tricore/translate.c
> @@ -8414,7 +8414,7 @@ static void tricore_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
> ctx->base.pc_next = ctx->pc_succ_insn;
>
> if (ctx->base.is_jmp == DISAS_NEXT) {
> - target_ulong page_start;
> + vaddr page_start;
>
> page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
> if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 04/12] target/tricore: Remove target_ulong use in gen_addi_d()
2025-10-10 5:21 ` [PATCH 04/12] target/tricore: Remove target_ulong use in gen_addi_d() Philippe Mathieu-Daudé
@ 2025-10-10 16:59 ` Richard Henderson
0 siblings, 0 replies; 25+ messages in thread
From: Richard Henderson @ 2025-10-10 16:59 UTC (permalink / raw)
To: qemu-devel
On 10/9/25 22:21, Philippe Mathieu-Daudé wrote:
> Callers pass either int32_t or int16_t.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> target/tricore/translate.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/tricore/translate.c b/target/tricore/translate.c
> index 4b769b204ab..116f45135bb 100644
> --- a/target/tricore/translate.c
> +++ b/target/tricore/translate.c
> @@ -1308,7 +1308,7 @@ gen_msubui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
> gen_msubu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
> }
>
> -static inline void gen_addi_d(TCGv ret, TCGv r1, target_ulong r2)
> +static inline void gen_addi_d(TCGv ret, TCGv r1, int32_t r2)
> {
> TCGv temp = tcg_constant_i32(r2);
> gen_add_d(ret, r1, temp);
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 05/12] target/tricore: Remove unnecessary cast to target_ulong
2025-10-10 5:21 ` [PATCH 05/12] target/tricore: Remove unnecessary cast to target_ulong Philippe Mathieu-Daudé
@ 2025-10-10 16:59 ` Richard Henderson
0 siblings, 0 replies; 25+ messages in thread
From: Richard Henderson @ 2025-10-10 16:59 UTC (permalink / raw)
To: qemu-devel
On 10/9/25 22:21, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> target/tricore/cpu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
> index 4f035b6f768..04319e107ba 100644
> --- a/target/tricore/cpu.c
> +++ b/target/tricore/cpu.c
> @@ -37,7 +37,7 @@ static const gchar *tricore_gdb_arch_name(CPUState *cs)
>
> static void tricore_cpu_set_pc(CPUState *cs, vaddr value)
> {
> - cpu_env(cs)->PC = value & ~(target_ulong)1;
> + cpu_env(cs)->PC = value & ~1;
> }
>
> static vaddr tricore_cpu_get_pc(CPUState *cs)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 06/12] target/tricore: Replace target_ulong -> uint32_t in op_helper.c
2025-10-10 5:21 ` [PATCH 06/12] target/tricore: Replace target_ulong -> uint32_t in op_helper.c Philippe Mathieu-Daudé
@ 2025-10-10 17:01 ` Richard Henderson
0 siblings, 0 replies; 25+ messages in thread
From: Richard Henderson @ 2025-10-10 17:01 UTC (permalink / raw)
To: qemu-devel
On 10/9/25 22:21, Philippe Mathieu-Daudé wrote:
> The TriCore target is only built as 32-bit:
>
> $ git grep TARGET_LONG_BITS configs/targets/tricore-*
> configs/targets/tricore-softmmu.mak:2:TARGET_LONG_BITS=32
>
> Therefore target_ulong type always expands to uint32_t.
>
> This is a mechanical replacement.
>
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> ---
> target/tricore/op_helper.c | 219 +++++++++++++++++--------------------
> 1 file changed, 103 insertions(+), 116 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 07/12] target/tricore: Declare registers as TCGv_i32
2025-10-10 5:21 ` [PATCH 07/12] target/tricore: Declare registers as TCGv_i32 Philippe Mathieu-Daudé
@ 2025-10-10 17:04 ` Richard Henderson
0 siblings, 0 replies; 25+ messages in thread
From: Richard Henderson @ 2025-10-10 17:04 UTC (permalink / raw)
To: qemu-devel
On 10/9/25 22:21, Philippe Mathieu-Daudé wrote:
> CPUTriCoreState register are declared as uint32_t since the
> target introduction in commit 48e06fe0ed8 ("target-tricore:
> Add target stubs and qom-cpu").
>
> Mechanical replacement of:
>
> TCGv -> TCGv_i32
> tcg_temp_new -> tcg_temp_new_i32
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> target/tricore/translate.c | 80 +++++++++++++++++++-------------------
> 1 file changed, 40 insertions(+), 40 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 08/12] target/tricore: Inline tcg_gen_ld32u_tl()
2025-10-10 5:21 ` [PATCH 08/12] target/tricore: Inline tcg_gen_ld32u_tl() Philippe Mathieu-Daudé
@ 2025-10-10 17:05 ` Richard Henderson
0 siblings, 0 replies; 25+ messages in thread
From: Richard Henderson @ 2025-10-10 17:05 UTC (permalink / raw)
To: qemu-devel
On 10/9/25 22:21, Philippe Mathieu-Daudé wrote:
> The TriCore target is only built as 32-bit, so tcg_gen_ld32u_tl()
> expands to tcg_gen_ld_i32(). Use the latter to simplify the next
> commit mechanical change.
>
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> ---
> target/tricore/translate.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 09/12] target/tricore: Expand TCG helpers for 32-bit target
2025-10-10 5:21 ` [PATCH 09/12] target/tricore: Expand TCG helpers for 32-bit target Philippe Mathieu-Daudé
@ 2025-10-10 17:06 ` Richard Henderson
0 siblings, 0 replies; 25+ messages in thread
From: Richard Henderson @ 2025-10-10 17:06 UTC (permalink / raw)
To: qemu-devel
On 10/9/25 22:21, Philippe Mathieu-Daudé wrote:
> The TriCore target is only built as 32-bit:
>
> $ git grep TARGET_LONG_BITS configs/targets/tricore-*
> configs/targets/tricore-softmmu.mak:2:TARGET_LONG_BITS=32
>
> Therefore tcg_FOO_tl() always expands to tcg_FOO_i32().
>
> This is a mechanical replacement.
>
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> ---
> target/tricore/translate.c | 2595 ++++++++++++++++++------------------
> 1 file changed, 1298 insertions(+), 1297 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 10/12] target/tricore: Pass DisasContext as first argument
2025-10-10 5:21 ` [PATCH 10/12] target/tricore: Pass DisasContext as first argument Philippe Mathieu-Daudé
@ 2025-10-10 17:07 ` Richard Henderson
0 siblings, 0 replies; 25+ messages in thread
From: Richard Henderson @ 2025-10-10 17:07 UTC (permalink / raw)
To: qemu-devel
On 10/9/25 22:21, Philippe Mathieu-Daudé wrote:
> Unify style, always pass DisasContext as the first argument.
>
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> ---
> target/tricore/translate.c | 68 +++++++++++++++++++-------------------
> 1 file changed, 34 insertions(+), 34 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 11/12] target/tricore: Un-inline various helpers
2025-10-10 5:21 ` [PATCH 11/12] target/tricore: Un-inline various helpers Philippe Mathieu-Daudé
@ 2025-10-10 17:07 ` Richard Henderson
0 siblings, 0 replies; 25+ messages in thread
From: Richard Henderson @ 2025-10-10 17:07 UTC (permalink / raw)
To: qemu-devel
On 10/9/25 22:21, Philippe Mathieu-Daudé wrote:
> Rely on the linker to optimize at linking time.
>
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> ---
> target/tricore/translate.c | 274 ++++++++++++++++++-------------------
> 1 file changed, 135 insertions(+), 139 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 12/12] target/tricore: Expand TCGv type for 32-bit target
2025-10-10 5:21 ` [PATCH 12/12] target/tricore: Expand TCGv type for 32-bit target Philippe Mathieu-Daudé
@ 2025-10-10 17:09 ` Richard Henderson
0 siblings, 0 replies; 25+ messages in thread
From: Richard Henderson @ 2025-10-10 17:09 UTC (permalink / raw)
To: qemu-devel
On 10/9/25 22:21, Philippe Mathieu-Daudé wrote:
> The TriCore target is only built as 32-bit:
>
> $ git grep TARGET_LONG_BITS configs/targets/tricore-*
> configs/targets/tricore-softmmu.mak:2:TARGET_LONG_BITS=32
>
> Replace:
>
> TCGv -> TCGv_i32
> tcg_temp_new -> tcg_temp_new_i32
>
> This is a mechanical replacement, adapting style to pass
> the checkpatch.pl script.
>
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> ---
> target/tricore/translate.c | 1248 +++++++++++++++++++-----------------
> 1 file changed, 642 insertions(+), 606 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 25+ messages in thread
end of thread, other threads:[~2025-10-10 17:10 UTC | newest]
Thread overview: 25+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-10-10 5:21 [PATCH 00/12] target/tricore: Remove all uses of target_ulong types Philippe Mathieu-Daudé
2025-10-10 5:21 ` [PATCH 01/12] target/tricore: Remove target_ulong use in gen_goto_tb() Philippe Mathieu-Daudé
2025-10-10 16:56 ` Richard Henderson
2025-10-10 5:21 ` [PATCH 02/12] target/tricore: Replace target_ulong -> vaddr with tlb_fill() callees Philippe Mathieu-Daudé
2025-10-10 16:56 ` Richard Henderson
2025-10-10 5:21 ` [PATCH 03/12] target/tricore: Remove target_ulong use in translate_insn() handler Philippe Mathieu-Daudé
2025-10-10 16:57 ` Richard Henderson
2025-10-10 5:21 ` [PATCH 04/12] target/tricore: Remove target_ulong use in gen_addi_d() Philippe Mathieu-Daudé
2025-10-10 16:59 ` Richard Henderson
2025-10-10 5:21 ` [PATCH 05/12] target/tricore: Remove unnecessary cast to target_ulong Philippe Mathieu-Daudé
2025-10-10 16:59 ` Richard Henderson
2025-10-10 5:21 ` [PATCH 06/12] target/tricore: Replace target_ulong -> uint32_t in op_helper.c Philippe Mathieu-Daudé
2025-10-10 17:01 ` Richard Henderson
2025-10-10 5:21 ` [PATCH 07/12] target/tricore: Declare registers as TCGv_i32 Philippe Mathieu-Daudé
2025-10-10 17:04 ` Richard Henderson
2025-10-10 5:21 ` [PATCH 08/12] target/tricore: Inline tcg_gen_ld32u_tl() Philippe Mathieu-Daudé
2025-10-10 17:05 ` Richard Henderson
2025-10-10 5:21 ` [PATCH 09/12] target/tricore: Expand TCG helpers for 32-bit target Philippe Mathieu-Daudé
2025-10-10 17:06 ` Richard Henderson
2025-10-10 5:21 ` [PATCH 10/12] target/tricore: Pass DisasContext as first argument Philippe Mathieu-Daudé
2025-10-10 17:07 ` Richard Henderson
2025-10-10 5:21 ` [PATCH 11/12] target/tricore: Un-inline various helpers Philippe Mathieu-Daudé
2025-10-10 17:07 ` Richard Henderson
2025-10-10 5:21 ` [PATCH 12/12] target/tricore: Expand TCGv type for 32-bit target Philippe Mathieu-Daudé
2025-10-10 17:09 ` Richard Henderson
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