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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-426ce57cd11sm2327565f8f.5.2025.10.09.22.22.30 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 09 Oct 2025 22:22:31 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bastian Koppelmann , Pierrick Bouvier , Anton Johansson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 10/12] target/tricore: Pass DisasContext as first argument Date: Fri, 10 Oct 2025 07:21:38 +0200 Message-ID: <20251010052141.42460-11-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251010052141.42460-1-philmd@linaro.org> References: <20251010052141.42460-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::441; envelope-from=philmd@linaro.org; helo=mail-wr1-x441.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Unify style, always pass DisasContext as the first argument. Signed-off-by: Philippe Mathieu-Daudé --- target/tricore/translate.c | 68 +++++++++++++++++++------------------- 1 file changed, 34 insertions(+), 34 deletions(-) diff --git a/target/tricore/translate.c b/target/tricore/translate.c index ce4e3f6202e..595db14bb2b 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -226,7 +226,7 @@ static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2, tcg_gen_qemu_st_i32(r1, temp, ctx->mem_idx, mop); } -static void gen_st_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx) +static void gen_st_2regs_64(DisasContext *ctx, TCGv rh, TCGv rl, TCGv address) { TCGv_i64 temp = tcg_temp_new_i64(); @@ -234,15 +234,15 @@ static void gen_st_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx) tcg_gen_qemu_st_i64(temp, address, ctx->mem_idx, MO_LEUQ); } -static void gen_offset_st_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con, - DisasContext *ctx) +static void gen_offset_st_2regs(DisasContext *ctx, + TCGv rh, TCGv rl, TCGv base, int16_t con) { TCGv temp = tcg_temp_new(); tcg_gen_addi_i32(temp, base, con); - gen_st_2regs_64(rh, rl, temp, ctx); + gen_st_2regs_64(ctx, rh, rl, temp); } -static void gen_ld_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx) +static void gen_ld_2regs_64(DisasContext *ctx, TCGv rh, TCGv rl, TCGv address) { TCGv_i64 temp = tcg_temp_new_i64(); @@ -251,12 +251,12 @@ static void gen_ld_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx) tcg_gen_extr_i64_i32(rl, rh, temp); } -static void gen_offset_ld_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con, - DisasContext *ctx) +static void gen_offset_ld_2regs(DisasContext *ctx, + TCGv rh, TCGv rl, TCGv base, int16_t con) { TCGv temp = tcg_temp_new(); tcg_gen_addi_i32(temp, base, con); - gen_ld_2regs_64(rh, rl, temp, ctx); + gen_ld_2regs_64(ctx, rh, rl, temp); } static void gen_st_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off, @@ -3798,11 +3798,11 @@ static void decode_abs_ldw(DisasContext *ctx) break; case OPC2_32_ABS_LD_D: CHECK_REG_PAIR(r1); - gen_ld_2regs_64(cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], temp, ctx); + gen_ld_2regs_64(ctx, cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], temp); break; case OPC2_32_ABS_LD_DA: CHECK_REG_PAIR(r1); - gen_ld_2regs_64(cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], temp, ctx); + gen_ld_2regs_64(ctx, cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], temp); break; case OPC2_32_ABS_LD_W: tcg_gen_qemu_ld_i32(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL); @@ -3913,11 +3913,11 @@ static void decode_abs_store(DisasContext *ctx) break; case OPC2_32_ABS_ST_D: CHECK_REG_PAIR(r1); - gen_st_2regs_64(cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], temp, ctx); + gen_st_2regs_64(ctx, cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], temp); break; case OPC2_32_ABS_ST_DA: CHECK_REG_PAIR(r1); - gen_st_2regs_64(cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], temp, ctx); + gen_st_2regs_64(ctx, cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], temp); break; case OPC2_32_ABS_ST_W: tcg_gen_qemu_st_i32(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL); @@ -4289,36 +4289,36 @@ static void decode_bo_addrmode_post_pre_base(DisasContext *ctx) break; case OPC2_32_BO_ST_D_SHORTOFF: CHECK_REG_PAIR(r1); - gen_offset_st_2regs(cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], cpu_gpr_a[r2], - off10, ctx); + gen_offset_st_2regs(ctx, cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], cpu_gpr_a[r2], + off10); break; case OPC2_32_BO_ST_D_POSTINC: CHECK_REG_PAIR(r1); - gen_st_2regs_64(cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx); + gen_st_2regs_64(ctx, cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], cpu_gpr_a[r2]); tcg_gen_addi_i32(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); break; case OPC2_32_BO_ST_D_PREINC: CHECK_REG_PAIR(r1); temp = tcg_temp_new(); tcg_gen_addi_i32(temp, cpu_gpr_a[r2], off10); - gen_st_2regs_64(cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], temp, ctx); + gen_st_2regs_64(ctx, cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], temp); tcg_gen_mov_i32(cpu_gpr_a[r2], temp); break; case OPC2_32_BO_ST_DA_SHORTOFF: CHECK_REG_PAIR(r1); - gen_offset_st_2regs(cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], cpu_gpr_a[r2], - off10, ctx); + gen_offset_st_2regs(ctx, cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], cpu_gpr_a[r2], + off10); break; case OPC2_32_BO_ST_DA_POSTINC: CHECK_REG_PAIR(r1); - gen_st_2regs_64(cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx); + gen_st_2regs_64(ctx, cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], cpu_gpr_a[r2]); tcg_gen_addi_i32(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); break; case OPC2_32_BO_ST_DA_PREINC: CHECK_REG_PAIR(r1); temp = tcg_temp_new(); tcg_gen_addi_i32(temp, cpu_gpr_a[r2], off10); - gen_st_2regs_64(cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], temp, ctx); + gen_st_2regs_64(ctx, cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], temp); tcg_gen_mov_i32(cpu_gpr_a[r2], temp); break; case OPC2_32_BO_ST_H_SHORTOFF: @@ -4413,7 +4413,7 @@ static void decode_bo_addrmode_bitreverse_circular(DisasContext *ctx) break; case OPC2_32_BO_ST_D_BR: CHECK_REG_PAIR(r1); - gen_st_2regs_64(cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], temp2, ctx); + gen_st_2regs_64(ctx, cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], temp2); gen_helper_br_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1]); break; case OPC2_32_BO_ST_D_CIRC: @@ -4428,7 +4428,7 @@ static void decode_bo_addrmode_bitreverse_circular(DisasContext *ctx) break; case OPC2_32_BO_ST_DA_BR: CHECK_REG_PAIR(r1); - gen_st_2regs_64(cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], temp2, ctx); + gen_st_2regs_64(ctx, cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], temp2); gen_helper_br_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1]); break; case OPC2_32_BO_ST_DA_CIRC: @@ -4520,36 +4520,36 @@ static void decode_bo_addrmode_ld_post_pre_base(DisasContext *ctx) break; case OPC2_32_BO_LD_D_SHORTOFF: CHECK_REG_PAIR(r1); - gen_offset_ld_2regs(cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], cpu_gpr_a[r2], - off10, ctx); + gen_offset_ld_2regs(ctx, cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], cpu_gpr_a[r2], + off10); break; case OPC2_32_BO_LD_D_POSTINC: CHECK_REG_PAIR(r1); - gen_ld_2regs_64(cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx); + gen_ld_2regs_64(ctx, cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], cpu_gpr_a[r2]); tcg_gen_addi_i32(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); break; case OPC2_32_BO_LD_D_PREINC: CHECK_REG_PAIR(r1); temp = tcg_temp_new(); tcg_gen_addi_i32(temp, cpu_gpr_a[r2], off10); - gen_ld_2regs_64(cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], temp, ctx); + gen_ld_2regs_64(ctx, cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], temp); tcg_gen_mov_i32(cpu_gpr_a[r2], temp); break; case OPC2_32_BO_LD_DA_SHORTOFF: CHECK_REG_PAIR(r1); - gen_offset_ld_2regs(cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], cpu_gpr_a[r2], - off10, ctx); + gen_offset_ld_2regs(ctx, cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], cpu_gpr_a[r2], + off10); break; case OPC2_32_BO_LD_DA_POSTINC: CHECK_REG_PAIR(r1); - gen_ld_2regs_64(cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx); + gen_ld_2regs_64(ctx, cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], cpu_gpr_a[r2]); tcg_gen_addi_i32(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); break; case OPC2_32_BO_LD_DA_PREINC: CHECK_REG_PAIR(r1); temp = tcg_temp_new(); tcg_gen_addi_i32(temp, cpu_gpr_a[r2], off10); - gen_ld_2regs_64(cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], temp, ctx); + gen_ld_2regs_64(ctx, cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], temp); tcg_gen_mov_i32(cpu_gpr_a[r2], temp); break; case OPC2_32_BO_LD_H_SHORTOFF: @@ -4651,7 +4651,7 @@ static void decode_bo_addrmode_ld_bitreverse_circular(DisasContext *ctx) break; case OPC2_32_BO_LD_D_BR: CHECK_REG_PAIR(r1); - gen_ld_2regs_64(cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], temp2, ctx); + gen_ld_2regs_64(ctx, cpu_gpr_d[r1 + 1], cpu_gpr_d[r1], temp2); gen_helper_br_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1]); break; case OPC2_32_BO_LD_D_CIRC: @@ -4666,7 +4666,7 @@ static void decode_bo_addrmode_ld_bitreverse_circular(DisasContext *ctx) break; case OPC2_32_BO_LD_DA_BR: CHECK_REG_PAIR(r1); - gen_ld_2regs_64(cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], temp2, ctx); + gen_ld_2regs_64(ctx, cpu_gpr_a[r1 + 1], cpu_gpr_a[r1], temp2); gen_helper_br_update(cpu_gpr_a[r2 + 1], cpu_gpr_a[r2 + 1]); break; case OPC2_32_BO_LD_DA_CIRC: @@ -8377,7 +8377,7 @@ static void tricore_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) tcg_gen_insn_start(ctx->base.pc_next); } -static bool insn_crosses_page(CPUTriCoreState *env, DisasContext *ctx) +static bool insn_crosses_page(DisasContext *ctx, CPUTriCoreState *env) { /* * Return true if the insn at ctx->base.pc_next might cross a page boundary. @@ -8420,7 +8420,7 @@ static void tricore_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) page_start = ctx->base.pc_first & TARGET_PAGE_MASK; if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE || (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE - 3 - && insn_crosses_page(env, ctx))) { + && insn_crosses_page(ctx, env))) { ctx->base.is_jmp = DISAS_TOO_MANY; } } -- 2.51.0