From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Bastian Koppelmann" <kbastian@mail.uni-paderborn.de>,
"Pierrick Bouvier" <pierrick.bouvier@linaro.org>,
"Anton Johansson" <anjo@rev.ng>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PATCH 07/12] target/tricore: Declare registers as TCGv_i32
Date: Fri, 10 Oct 2025 07:21:35 +0200 [thread overview]
Message-ID: <20251010052141.42460-8-philmd@linaro.org> (raw)
In-Reply-To: <20251010052141.42460-1-philmd@linaro.org>
CPUTriCoreState register are declared as uint32_t since the
target introduction in commit 48e06fe0ed8 ("target-tricore:
Add target stubs and qom-cpu").
Mechanical replacement of:
TCGv -> TCGv_i32
tcg_temp_new -> tcg_temp_new_i32
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/tricore/translate.c | 80 +++++++++++++++++++-------------------
1 file changed, 40 insertions(+), 40 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 116f45135bb..194c4db8d0f 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -44,19 +44,19 @@
/*
* TCG registers
*/
-static TCGv cpu_PC;
-static TCGv cpu_PCXI;
-static TCGv cpu_PSW;
-static TCGv cpu_ICR;
+static TCGv_i32 cpu_PC;
+static TCGv_i32 cpu_PCXI;
+static TCGv_i32 cpu_PSW;
+static TCGv_i32 cpu_ICR;
/* GPR registers */
-static TCGv cpu_gpr_a[16];
-static TCGv cpu_gpr_d[16];
+static TCGv_i32 cpu_gpr_a[16];
+static TCGv_i32 cpu_gpr_d[16];
/* PSW Flag cache */
-static TCGv cpu_PSW_C;
-static TCGv cpu_PSW_V;
-static TCGv cpu_PSW_SV;
-static TCGv cpu_PSW_AV;
-static TCGv cpu_PSW_SAV;
+static TCGv_i32 cpu_PSW_C;
+static TCGv_i32 cpu_PSW_V;
+static TCGv_i32 cpu_PSW_SV;
+static TCGv_i32 cpu_PSW_AV;
+static TCGv_i32 cpu_PSW_SAV;
static const char *regnames_a[] = {
"a0" , "a1" , "a2" , "a3" , "a4" , "a5" ,
@@ -8480,14 +8480,14 @@ void cpu_state_reset(CPUTriCoreState *env)
static void tricore_tcg_init_csfr(void)
{
- cpu_PCXI = tcg_global_mem_new(tcg_env,
- offsetof(CPUTriCoreState, PCXI), "PCXI");
- cpu_PSW = tcg_global_mem_new(tcg_env,
- offsetof(CPUTriCoreState, PSW), "PSW");
- cpu_PC = tcg_global_mem_new(tcg_env,
- offsetof(CPUTriCoreState, PC), "PC");
- cpu_ICR = tcg_global_mem_new(tcg_env,
- offsetof(CPUTriCoreState, ICR), "ICR");
+ cpu_PCXI = tcg_global_mem_new_i32(tcg_env,
+ offsetof(CPUTriCoreState, PCXI), "PCXI");
+ cpu_PSW = tcg_global_mem_new_i32(tcg_env,
+ offsetof(CPUTriCoreState, PSW), "PSW");
+ cpu_PC = tcg_global_mem_new_i32(tcg_env,
+ offsetof(CPUTriCoreState, PC), "PC");
+ cpu_ICR = tcg_global_mem_new_i32(tcg_env,
+ offsetof(CPUTriCoreState, ICR), "ICR");
}
void tricore_tcg_init(void)
@@ -8496,30 +8496,30 @@ void tricore_tcg_init(void)
/* reg init */
for (i = 0 ; i < 16 ; i++) {
- cpu_gpr_a[i] = tcg_global_mem_new(tcg_env,
- offsetof(CPUTriCoreState, gpr_a[i]),
- regnames_a[i]);
+ cpu_gpr_a[i] = tcg_global_mem_new_i32(tcg_env,
+ offsetof(CPUTriCoreState, gpr_a[i]),
+ regnames_a[i]);
}
for (i = 0 ; i < 16 ; i++) {
- cpu_gpr_d[i] = tcg_global_mem_new(tcg_env,
- offsetof(CPUTriCoreState, gpr_d[i]),
- regnames_d[i]);
+ cpu_gpr_d[i] = tcg_global_mem_new_i32(tcg_env,
+ offsetof(CPUTriCoreState, gpr_d[i]),
+ regnames_d[i]);
}
tricore_tcg_init_csfr();
/* init PSW flag cache */
- cpu_PSW_C = tcg_global_mem_new(tcg_env,
- offsetof(CPUTriCoreState, PSW_USB_C),
- "PSW_C");
- cpu_PSW_V = tcg_global_mem_new(tcg_env,
- offsetof(CPUTriCoreState, PSW_USB_V),
- "PSW_V");
- cpu_PSW_SV = tcg_global_mem_new(tcg_env,
- offsetof(CPUTriCoreState, PSW_USB_SV),
- "PSW_SV");
- cpu_PSW_AV = tcg_global_mem_new(tcg_env,
- offsetof(CPUTriCoreState, PSW_USB_AV),
- "PSW_AV");
- cpu_PSW_SAV = tcg_global_mem_new(tcg_env,
- offsetof(CPUTriCoreState, PSW_USB_SAV),
- "PSW_SAV");
+ cpu_PSW_C = tcg_global_mem_new_i32(tcg_env,
+ offsetof(CPUTriCoreState, PSW_USB_C),
+ "PSW_C");
+ cpu_PSW_V = tcg_global_mem_new_i32(tcg_env,
+ offsetof(CPUTriCoreState, PSW_USB_V),
+ "PSW_V");
+ cpu_PSW_SV = tcg_global_mem_new_i32(tcg_env,
+ offsetof(CPUTriCoreState, PSW_USB_SV),
+ "PSW_SV");
+ cpu_PSW_AV = tcg_global_mem_new_i32(tcg_env,
+ offsetof(CPUTriCoreState, PSW_USB_AV),
+ "PSW_AV");
+ cpu_PSW_SAV = tcg_global_mem_new_i32(tcg_env,
+ offsetof(CPUTriCoreState, PSW_USB_SAV),
+ "PSW_SAV");
}
--
2.51.0
next prev parent reply other threads:[~2025-10-10 5:24 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-10 5:21 [PATCH 00/12] target/tricore: Remove all uses of target_ulong types Philippe Mathieu-Daudé
2025-10-10 5:21 ` [PATCH 01/12] target/tricore: Remove target_ulong use in gen_goto_tb() Philippe Mathieu-Daudé
2025-10-10 16:56 ` Richard Henderson
2025-10-10 5:21 ` [PATCH 02/12] target/tricore: Replace target_ulong -> vaddr with tlb_fill() callees Philippe Mathieu-Daudé
2025-10-10 16:56 ` Richard Henderson
2025-10-10 5:21 ` [PATCH 03/12] target/tricore: Remove target_ulong use in translate_insn() handler Philippe Mathieu-Daudé
2025-10-10 16:57 ` Richard Henderson
2025-10-10 5:21 ` [PATCH 04/12] target/tricore: Remove target_ulong use in gen_addi_d() Philippe Mathieu-Daudé
2025-10-10 16:59 ` Richard Henderson
2025-10-10 5:21 ` [PATCH 05/12] target/tricore: Remove unnecessary cast to target_ulong Philippe Mathieu-Daudé
2025-10-10 16:59 ` Richard Henderson
2025-10-10 5:21 ` [PATCH 06/12] target/tricore: Replace target_ulong -> uint32_t in op_helper.c Philippe Mathieu-Daudé
2025-10-10 17:01 ` Richard Henderson
2025-10-10 5:21 ` Philippe Mathieu-Daudé [this message]
2025-10-10 17:04 ` [PATCH 07/12] target/tricore: Declare registers as TCGv_i32 Richard Henderson
2025-10-10 5:21 ` [PATCH 08/12] target/tricore: Inline tcg_gen_ld32u_tl() Philippe Mathieu-Daudé
2025-10-10 17:05 ` Richard Henderson
2025-10-10 5:21 ` [PATCH 09/12] target/tricore: Expand TCG helpers for 32-bit target Philippe Mathieu-Daudé
2025-10-10 17:06 ` Richard Henderson
2025-10-10 5:21 ` [PATCH 10/12] target/tricore: Pass DisasContext as first argument Philippe Mathieu-Daudé
2025-10-10 17:07 ` Richard Henderson
2025-10-10 5:21 ` [PATCH 11/12] target/tricore: Un-inline various helpers Philippe Mathieu-Daudé
2025-10-10 17:07 ` Richard Henderson
2025-10-10 5:21 ` [PATCH 12/12] target/tricore: Expand TCGv type for 32-bit target Philippe Mathieu-Daudé
2025-10-10 17:09 ` Richard Henderson
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