From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Richard Henderson" <richard.henderson@linaro.org>,
"Stafford Horne" <shorne@gmail.com>,
"Anton Johansson" <anjo@rev.ng>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PATCH v3 05/13] target/openrisc: Use vaddr type for $pc jumps
Date: Fri, 10 Oct 2025 09:06:53 +0200 [thread overview]
Message-ID: <20251010070702.51484-6-philmd@linaro.org> (raw)
In-Reply-To: <20251010070702.51484-1-philmd@linaro.org>
translator_use_goto_tb() expects a vaddr type since commit
b1c09220b4c ("accel/tcg: Replace target_ulong with vaddr in
translator_*()").
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/openrisc/translate.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 5ab3bc7021d..9f61f917b3b 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -51,7 +51,7 @@ typedef struct DisasContext {
uint32_t avr;
/* If not -1, jmp_pc contains this value and so is a direct jump. */
- target_ulong jmp_pc_imm;
+ vaddr jmp_pc_imm;
/* The temporary corresponding to register 0 for this compilation. */
TCGv R0;
@@ -580,7 +580,7 @@ static bool trans_l_muldu(DisasContext *dc, arg_ab *a)
static bool trans_l_j(DisasContext *dc, arg_l_j *a)
{
- target_ulong tmp_pc = dc->base.pc_next + a->n * 4;
+ vaddr tmp_pc = dc->base.pc_next + a->n * 4;
tcg_gen_movi_tl(jmp_pc, tmp_pc);
dc->jmp_pc_imm = tmp_pc;
@@ -590,8 +590,8 @@ static bool trans_l_j(DisasContext *dc, arg_l_j *a)
static bool trans_l_jal(DisasContext *dc, arg_l_jal *a)
{
- target_ulong tmp_pc = dc->base.pc_next + a->n * 4;
- target_ulong ret_pc = dc->base.pc_next + 8;
+ vaddr tmp_pc = dc->base.pc_next + a->n * 4;
+ vaddr ret_pc = dc->base.pc_next + 8;
tcg_gen_movi_tl(cpu_regs[9], ret_pc);
/* Optimize jal being used to load the PC for PIC. */
@@ -605,7 +605,7 @@ static bool trans_l_jal(DisasContext *dc, arg_l_jal *a)
static void do_bf(DisasContext *dc, arg_l_bf *a, TCGCond cond)
{
- target_ulong tmp_pc = dc->base.pc_next + a->n * 4;
+ vaddr tmp_pc = dc->base.pc_next + a->n * 4;
TCGv t_next = tcg_constant_tl(dc->base.pc_next + 8);
TCGv t_true = tcg_constant_tl(tmp_pc);
@@ -1586,7 +1586,7 @@ static void openrisc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
static void openrisc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- target_ulong jmp_dest;
+ vaddr jmp_dest;
/* If we have already exited the TB, nothing following has effect. */
if (dc->base.is_jmp == DISAS_NORETURN) {
--
2.51.0
next prev parent reply other threads:[~2025-10-10 7:09 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-10 7:06 [PATCH v3 00/13] target/openrisc: Remove all uses of target_[u]long types Philippe Mathieu-Daudé
2025-10-10 7:06 ` [PATCH v3 01/13] target/openrisc: Replace VMSTATE_UINTTL() -> VMSTATE_UINT32() Philippe Mathieu-Daudé
2025-10-10 7:06 ` [PATCH v3 02/13] target/openrisc: Do not use target_ulong for @mr in MTSPR helper Philippe Mathieu-Daudé
2025-10-10 7:06 ` [PATCH v3 03/13] target/openrisc: Remove unused cpu_openrisc_map_address_*() handlers Philippe Mathieu-Daudé
2025-10-10 7:06 ` [PATCH v3 04/13] target/openrisc: Remove target_ulong use in raise_mmu_exception() Philippe Mathieu-Daudé
2025-10-10 7:06 ` Philippe Mathieu-Daudé [this message]
2025-10-10 7:06 ` [PATCH v3 06/13] target/openrisc: Remove 'TARGET_LONG_BITS != 32' dead code Philippe Mathieu-Daudé
2025-10-10 7:06 ` [PATCH v3 07/13] target/openrisc: Explode MO_TExx -> MO_TE | MO_xx Philippe Mathieu-Daudé
2025-10-10 18:55 ` Richard Henderson
2025-10-10 7:06 ` [PATCH v3 08/13] target/openrisc: Conceal MO_TE within do_load() Philippe Mathieu-Daudé
2025-10-10 18:56 ` Richard Henderson
2025-10-10 7:06 ` [PATCH v3 09/13] target/openrisc: Conceal MO_TE within do_store() Philippe Mathieu-Daudé
2025-10-10 18:56 ` Richard Henderson
2025-10-10 7:06 ` [PATCH v3 10/13] target/openrisc: Introduce mo_endian() helper Philippe Mathieu-Daudé
2025-10-10 18:56 ` Richard Henderson
2025-10-10 7:06 ` [PATCH v3 11/13] target/openrisc: Replace MO_TE -> MO_BE Philippe Mathieu-Daudé
2025-10-10 19:00 ` Richard Henderson
2025-10-10 7:07 ` [PATCH v3 12/13] target/openrisc: Inline tcg_gen_trunc_i64_tl() Philippe Mathieu-Daudé
2025-10-10 7:07 ` [PATCH v3 13/13] target/openrisc: Replace target_ulong -> uint32_t Philippe Mathieu-Daudé
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20251010070702.51484-6-philmd@linaro.org \
--to=philmd@linaro.org \
--cc=anjo@rev.ng \
--cc=qemu-devel@nongnu.org \
--cc=richard.henderson@linaro.org \
--cc=shorne@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).