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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-46fb489197dsm56759745e9.10.2025.10.10.08.51.41 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 10 Oct 2025 08:51:41 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Christoph Muellner , Heinrich Schuchardt , Palmer Dabbelt , Alistair Francis , Liu Zhiwei , Anton Johansson , Richard Henderson , Valentin Haudiquet , Weiwei Li , qemu-riscv@nongnu.org, Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 11/13] target/riscv: Factor MemOp variable out when MO_TE is set Date: Fri, 10 Oct 2025 17:50:42 +0200 Message-ID: <20251010155045.78220-12-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251010155045.78220-1-philmd@linaro.org> References: <20251010155045.78220-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In preparation of automatically replacing the MO_TE flag in the next commit, use an local @memop variable. Signed-off-by: Philippe Mathieu-Daudé --- target/riscv/insn_trans/trans_rvd.c.inc | 6 ++++-- target/riscv/insn_trans/trans_rvf.c.inc | 6 ++++-- target/riscv/insn_trans/trans_rvzacas.c.inc | 5 +++-- target/riscv/insn_trans/trans_rvzce.c.inc | 6 ++++-- target/riscv/insn_trans/trans_rvzfh.c.inc | 8 ++++++-- target/riscv/insn_trans/trans_rvzicfiss.c.inc | 10 ++++++---- 6 files changed, 27 insertions(+), 14 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc index 33858206788..62b75358158 100644 --- a/target/riscv/insn_trans/trans_rvd.c.inc +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -42,7 +42,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) { TCGv addr; - MemOp memop = MO_TE | MO_UQ; + MemOp memop = MO_UQ; REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); @@ -60,6 +60,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) } else { memop |= MO_ATOM_IFALIGN; } + memop |= MO_TE; decode_save_opc(ctx, 0); addr = get_address(ctx, a->rs1, a->imm); @@ -72,7 +73,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) static bool trans_fsd(DisasContext *ctx, arg_fsd *a) { TCGv addr; - MemOp memop = MO_TE | MO_UQ; + MemOp memop = MO_UQ; REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); @@ -84,6 +85,7 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a) } else { memop |= MO_ATOM_IFALIGN; } + memop |= MO_TE; decode_save_opc(ctx, 0); addr = get_address(ctx, a->rs1, a->imm); diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc index 150e2b9a7d4..878417eae92 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -43,11 +43,12 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) { TCGv_i64 dest; TCGv addr; - MemOp memop = MO_TE | MO_UL; + MemOp memop = MO_UL; REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); + memop |= MO_TE; if (ctx->cfg_ptr->ext_zama16b) { memop |= MO_ATOM_WITHIN16; } @@ -65,11 +66,12 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) static bool trans_fsw(DisasContext *ctx, arg_fsw *a) { TCGv addr; - MemOp memop = MO_TE | MO_UL; + MemOp memop = MO_UL; REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); + memop |= MO_TE; if (ctx->cfg_ptr->ext_zama16b) { memop |= MO_ATOM_WITHIN16; } diff --git a/target/riscv/insn_trans/trans_rvzacas.c.inc b/target/riscv/insn_trans/trans_rvzacas.c.inc index d850b142642..6458ac4f241 100644 --- a/target/riscv/insn_trans/trans_rvzacas.c.inc +++ b/target/riscv/insn_trans/trans_rvzacas.c.inc @@ -119,12 +119,13 @@ static bool trans_amocas_q(DisasContext *ctx, arg_amocas_q *a) TCGv_i64 src2h = get_gpr(ctx, a->rs2 == 0 ? 0 : a->rs2 + 1, EXT_NONE); TCGv_i64 destl = get_gpr(ctx, a->rd, EXT_NONE); TCGv_i64 desth = get_gpr(ctx, a->rd == 0 ? 0 : a->rd + 1, EXT_NONE); + MemOp memop = MO_ALIGN | MO_UO; + memop |= MO_TE; tcg_gen_concat_i64_i128(src2, src2l, src2h); tcg_gen_concat_i64_i128(dest, destl, desth); decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO); - tcg_gen_atomic_cmpxchg_i128(dest, src1, dest, src2, ctx->mem_idx, - (MO_ALIGN | MO_TE | MO_UO)); + tcg_gen_atomic_cmpxchg_i128(dest, src1, dest, src2, ctx->mem_idx, memop); tcg_gen_extr_i128_i64(destl, desth, dest); diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/insn_trans/trans_rvzce.c.inc index c8dc102c8e3..172c2c19c17 100644 --- a/target/riscv/insn_trans/trans_rvzce.c.inc +++ b/target/riscv/insn_trans/trans_rvzce.c.inc @@ -175,7 +175,7 @@ static bool gen_pop(DisasContext *ctx, arg_cmpp *a, bool ret, bool ret_val) return false; } - MemOp memop = get_ol(ctx) == MXL_RV32 ? MO_TE | MO_UL : MO_TE | MO_UQ; + MemOp memop = get_ol(ctx) == MXL_RV32 ? MO_UL : MO_UQ; int reg_size = memop_size(memop); target_ulong stack_adj = ROUND_UP(ctpop32(reg_bitmap) * reg_size, 16) + a->spimm; @@ -185,6 +185,7 @@ static bool gen_pop(DisasContext *ctx, arg_cmpp *a, bool ret, bool ret_val) tcg_gen_addi_tl(addr, sp, stack_adj - reg_size); + memop |= MO_TE; for (i = X_Sn + 11; i >= 0; i--) { if (reg_bitmap & (1 << i)) { TCGv dest = dest_gpr(ctx, i); @@ -228,7 +229,7 @@ static bool trans_cm_push(DisasContext *ctx, arg_cm_push *a) return false; } - MemOp memop = get_ol(ctx) == MXL_RV32 ? MO_TE | MO_UL : MO_TE | MO_UQ; + MemOp memop = get_ol(ctx) == MXL_RV32 ? MO_UL : MO_UQ; int reg_size = memop_size(memop); target_ulong stack_adj = ROUND_UP(ctpop32(reg_bitmap) * reg_size, 16) + a->spimm; @@ -238,6 +239,7 @@ static bool trans_cm_push(DisasContext *ctx, arg_cm_push *a) tcg_gen_subi_tl(addr, sp, reg_size); + memop |= MO_TE; for (i = X_Sn + 11; i >= 0; i--) { if (reg_bitmap & (1 << i)) { TCGv val = get_gpr(ctx, i, EXT_NONE); diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_trans/trans_rvzfh.c.inc index eec478afcb0..5355cd46c3d 100644 --- a/target/riscv/insn_trans/trans_rvzfh.c.inc +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc @@ -42,12 +42,14 @@ static bool trans_flh(DisasContext *ctx, arg_flh *a) { + MemOp memop = MO_UW; TCGv_i64 dest; TCGv t0; REQUIRE_FPU; REQUIRE_ZFHMIN_OR_ZFBFMIN(ctx); + memop |= MO_TE; decode_save_opc(ctx, 0); t0 = get_gpr(ctx, a->rs1, EXT_NONE); if (a->imm) { @@ -57,7 +59,7 @@ static bool trans_flh(DisasContext *ctx, arg_flh *a) } dest = cpu_fpr[a->rd]; - tcg_gen_qemu_ld_i64(dest, t0, ctx->mem_idx, MO_TE | MO_UW); + tcg_gen_qemu_ld_i64(dest, t0, ctx->mem_idx, memop); gen_nanbox_h(dest, dest); mark_fs_dirty(ctx); @@ -66,11 +68,13 @@ static bool trans_flh(DisasContext *ctx, arg_flh *a) static bool trans_fsh(DisasContext *ctx, arg_fsh *a) { + MemOp memop = MO_UW; TCGv t0; REQUIRE_FPU; REQUIRE_ZFHMIN_OR_ZFBFMIN(ctx); + memop |= MO_TE; decode_save_opc(ctx, 0); t0 = get_gpr(ctx, a->rs1, EXT_NONE); if (a->imm) { @@ -79,7 +83,7 @@ static bool trans_fsh(DisasContext *ctx, arg_fsh *a) t0 = temp; } - tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TE | MO_UW); + tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, memop); return true; } diff --git a/target/riscv/insn_trans/trans_rvzicfiss.c.inc b/target/riscv/insn_trans/trans_rvzicfiss.c.inc index c5555966175..89eed007587 100644 --- a/target/riscv/insn_trans/trans_rvzicfiss.c.inc +++ b/target/riscv/insn_trans/trans_rvzicfiss.c.inc @@ -100,12 +100,13 @@ static bool trans_ssamoswap_w(DisasContext *ctx, arg_amoswap_w *a) TCGv dest = dest_gpr(ctx, a->rd); TCGv src1, src2 = get_gpr(ctx, a->rs2, EXT_NONE); + MemOp memop = MO_ALIGN | MO_SL; decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO); src1 = get_address(ctx, a->rs1, 0); - tcg_gen_atomic_xchg_tl(dest, src1, src2, SS_MMU_INDEX(ctx), - (MO_ALIGN | MO_TE | MO_SL)); + memop |= MO_TE; + tcg_gen_atomic_xchg_tl(dest, src1, src2, SS_MMU_INDEX(ctx), memop); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -129,12 +130,13 @@ static bool trans_ssamoswap_d(DisasContext *ctx, arg_amoswap_w *a) TCGv dest = dest_gpr(ctx, a->rd); TCGv src1, src2 = get_gpr(ctx, a->rs2, EXT_NONE); + MemOp memop = MO_ALIGN | MO_SQ; decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO); src1 = get_address(ctx, a->rs1, 0); - tcg_gen_atomic_xchg_tl(dest, src1, src2, SS_MMU_INDEX(ctx), - (MO_ALIGN | MO_TE | MO_SQ)); + memop |= MO_TE; + tcg_gen_atomic_xchg_tl(dest, src1, src2, SS_MMU_INDEX(ctx), memop); gen_set_gpr(ctx, a->rd, dest); return true; } -- 2.51.0