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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-46fb55ac08dsm45452255e9.13.2025.10.10.08.50.51 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 10 Oct 2025 08:50:51 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Christoph Muellner , Heinrich Schuchardt , Palmer Dabbelt , Alistair Francis , Liu Zhiwei , Anton Johansson , Richard Henderson , Valentin Haudiquet , Weiwei Li , qemu-riscv@nongnu.org, Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Fabien Portas , =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= Subject: [PATCH 01/13] target/riscv: Really use little endianness for 128-bit loads/stores Date: Fri, 10 Oct 2025 17:50:32 +0200 Message-ID: <20251010155045.78220-2-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251010155045.78220-1-philmd@linaro.org> References: <20251010155045.78220-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philmd@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Per commit a2f827ff4f4 ("target/riscv: accessors to registers upper part and 128-bit load/store") description: > The 128-bit ISA adds ldu, lq and sq. We provide support for these > instructions. Note that (a) we compute only 64-bit addresses to > actually access memory, cowardly utilizing the existing address > translation mechanism of QEMU, and (b) we assume for now > little-endian memory accesses. ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ However this commit used MO_TE (target endianness) for the gen_load_i128() and gen_store_i128() helpers. Likely it was unnoticed because current targets are only built using little endianness: $ git grep -L TARGET_BIG_ENDIAN=y configs/targets/riscv* configs/targets/riscv32-linux-user.mak configs/targets/riscv32-softmmu.mak configs/targets/riscv64-bsd-user.mak configs/targets/riscv64-linux-user.mak configs/targets/riscv64-softmmu.mak Replace by MO_TE -> MO_LE to really use little endianness. Cc: Fabien Portas Cc: Frédéric Pétrot Fixes: a2f827ff4f4 ("target/riscv: accessors to registers upper part and 128-bit load/store") Signed-off-by: Philippe Mathieu-Daudé --- target/riscv/insn_trans/trans_rvi.c.inc | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index b9c71604687..df0b555176a 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -389,9 +389,11 @@ static bool gen_load_i128(DisasContext *ctx, arg_lb *a, MemOp memop) } } else { /* assume little-endian memory access for now */ - tcg_gen_qemu_ld_tl(destl, addrl, ctx->mem_idx, MO_TEUQ); + MemOp memop = MO_LEUQ; + + tcg_gen_qemu_ld_tl(destl, addrl, ctx->mem_idx, memop); tcg_gen_addi_tl(addrl, addrl, 8); - tcg_gen_qemu_ld_tl(desth, addrl, ctx->mem_idx, MO_TEUQ); + tcg_gen_qemu_ld_tl(desth, addrl, ctx->mem_idx, memop); } gen_set_gpr128(ctx, a->rd, destl, desth); @@ -494,9 +496,11 @@ static bool gen_store_i128(DisasContext *ctx, arg_sb *a, MemOp memop) tcg_gen_qemu_st_tl(src2l, addrl, ctx->mem_idx, memop); } else { /* little-endian memory access assumed for now */ - tcg_gen_qemu_st_tl(src2l, addrl, ctx->mem_idx, MO_TEUQ); + MemOp memop = MO_LEUQ; + + tcg_gen_qemu_st_tl(src2l, addrl, ctx->mem_idx, memop); tcg_gen_addi_tl(addrl, addrl, 8); - tcg_gen_qemu_st_tl(src2h, addrl, ctx->mem_idx, MO_TEUQ); + tcg_gen_qemu_st_tl(src2h, addrl, ctx->mem_idx, memop); } return true; } -- 2.51.0