From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Christoph Muellner" <christoph.muellner@vrull.eu>,
"Heinrich Schuchardt" <heinrich.schuchardt@canonical.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Alistair Francis" <alistair.francis@wdc.com>,
"Liu Zhiwei" <zhiwei_liu@linux.alibaba.com>,
"Anton Johansson" <anjo@rev.ng>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Valentin Haudiquet" <valentin.haudiquet@canonical.com>,
"Weiwei Li" <liwei1518@gmail.com>,
qemu-riscv@nongnu.org,
"Daniel Henrique Barboza" <dbarboza@ventanamicro.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PATCH 03/13] target/riscv: Conceal MO_TE within gen_amo()
Date: Fri, 10 Oct 2025 17:50:34 +0200 [thread overview]
Message-ID: <20251010155045.78220-4-philmd@linaro.org> (raw)
In-Reply-To: <20251010155045.78220-1-philmd@linaro.org>
All callers of gen_amo() set the MO_TE flag. Set it once in
the callee.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/riscv/translate.c | 1 +
target/riscv/insn_trans/trans_rva.c.inc | 36 ++++++++++-----------
target/riscv/insn_trans/trans_rvzabha.c.inc | 18 +++++------
3 files changed, 28 insertions(+), 27 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 9a53aecbfe9..94af9853cfe 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1135,6 +1135,7 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a,
TCGv src1, src2 = get_gpr(ctx, a->rs2, EXT_NONE);
MemOp size = mop & MO_SIZE;
+ mop |= MO_TE;
if (ctx->cfg_ptr->ext_zama16b && size >= MO_32) {
mop |= MO_ATOM_WITHIN16;
} else {
diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc
index 10e4c55efda..e0fbfafdde4 100644
--- a/target/riscv/insn_trans/trans_rva.c.inc
+++ b/target/riscv/insn_trans/trans_rva.c.inc
@@ -111,55 +111,55 @@ static bool trans_sc_w(DisasContext *ctx, arg_sc_w *a)
static bool trans_amoswap_w(DisasContext *ctx, arg_amoswap_w *a)
{
REQUIRE_A_OR_ZAAMO(ctx);
- return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, MO_TE | MO_SL);
+ return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, MO_SL);
}
static bool trans_amoadd_w(DisasContext *ctx, arg_amoadd_w *a)
{
REQUIRE_A_OR_ZAAMO(ctx);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, MO_TE | MO_SL);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, MO_SL);
}
static bool trans_amoxor_w(DisasContext *ctx, arg_amoxor_w *a)
{
REQUIRE_A_OR_ZAAMO(ctx);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, MO_TE | MO_SL);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, MO_SL);
}
static bool trans_amoand_w(DisasContext *ctx, arg_amoand_w *a)
{
REQUIRE_A_OR_ZAAMO(ctx);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, MO_TE | MO_SL);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, MO_SL);
}
static bool trans_amoor_w(DisasContext *ctx, arg_amoor_w *a)
{
REQUIRE_A_OR_ZAAMO(ctx);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, MO_TE | MO_SL);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, MO_SL);
}
static bool trans_amomin_w(DisasContext *ctx, arg_amomin_w *a)
{
REQUIRE_A_OR_ZAAMO(ctx);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, MO_TE | MO_SL);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, MO_SL);
}
static bool trans_amomax_w(DisasContext *ctx, arg_amomax_w *a)
{
REQUIRE_A_OR_ZAAMO(ctx);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, MO_TE | MO_SL);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, MO_SL);
}
static bool trans_amominu_w(DisasContext *ctx, arg_amominu_w *a)
{
REQUIRE_A_OR_ZAAMO(ctx);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, MO_TE | MO_SL);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, MO_SL);
}
static bool trans_amomaxu_w(DisasContext *ctx, arg_amomaxu_w *a)
{
REQUIRE_A_OR_ZAAMO(ctx);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, MO_TE | MO_SL);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, MO_SL);
}
static bool trans_lr_d(DisasContext *ctx, arg_lr_d *a)
@@ -180,61 +180,61 @@ static bool trans_amoswap_d(DisasContext *ctx, arg_amoswap_d *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_A_OR_ZAAMO(ctx);
- return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, MO_TE | MO_UQ);
+ return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, MO_UQ);
}
static bool trans_amoadd_d(DisasContext *ctx, arg_amoadd_d *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_A_OR_ZAAMO(ctx);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, MO_TE | MO_UQ);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, MO_UQ);
}
static bool trans_amoxor_d(DisasContext *ctx, arg_amoxor_d *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_A_OR_ZAAMO(ctx);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, MO_TE | MO_UQ);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, MO_UQ);
}
static bool trans_amoand_d(DisasContext *ctx, arg_amoand_d *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_A_OR_ZAAMO(ctx);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, MO_TE | MO_UQ);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, MO_UQ);
}
static bool trans_amoor_d(DisasContext *ctx, arg_amoor_d *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_A_OR_ZAAMO(ctx);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, MO_TE | MO_UQ);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, MO_UQ);
}
static bool trans_amomin_d(DisasContext *ctx, arg_amomin_d *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_A_OR_ZAAMO(ctx);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, MO_TE | MO_UQ);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, MO_UQ);
}
static bool trans_amomax_d(DisasContext *ctx, arg_amomax_d *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_A_OR_ZAAMO(ctx);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, MO_TE | MO_UQ);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, MO_UQ);
}
static bool trans_amominu_d(DisasContext *ctx, arg_amominu_d *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_A_OR_ZAAMO(ctx);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, MO_TE | MO_UQ);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, MO_UQ);
}
static bool trans_amomaxu_d(DisasContext *ctx, arg_amomaxu_d *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_A_OR_ZAAMO(ctx);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, MO_TE | MO_UQ);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, MO_UQ);
}
diff --git a/target/riscv/insn_trans/trans_rvzabha.c.inc b/target/riscv/insn_trans/trans_rvzabha.c.inc
index 25db42d24cd..c1f99b65f09 100644
--- a/target/riscv/insn_trans/trans_rvzabha.c.inc
+++ b/target/riscv/insn_trans/trans_rvzabha.c.inc
@@ -79,55 +79,55 @@ static bool trans_amomaxu_b(DisasContext *ctx, arg_amomaxu_b *a)
static bool trans_amoswap_h(DisasContext *ctx, arg_amoswap_h *a)
{
REQUIRE_ZABHA(ctx);
- return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, MO_TE | MO_SW);
+ return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, MO_SW);
}
static bool trans_amoadd_h(DisasContext *ctx, arg_amoadd_h *a)
{
REQUIRE_ZABHA(ctx);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, MO_TE | MO_SW);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, MO_SW);
}
static bool trans_amoxor_h(DisasContext *ctx, arg_amoxor_h *a)
{
REQUIRE_ZABHA(ctx);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, MO_TE | MO_SW);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, MO_SW);
}
static bool trans_amoand_h(DisasContext *ctx, arg_amoand_h *a)
{
REQUIRE_ZABHA(ctx);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, MO_TE | MO_SW);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, MO_SW);
}
static bool trans_amoor_h(DisasContext *ctx, arg_amoor_h *a)
{
REQUIRE_ZABHA(ctx);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, MO_TE | MO_SW);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, MO_SW);
}
static bool trans_amomin_h(DisasContext *ctx, arg_amomin_h *a)
{
REQUIRE_ZABHA(ctx);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, MO_TE | MO_SW);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, MO_SW);
}
static bool trans_amomax_h(DisasContext *ctx, arg_amomax_h *a)
{
REQUIRE_ZABHA(ctx);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, MO_TE | MO_SW);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, MO_SW);
}
static bool trans_amominu_h(DisasContext *ctx, arg_amominu_h *a)
{
REQUIRE_ZABHA(ctx);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, MO_TE | MO_SW);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, MO_SW);
}
static bool trans_amomaxu_h(DisasContext *ctx, arg_amomaxu_h *a)
{
REQUIRE_ZABHA(ctx);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, MO_TE | MO_SW);
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, MO_SW);
}
static bool trans_amocas_b(DisasContext *ctx, arg_amocas_b *a)
--
2.51.0
next prev parent reply other threads:[~2025-10-10 15:52 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-10 15:50 [PATCH 00/13] target/riscv: Centralize MO_TE uses in a pair of helpers Philippe Mathieu-Daudé
2025-10-10 15:50 ` [PATCH 01/13] target/riscv: Really use little endianness for 128-bit loads/stores Philippe Mathieu-Daudé
2025-10-10 18:44 ` Richard Henderson
2025-10-10 15:50 ` [PATCH 02/13] target/riscv: Explode MO_TExx -> MO_TE | MO_xx Philippe Mathieu-Daudé
2025-10-10 18:45 ` Richard Henderson
2025-10-14 4:59 ` Alistair Francis
2025-10-10 15:50 ` Philippe Mathieu-Daudé [this message]
2025-10-10 18:46 ` [PATCH 03/13] target/riscv: Conceal MO_TE within gen_amo() Richard Henderson
2025-10-14 5:00 ` Alistair Francis
2025-10-10 15:50 ` [PATCH 04/13] target/riscv: Conceal MO_TE within gen_inc() Philippe Mathieu-Daudé
2025-10-10 18:47 ` Richard Henderson
2025-10-14 5:01 ` Alistair Francis
2025-10-10 15:50 ` [PATCH 05/13] target/riscv: Conceal MO_TE within gen_load() / gen_store() Philippe Mathieu-Daudé
2025-10-10 18:47 ` Richard Henderson
2025-10-14 5:02 ` Alistair Francis
2025-10-10 15:50 ` [PATCH 06/13] target/riscv: Conceal MO_TE within gen_load_idx() / gen_store_idx() Philippe Mathieu-Daudé
2025-10-10 18:48 ` Richard Henderson
2025-10-14 5:03 ` Alistair Francis
2025-10-10 15:50 ` [PATCH 07/13] target/riscv: Conceal MO_TE within gen_fload_idx() / gen_fstore_idx() Philippe Mathieu-Daudé
2025-10-10 18:49 ` Richard Henderson
2025-10-14 5:05 ` Alistair Francis
2025-10-10 15:50 ` [PATCH 08/13] target/riscv: Conceal MO_TE within gen_storepair_tl() Philippe Mathieu-Daudé
2025-10-10 18:49 ` Richard Henderson
2025-10-14 5:06 ` Alistair Francis
2025-10-10 15:50 ` [PATCH 09/13] target/riscv: Conceal MO_TE within gen_cmpxchg*() Philippe Mathieu-Daudé
2025-10-10 18:50 ` Richard Henderson
2025-10-14 5:07 ` Alistair Francis
2025-10-10 15:50 ` [PATCH 10/13] target/riscv: Conceal MO_TE|MO_ALIGN within gen_lr() / gen_sc() Philippe Mathieu-Daudé
2025-10-10 18:51 ` Richard Henderson
2025-10-14 5:08 ` Alistair Francis
2025-10-10 15:50 ` [PATCH 11/13] target/riscv: Factor MemOp variable out when MO_TE is set Philippe Mathieu-Daudé
2025-10-10 16:18 ` Heinrich Schuchardt
2025-10-14 5:11 ` Alistair Francis
2025-10-10 15:50 ` [PATCH 12/13] target/riscv: Introduce mo_endian() helper Philippe Mathieu-Daudé
2025-10-10 16:35 ` Heinrich Schuchardt
2025-10-10 18:52 ` Richard Henderson
2025-10-14 5:13 ` Alistair Francis
2025-10-10 15:50 ` [PATCH 13/13] target/riscv: Introduce mo_endian_env() helper Philippe Mathieu-Daudé
2025-10-10 16:38 ` Heinrich Schuchardt
2025-10-14 5:15 ` Alistair Francis
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